JPS6359313B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field to which the invention pertains) The present invention relates to an interframe encoding device that performs highly accurate prediction of an image displayed after a subject moves and encodes the image with high efficiency.

(Prior Art) An interframe coding method is a method for highly efficient coding using interframe correlation of a video signal. The interframe coding method uses the pixel value of one frame before as the predicted value of the input video signal,
The prediction error is encoded and transmitted, and it is assumed that the movement of the image is small, and is intended for situations such as video conferences where the movement of the subject is small. For this reason, if the motion of the image is large, predictions will not be accurate and encoding efficiency will decrease.

A motion-compensated interframe coding method is available as a method for increasing prediction accuracy even when motion is large. In this method, the input signal is divided into blocks of a predetermined size, for example, 7 lines x 7 images, and for this block, a block at the same position one frame before, or ±m lines vertically (for example, m= 1
~6) and ±n pixels in the left and right direction (e.g. n=1~
6) Extract blocks at shifted positions and select the block with the smallest prediction error between it and the input signal.

As described above, the conventional interframe coding method has the disadvantage that the coding efficiency decreases for video signals with large motion. Furthermore, the motion compensated interframe coding method, which encodes with high efficiency even when there is a large amount of motion, requires a large number of high-speed calculations to detect the optimal prediction block, resulting in a large equipment size and a high price. It had the disadvantage of being expensive.

In addition, there are also methods that use background memory for the background that appears after the movement of a person (for example,
157696), but this only stores the background and does not have the concept of sequentially correcting the contents of the background memory according to changes in the background to improve prediction accuracy.

Additionally, there is currently no way to gradually compensate for changes in camera switching or brightness in a conference room, and this has the drawback of being unable to respond without consciously rewriting the background memory.

Furthermore, although it is important to predict the background that appears after movement, no suitable means has been found so far, and high-efficiency encoding has not been achieved.

(Objective of the Invention) In order to eliminate such drawbacks, the present invention installs a frame memory for the background and performs predictive coding of the background displayed after a person moves with high precision. Explain in detail.

(Structure and operation of the invention) FIG. 1 is a block diagram showing the structure of an embodiment of the invention, in which in the transmitting section, 1 is a video input terminal, 2 is a low-pass filter that limits the band of the input signal, 3 is a synchronous separation circuit that separates a synchronous signal from the output of the low-pass filter 2; 4 is a synchronous separation circuit that generates various clock information phase-synchronized with the output of the synchronous separation circuit 3;
A clock generation circuit outputs to each circuit requiring a clock; 5 is an A/D conversion circuit that converts the analog video signal output from the low-pass filter 2 into a digital signal; 6 is a predetermined output of the A/D conversion circuit 5; A preprocessing circuit that divides the data into blocks of size and outputs the data.
7 is a first storage circuit that stores the encoded/decoded processed image; 8 is a second storage circuit that stores the background image; 9 is a prediction circuit for the input signal supplied from the preprocessing circuit 6; The block with the smaller error is assigned to the first memory circuit 7 and the second memory circuit 8.
An optimal prediction block detection circuit 10 detects the signal of the corresponding block from among the outputs of the first storage circuit 7 and the second storage circuit 8 based on the output of the optimal prediction block detection circuit 9. 11 is a subtraction circuit that subtracts the output of the selection circuit 10 as a predicted value from the output of the preprocessing circuit 6 and outputs a prediction error; 12 is the output of the subtraction circuit 11; 13 is a code assignment circuit that assigns a predetermined code to the output of the prediction error processing circuit 12 and the output of the optimal prediction block detection circuit 9;
14 is an address information generation circuit that generates information representing a position on the screen, that is, an address in response to the output of the code assignment circuit 13; 15 is a correspondence between the contents of the first storage circuit 7 and the second storage circuit 8 and the receiving section, respectively; an error control information sending circuit that sends out information for matching the contents of the storage circuit with the contents of the storage circuit; 16 is an encoding information generating circuit that generates information representing the encoding control state;
17 is a multiplexing circuit which takes timing with the output of the clock generation circuit 4 and multiplexes the outputs of the code allocation circuit 13, the address information generation circuit 14, the error control information transmission circuit 15 and the encoded control information generation circuit 16 in a time division manner; 18 is a buffer memory that temporarily stores the output of the multiplex circuit 17 and reads it out using the output clock of the transmission clock generation circuit 19; 20 is the buffer memory 1;
A frame configuration circuit 21 configures a transmission frame for the output of the frame configuration circuit 20, a digital interface 21 converts the output of the frame configuration circuit 20 into a transmission path code, for example, an AMI code, and sends it out to a digital transmission path via a data output terminal 22; , 23 is an addition circuit that adds the output of the prediction error processing circuit 12 and the output of the selection circuit 10 to output a locally decoded signal, and 24 is a background detection circuit that detects the background of the image based on the output of the prediction error processing circuit 12. , 25 is the addition circuit 23
This is a storage control circuit that receives the output of the second storage circuit 8, corrects the pixel value of the area designated by the output of the background detection circuit 24, and outputs the corrected pixel value.

On the receiving side, 26 is a data input terminal, 27
28 is a digital interface that receives an input transmission path code, such as an AMI code, and converts it into a signal that can be decoded, such as a unipolar signal; 28 receives the output of the digital interface 27 and regenerates the transmission path clock; A clock regeneration circuit that regenerates various clock signals necessary for decoding, 2
9 is a frame disassembly circuit for disassembling transmission frames from the output of the digital interface 27;
0 temporarily stores the output of the frame decomposition circuit 29,
A buffer memory 31 reads out stored data according to the decoding speed, and a word identification circuit 3 identifies address information from the output of the buffer memory 30.
3, an address information identification circuit 32 identifies error control information from the output of the buffer memory 30, and supplies this information to a third storage circuit 35, a storage control circuit 40, and a first storage circuit 7 of the transmitting section, which will be described later. , a control information identification circuit that supplies the storage control circuit 25 and the error control information sending circuit 15, identifies control information for decoding, and supplies it to each circuit necessary for decoding;
33 is a word identification circuit 34 that identifies information representing the optimal prediction block from the output of the buffer memory 30 and outputs it to a selection circuit 37 to be described later, and also identifies a word representing a prediction error and outputs it to the prediction error decoding circuit 34; is a prediction error decoding circuit that receives the output of the word identification circuit 33 and decodes the prediction error;
35 is a third storage circuit that stores decoded images; 36 is a fourth storage circuit that stores background images;
37 is a selection circuit that selects and outputs the signal of the block specified by the output of the word identification circuit 33 from among the outputs of the third storage circuit 35 and the fourth storage circuit 36; 38 is the output of the selection circuit 37; and the output of the prediction error decoding circuit 34 to output a decoded signal; 39 is a background detection circuit that detects the background based on the output of the prediction error decoding circuit 34; 40 is the fourth
A memory control circuit 41 receives the outputs of the memory circuit 36 and the adder circuit 38, corrects and outputs the pixel values in the area designated by the output of the background detection circuit 39, and 41 receives the outputs of the adder circuit 38, rearranges them, and removes noise. A post-processing circuit that performs processing such as removal, 42 is a post-processing circuit 4
A D/A conversion circuit 43 converts the digital signal supplied from 1 to an analog signal, and 43 is a low-pass filter that band-limits the output of the D/A conversion circuit 42 and outputs it to a video output terminal 44.

Next, these operations will be explained. Video signal input from video input terminal 1, e.g. NTSC
The signal is limited to a predetermined band, for example 4.2MHz, by a low-pass filter 2 and an A/D conversion circuit 5, and is converted to 4f _SC (f _SC
is sampled at the frequency (subcarrier frequency),
For example, each sample is encoded into an 8-bit digital signal and supplied to the preprocessing circuit 6.

FIG. 2 is a diagram showing an example of the configuration of the preprocessing circuit 6, in which 601 is a color separation TDM circuit, 602 is a noise removal circuit, and 603 is a scan conversion circuit. The present invention is directed to a composite signal composed of a luminance signal and a color signal, such as an NTSC signal or a PAL signal, as an input signal. In such a signal, the subcarrier modulated by the chrominance signal is frequency multiplexed into the high frequency range of the luminance signal, and the phase of this subcarrier is shifted by 180° for each frame, so the frame is processed as is. Even if the difference between data is encoded, it cannot be encoded with high efficiency. The color separation TDM circuit 601 is a circuit for converting the signal format to enable high-efficiency encoding, and separates the luminance signal Y and two color signals C ₁ and C ₂ (for example, I signal and Q signal). Then, the time-compressed color signal is time-division multiplexed during the blanking period of the luminance signal.

Figure 3 shows the output of the color separation TDM circuit 601.
FIG. 2 is a diagram showing the relationship between the TDM signal format and sample points, where a shows the signal of one horizontal scanning line of the NTSC signal, and b shows the TDM color TV signal format.

There are 455 samples per line, and the first 7 samples transmit the amplitude value of the color burst, followed by 63 samples.
The color signal and luminance signal are transmitted using 385 samples and 385 samples, respectively. Here, the _C1 signal is transmitted only for odd lines, and the _C2 signal is transmitted only for even lines.
Furthermore, the C ¹ and C ² signals divide the sample values of odd lines into two odd and even lines and send them out.

The noise removal circuit 602 can be realized by the circuit configuration of a normal noise reducer. That is, minute frame time differences are regarded as noise and suppressed.

The scanning line conversion circuit 603 is composed of memories for a plurality of lines.

FIG. 4 shows the format of input/output signals of the scan conversion circuit 603, where a indicates the output of the noise removal circuit 602, and b indicates the scan conversion output.

In this example, scan conversion is performed between seven lines, and the output of the noise removal circuit 602 is sequentially written into the memories from the first line to the seventh line as shown in a. As shown in column b of the scan conversion output, the written data consists of samples arranged in the vertical direction as X ¹ ₁ , X ² ₁ ,
...Read out in the order of X ⁷ ₁ , X ¹ ₂ , X ² ₂ , X ⁷ ₂ , and X ³ ₁ . However, m in X ^m _o is a line number and n is a sample number.

This scan conversion has a memory for 14 lines, and during the 7-line period in which it is written to the 7-line memory, it is read from the other 7-line memory, and in the next 7-line period, it is read from the memory to which it is written. This can be achieved by switching memory. After the scan-converted data is delayed by a predetermined time, it is sent to the optimal prediction block detection circuit 9 and the subtraction circuit 11.

The first storage circuit 7 stores an image of one frame before, that is, the foreground. The second memory circuit 8 stores the background.

The optimal prediction block detection circuit 9 receives the signal from the preprocessing circuit 6 as an input signal, and receives the outputs of the first storage circuit 7 and the second storage circuit 8 as prediction signals. Among these signals, prediction errors are measured for blocks at the same position on one screen, and information specifying the storage device with the smaller prediction error is output.

FIG. 5 is a block diagram showing an example of the configuration of the optimal prediction block detection circuit 9.
03 is a parallel expansion circuit, 904 is a prediction error accumulation circuit, and 905 is an optimal block detection circuit.

The signals supplied from the preprocessing circuit 6, the first storage circuit 7 and the second storage circuit 8 all have the same format and are input in the format of the scan conversion output shown in FIG. 4b. These are parallel expansion circuits 90
1,902,903, it is converted into 7-sample parallel data of X ¹ _i . . . X ⁷ _i . These parallel expansion circuits can be realized by shift registers capable of parallel output, and their outputs are supplied to the prediction error circuit 904.

FIG. 6 is a diagram for explaining the operation of the prediction error accumulation circuit 904, and the vertical column is the parallel expansion circuit 904.
The horizontal column represents the line number within the block of the output of parallel expansion circuits 902 and 903. The prediction error is calculated between the pixel values at the intersection points marked with 〇 marks, and the result is 7, which is connected by a thick line.
Accumulate the prediction errors for the two intersection points.

FIG. 7 shows a configuration example of the prediction error accumulating circuit 904 for the seven intersections shown in FIG.
ROM, 944 is an adder circuit, 945 is a flip-flop, and the number inside △ in the figure indicates the number of bits.
The subtraction circuit 941 subtracts the input data supplied from the parallel expansion circuit 901 using the output of the parallel expansion circuit 902 or 903 as a predicted value, and outputs a prediction error. The ROM 942 outputs "1" when the absolute value of the output of the subtraction circuit 941 is greater than a predetermined threshold value, and "0" otherwise. ROM943 decodes the output of ROM942. That is, a number that is "1" among the 7-bit input is decoded, and the number is expressed as, for example, a two's complement number and output. Addition circuit 94
4 and flip-flop 945 constitute an accumulation circuit. The contents of the flip-flop 945 are reset at the beginning of a block consisting of 49 samples (7 lines x 7 samples), and thereafter the outputs thereof are added together by an adder circuit 944. Therefore, the adder circuit 944
The outputs SF and PF at the end of the block represent the number of samples in the block whose prediction error was greater than or equal to a predetermined threshold. With this SF
Compare the PF values and choose the smaller block as the optimal block.

In this embodiment, the method of accumulating the number of samples for which the absolute value of the prediction error is equal to or greater than a predetermined threshold has been described, but in addition to this, there is also a method of accumulating the absolute value of the prediction error,
There is also a method of comparing the accumulated values for each block and determining the block with the smallest accumulated value as the optimal prediction block. At this time, the ROM 942 is replaced with an absolute value circuit, and the ROM 943 is replaced with an addition circuit.

There is also a method of accumulating the root mean square value of prediction errors and comparing the magnitude of the accumulated values for each block to identify the optimum block. At this time, the ROM 942 is replaced with a mean square circuit, and the ROM 943 is replaced with an addition circuit.

The output SF (accumulated prediction error value in the background block) and PF (accumulated prediction error value in the foreground block) shown in FIG. 7 are compared in the optimal block detection circuit 905, and the smaller one is Outputs information specifying. This circuit can be implemented using a comparison circuit.

The selection circuit 10 selects and outputs the designated data from the outputs of the first storage circuit 7 and the second storage circuit 8 based on the output of the optimal predicted block detection circuit 9.

The prediction error outputted by the subtraction circuit 11 is quantized into representative values of, for example, 15 levels in the prediction error processing circuit 12 based on predetermined quantization characteristics.

Although a case has been described here in which the prediction error processing circuit 12 is composed of a quantization circuit, it is also possible to include a frame difference suppression circuit/expansion circuit.

FIG. 8 shows an example of the configuration of the prediction error processing circuit 12, in which 121 is a suppression circuit, 122 is a quantization circuit, 1
23 is an expansion circuit. The prediction error supplied from the subtraction circuit 11 is suppressed in a suppression circuit 121 based on predetermined nonlinear characteristics. Several types of characteristics are prepared and controlled according to the storage capacity of the buffer memory 18. The larger the amount of memory, the higher the suppression rate characteristics are switched to. At this time, it is also possible to distinguish the characteristics based on the color signal and the luminance signal. The suppressed data is quantized in a quantization circuit 122 based on predetermined characteristics. In this case, it is also possible to switch the characteristics depending on the storage capacity of the buffer memory. The quantized data is sent to the code allocation circuit 13 and expanded in the expansion circuit 123 based on the inverse characteristics of the suppression circuit 121. The suppression circuit 121, the quantization circuit 122, and the expansion circuit 123 can all be implemented using a ROM.

Furthermore, as another embodiment, it is also possible to replace the quantization circuit 122 with a previous value DPCM circuit.
In this case, the inter-frame difference value is further subjected to intra-frame previous value DPCM processing, resulting in inter-frame composite prediction.

As yet another embodiment, the prediction error processing circuit 12
It is also possible to configure it with an orthogonal transform encoding circuit.

FIG. 9 shows a configuration example of the prediction error processing circuit 12 in this case, in which 124 is an orthogonal transform circuit, 125 is a quantization circuit, and 126 is an orthogonal inverse transform circuit. The orthogonal transform circuit 124 can be configured using any method such as Hadamard transform or cosine transform. For example, to explain Hadamard transform, subtraction circuit 1
The data input from 1 is divided into blocks every n samples, and this block is transformed into a vector X=(x ₁ , x ₂
...... x _o ) ^t , and by orthogonal matrix A, Y=
Convert each component according to the AX relationship and send it to the quantization circuit 12
Quantize at 5. The quantization characteristic may be changed depending on the amount of information measured by the orthogonal transform circuit 124 or the amount of storage in the buffer memory 18. In the orthogonal inverse transform circuit 126, X=A ^T Y
Inversely transform and output according to the relationship.

Next, the code assignment circuit 13 will be explained.

FIG. 10 shows an example of the configuration of the code allocation circuit 13, in which 131 and 132 are encoding circuits, and 133 is a multiplexing circuit. The data supplied from the prediction error processing circuit 12 is divided into blocks every 49 samples, for example, and
When the values of all samples in a block are zero, it is considered an invalid block and output is prohibited. The other blocks are treated as valid blocks, and a predetermined variable length code is assigned to each sample data and output. supplying information representing the type of block to the address information generation circuit 14;
Here, one bit of "1" is outputted for the invalid block, and one bit of "0" is outputted for the valid block, and the multiplexing circuit 17 time-division multiplexes them onto the beginning of the block.

Here, we have described the case where data is transmitted in blocks, but there is also a so-called run-length method in which continuous numbers of zero values are transmitted as codes, and addresses of other values are transmitted as codes. There is a way. In this case as well, these address information generating circuits 14 output to the multiplexing circuit 17.

The information supplied from the optimal prediction block detection circuit 9 is “0” if this information specifies the foreground.
or “1” if the background is specified, in the encoding circuit 132. Multiplex circuit 13
3 time-division multiplexes the outputs of the encoding circuits 131 and 132 and outputs it to the multiplexing circuit 17.

The multiplexing circuit 17 time-division multiplexes the outputs of the code allocation circuit 13, address information generation circuit 14, error control information transmission circuit 15, and encoding control information generation circuit 16. The buffer memory 18 temporarily stores irregularly input data, and transmits the data to the transmission clock generating circuit 19.
Read with a constant clock provided by Transmission clock generation circuit 19, frame configuration circuit 20, and digital interface 21 are conventional circuits that can be easily implemented by those involved in this type of equipment.

The encoding control information generation circuit 16 detects the storage capacity of the buffer memory 18, and according to the storage capacity, 1
A coding mode such as sub-sample coding in which every sample is coded or field frame dropping in which every other field is coded is determined, and control information representing the mode is supplied to various necessary circuits.

Further, the data outputted from the prediction error processing circuit 12 is added to the output value of the selection circuit 10 in the addition circuit 23, and outputted to the first storage circuit 7 and the storage control circuit 25 as a local decoded signal.

Next, the background detection circuit 24 and storage control circuit 25, which are features of the present invention, will be explained. The background detection circuit 24 receives a value supplied from the prediction error processing circuit 12, and when this value is less than a predetermined threshold value, it considers it to be a background,
Background information "1" indicating that it is a background is output to the storage control circuit 25. This is the background detection circuit 24
In this example, the output of the threshold circuit is stored for a period of, for example, 6 frames, and the area in which it is "1" for 6 consecutive frames is regarded as the background. In some cases, background information may be output.

Furthermore, although the embodiment described above has been described in which the background area is identified in units of samples, there is also a case where the background area is identified in units of blocks of, for example, 7 lines x 7 samples. In this case, when all samples in a block are less than a predetermined threshold, this block is regarded as a background area and background information is output. In addition, in this embodiment, when all samples in a block are less than a predetermined threshold, the background is used, but in other embodiments, when the number of samples in a block that exceeds a predetermined threshold is less than or equal to a predetermined value, Consider this block as the background.

FIG. 11 shows an embodiment of the storage control circuit 25, in which 251 is a subtraction circuit, 252 is a difference discrimination circuit,
253 is an addition value control circuit, 254 is an addition circuit, 2
55 is a switch. The subtraction circuit 251 subtracts the output value of the second storage circuit 8 from the locally decoded value supplied from the addition circuit 23 and outputs the difference. The difference discrimination circuit 252 discriminates whether the output of the subtraction circuit 251 is zero, positive, or negative, and outputs discrimination information. The addition value control circuit 253 switches the output value according to the output of the difference discrimination circuit 252 when the output of the background detection circuit 24 is "1". That is, when the output of the difference discrimination circuit 252 is positive, +m (expressed with 8-bit accuracy)
m/256V), when negative, -m, when zero, 0
Output. Further, when the output of the background detection circuit 24 is "0", it outputs 0. The value of m is 1, for example. Further, when the data supplied from the encoding control information generation circuit 16 represents the sub-sampling mode, the addition value control circuit 253 outputs 0 during that video field period. Similarly, when representing the field frame drop mode, 0 is output for the field period during which the frame is dropped.

In the above example, the addition value control circuit 253 is connected to the background detection circuit 2.
4. Although the explanation has been given of a system that operates only in response to the outputs of the difference identification circuit 252 and the encoded control information generation circuit 16, the following configuration may also be possible.

FIG. 12 shows a configuration example of the addition value control circuit 253 in FIG. 11, in which 2531 is a counter, 2532
is an AND circuit, and 2533 is a ROM. The counter 2531 counts the frame pulses supplied from the clock generation circuit 4, and outputs, for example, "1" for one frame period as a control enable signal to permit execution of addition value control every n frames (n is, for example, 6). Output. When this signal is "0", even if the output of the background detection circuit 24 is "1", it is made "0" by the AND circuit 2532,
ROM2533 outputs 0. ROM2
Reference numeral 533 has the function of the addition value control circuit described with reference to FIG.

The output of the addition value control circuit 253 is sent to the addition circuit 254.
is added to the output of the second storage circuit 8,
The signal is supplied to the second storage circuit 8 via the switch 255. The time constant for modifying the contents of the second storage circuit 8 is determined by the values of m and n.

In the above embodiment, a case has been described in which one memory having a storage capacity for one frame is installed in the second storage circuit 8. In this case, the contents of the second memory circuit 8 for the background are corrected with a relatively short time constant, so if the person who is the subject is stationary, this person is also regarded as the background, and this signal is also used as the second memory circuit 8. memory circuit 8
will be remembered. As a result, the background will be displayed next time the person moves, but since the correct background signal is not stored in the second storage circuit 8, prediction accuracy cannot be improved.

In order to improve this drawback, some embodiments include a plurality of background memories. One memory is, for example, 6
There is also a method in which modification control is allowed for every frame (n=6), and the other memory is set to n=∞ as an extreme example, and the background is written once when the power is turned on and is retained.

The switch 255 in FIG. 11 is used to prevent errors in the transmission path and to start up the device when the power is turned on, and will be explained together with the error control information sending circuit 15.

The error control information sending circuit 15 is connected to the first storage circuit 7
It is supplied with parity information of the stored data constituted by the receiver, and sends it out to the receiving side via the multiplexing circuit 17. This parity information is received by the receiving section of the communication partner device, and is compared there with the parity information of the stored data in the storage circuit of the receiving section. When the power is turned on, the data stored on the transmitting side and the data stored on the receiving side are different, so a mismatch occurs when the parity information is compared. For this reason, the receiving side sends demand refresh information to the transmitting side requesting a refresh of the stored data since the parity information does not match. This demand refresh information is sent from the transmitter of the communication partner device and received by the receiver of the own device shown in FIG. This demand refresh information is identified by the control information identification circuit 32 in FIG.
5, and is sent to the storage control circuit 25. After receiving this demand refresh information, the first storage circuit 7 sets the output to a predetermined value, for example, 127/256V, for one frame period from the start of the next video frame, and performs a predetermined interframe encoding process. I do.
Information for identifying a frame with a value set, that is, memory set information, is sent from the error control information sending circuit 15 and received by the receiving section of the communicating party via the multiplexing circuit 17. Here, the received memory set information is detected, and the output of the storage circuit is set to the same predetermined value as that on the transmitting side for one video frame period following this information, for example, 127/
It is set to 256V and predetermined interframe decoding processing is performed. As a result, after one frame, the data stored on the transmitting side and the data stored on the receiving side completely match, and thereafter, even when the parity information of the stored data is checked, no mismatch occurs unless a transmission path error occurs.

In order to reduce the interval between occurrences of this demand refresh, it is also possible to install a circuit for performing error correction encoding and decoding on the encoded data to be transmitted.

In this embodiment, the case where the demand refresh is performed in units of one video frame has been described, but it may also be performed in units of blocks of a predetermined size.

Further, in this embodiment, the case where the stored data is set for one video frame period has been described, but the stored data is set by the method described above only for the first field period of the two fields constituting one frame, and then the stored data is set for the second field period. During the field period, predetermined encoding may be performed by switching to an inter-field encoding method that uses the locally decoded value for the first field as a predicted value.

The method for setting the first memory circuit 7 has been described above, and now the method for setting the second memory circuit 8 will be described. Setting of this circuit is performed by a switch 255 shown in FIG. Switch 25
5 starts from the video frame in which the first storage circuit 7 is set by the above-described demand refresh, and connects the data supplied from the adder circuit 23 for, for example, 30 frame periods. This eliminates the need for collation of parity information between the transmitter and receiver for the second storage circuit.

In the above embodiment, a case has been described in which a demand refresh method is used as a countermeasure against transmission errors.
For example, the contents of the storage circuit on the receiving side may be forced to match the contents on the transmitting side by periodically transmitting the stored data for one line per video frame. In addition, only the data stored in the first storage circuit 7 is periodically transmitted as described above,
The second memory circuit 8 may be set using the data of the first memory circuit 7 at predetermined regular intervals.

The transmitter has been described above in detail. The receiving section has the configuration shown in FIG. 1, and each section operates with a function opposite to that of the corresponding section of the transmitting section.

In the receiving section, the data decoded by the adding circuit 38 is subjected to predetermined processing by a post-processing circuit 41.

FIG. 13 shows an example of the configuration of the post-processing circuit 41.
411 is a scan conversion circuit, 412 is a noise removal circuit,
413 is a D/TDM and modulation circuit. The scan conversion circuit 411 performs inverse conversion of the scan conversion circuit 603 on the transmission side. The noise removal circuit 412 can be realized by the configuration of a normal noise reducer, and removes block-like noise generated due to motion compensation encoding. D.
The TDM and modulation circuit 413 separates the time-division multiplexed luminance signal Y and the color signals _{C 1} and C _{2 .}
After time-stretching the signal, it is converted to the same format as the input signal, ie, a composite signal such as an NTSC signal or a PAL signal. Its output is D/
The digital signal is converted into an analog signal in the A conversion circuit 42, and after being limited to a predetermined band in the low-pass filter 43, it is sent to the video output terminal 4.
Sent on 4th.

In the above description, the case where the block size is 7×7 has been described, but it can be similarly realized in the case of n×m blocks. In particular, in the case of a block of 1 line x m samples, the scan conversion circuit 603 and parallel expansion circuits 901, 902, and 903 are unnecessary.

(Effects) As explained above, the background predictive interframe coding device accurately performs predictive coding on the background displayed after the subject moves, so the second storage circuit that stores the background is controlled by the storage control circuit. The contents are corrected sequentially. That is, as a result of sequentially correcting the contents of the background memory in accordance with changes in the background, there is an advantage that high efficiency encoding or high quality can be achieved when a bit rate is specified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a configuration diagram of a preprocessing circuit, and FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention.
Figure 4 shows the format of the input/output signal of the scan conversion circuit. Figure 5 shows the configuration of the optimal prediction block detection circuit. Figure 6 shows the relationship between the TDM signal format and sample points. 7 is an explanatory diagram of the configuration of the accumulator circuit; FIGS. 8 and 9 are configuration diagrams of the prediction error processing circuit; FIG. 10 is an example of the configuration of the code assignment circuit;
12 shows an example of the configuration of the storage control circuit, FIG. 12 shows an example of the configuration of the addition control circuit, and FIG. 13 shows an example of the configuration of the post-processing circuit. 1...Video input terminal, 2, 43...Low-pass filter, 3...Synchronization separation circuit, 4...Clock generation circuit, 5...A/D conversion circuit, 6...Preprocessing circuit, 7...th 1 storage circuit, 8...second storage circuit, 9...optimal prediction block detection circuit, 10,3
7... Selection circuit, 11,251,941... Subtraction circuit, 12... Prediction error processing circuit, 13... Code assignment circuit, 14... Address information generation circuit, 15
...Error control information sending circuit, 16...Encoding control information generation circuit, 17, 133...Multiple circuit, 1
8, 30... Buffer memory, 19... Transmission clock generation circuit, 20... Frame configuration circuit, 2
1, 27...Digital interface, 22...
...Data output terminal, 23, 38, 254, 944
... Addition circuit, 24, 39 ... Background detection circuit, 2
5, 40...Storage control circuit, 26...Data input terminal, 28...Clock regeneration circuit, 29...Frame decomposition circuit, 31...Address information identification circuit,
32... Control information identification circuit, 33... Word identification circuit, 34... Prediction error decoding circuit, 35... Third
memory circuit, 36... fourth memory circuit, 41...
Post-processing circuit, 42...D/A conversion circuit, 44...
Video output terminal, 121... Suppression circuit, 122,
125...quantization circuit, 123...expansion circuit, 1
24... Orthogonal transform circuit, 126... Orthogonal inverse transform circuit, 131, 132... Encoding circuit, 252...
Difference identification circuit, 253... Addition value control circuit, 25
5...Switcher, 411,603...Scan conversion circuit, 412,602...Noise removal circuit, 413...
...D/TDM and modulation circuit, 601...color separation
TDM circuit, 901, 902, 903... Parallel expansion circuit, 904... Prediction error accumulation circuit, 905...
...Optimal block detection circuit, 915-927...Vertical optimal block detection circuit, 942, 943, 25
33...ROM, 945...flipflop,
2531...Counter, 2532...AND circuit.

Claims (1)

[Scope of Claims] 1. An input video signal divided into blocks of a predetermined size is divided into blocks of a predetermined size, and for each block, both the background area and the foreground area of the previous frame stored in the first storage circuit 7 are divided into blocks of a predetermined size. In an interframe coding device that performs predictive coding using a signal of a block obtained from a containing image signal as a predicted value, in addition to the first storage circuit 7, the entire image of only the background is stored, and its contents are sequentially stored. A second memory circuit 8 to be corrected and a memory control circuit 25 for correcting the contents of the second memory circuit are provided, and the content obtained from the first memory circuit 7 is provided for each block of the input video signal divided into blocks. The optimum prediction block detection circuit 9 calculates the prediction error for the block at the same position on one screen among the signals of the input video signal obtained from the second storage circuit 8 and the block of the input video signal obtained from the second storage circuit 8. The prediction error in the foreground block is compared with the prediction error in the foreground block, the smaller memory circuit is determined to be the optimal block, and the optimal block is selected as the predicted value and predictive coding is performed. Background predictive interframe coding device. 2 The background detection circuit 24 is connected to the prediction error processing circuit 12.
Claim 1, characterized in that the sample is configured to receive a value supplied from the sample, and when the value is less than a predetermined threshold value, it is regarded as a background, and information indicating that it is a background is outputted in units of samples. Background predictive interframe coding device as described. 3 The background detection circuit 24 is the prediction error processing circuit 12
When the values of all samples in a block of a predetermined size are less than a predetermined threshold value, the block is considered to be background, and information indicating that it is background is output for each block. 2. A background predictive interframe coding device according to claim 1. 4 The background detection circuit 24 is the prediction error processing circuit 12
When the number of samples in a block of a predetermined size whose value is less than a predetermined threshold is greater than or equal to a predetermined value, this block is considered to be the background. 2. The background predictive interframe coding device according to claim 1, wherein the background predictive interframe coding device is configured to output information representing each block. 5 The background detection circuit 24 is connected to the prediction error processing circuit 12.
It is characterized by being configured to receive data supplied from the computer, and when this data continues to be less than a predetermined threshold for a predetermined plurality of frames, it is regarded as a background and outputs information indicating that it is a background. A background predictive interframe coding device according to claim 1. 6. If the storage control circuit 25 includes a subtraction circuit 11 that subtracts the output of the second storage circuit 8 from the output of the addition circuit 23, and the output of the background detection circuit 24 indicates the background, the subtraction circuit The second storage circuit 8 stores predetermined positive and negative values corresponding to the positive and negative outputs of the outputs 11 and 11.
2. The background predictive interframe coding device according to claim 1, wherein the background predictive interframe coding device is configured to write the result into the second storage circuit 8 in addition to the output of the background predictive interframe coding device. 7. The memory control circuit 25 is configured to enable the memory control circuit 25 to modify the data stored in the second memory circuit 8 at predetermined intervals. Background predictive interframe coding device. 8. The background predictive interframe coding device according to claim 1, wherein the second storage circuit 8 includes a plurality of frame memories.