JPS6360429B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a shared resource management circuit that manages the use of shared resources such as a bus and memory that are commonly used by a plurality of devices.

[Background of the invention]

In general, a bus circuit, a common memory based on a multiprocessor control system, etc. exist as resources that are shared by a plurality of devices, such as a system control processing device. These shared resources are generally managed by a management circuit called a competition circuit, which is provided for each shared resource. The management method in this case is generally as follows.

(1) Each processing device that uses the shared resource sends a resource use request signal to the management circuit.

(2) The management circuit side selects a use request signal for one processing device from among the use request signals received during a certain period of time according to a predetermined selection procedure.

(3) Send the selected use request signal to one processing device as a use permission signal.

(4) Monitors the end of resource use of the device to which usage permission has been given, and upon completion performs the operations described in the preceding paragraph (2).During this time, the operations described in the preceding paragraph (1) are performed in parallel from other processing devices. Therefore, common resources are used one after another.

However, let us consider a case where the processing device becomes a failure. That is, there may be a situation where a shared resource use request signal is sent even though a failure has occurred. In this case, in the conventional shared resource management system, the shared management circuit operates in the same way as when the processing device is normal, and returns a usage permission signal. Thereafter, the usage limit time is exceeded without a resource usage termination command, and the shared resource management circuit terminates usage permission and considers the usage of the shared resource to be complete, resulting in an invalid operation. In general, the usage time limit value for shared resources is set to be larger than the normally long normal processing time, so the invalid usage time for shared resources is large, which leads to an increase in the waiting time of normal processing units, which in turn improves system performance. This is a big problem. For this reason, in conventional systems, a mechanism is provided on the management circuit side that prohibits the reception of usage requests for each device, and this circuit is controlled by a master processing device that manages failures in each processing device that makes up the system. It has been adopted.

However, depending on the system, the processing unit identification information on the hardware and the processing unit identification information on the software may be different, and the conversion between the two may be performed on the shared resource management circuit side or the software side. What I don't have. Furthermore, if this conversion algorithm cannot be unified in the system actually installed, a conversion table must be prepared on the software side, which increases the burden on the software.

Additionally, detecting non-implementation or failure of each processing device that makes up the system generally requires very complex processing, making programming difficult.
Moreover, it is difficult to correctly determine abnormal equipment, and the final decision is left to the maintenance personnel, so there is a problem that the normal equipment may no longer be able to perform the process by the time the maintenance personnel determines the abnormality, and such situations can be avoided. In order to eliminate this problem, maintenance personnel are required to relatively frequently inform the system of the status of the device configuration in the event of a change in mounting, a power outage, etc., making maintenance difficult.

[Purpose of the invention]

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a shared resource management circuit that reduces the burden on software and facilitates maintenance.

[Summary of the invention]

The present invention provides means for detecting an abnormality in a processing device that is using a shared resource in a shared resource management circuit, and when an abnormality is detected by the means, the identification information of the abnormal processing device is stored and the next step is performed. When a usage request is received from an abnormal device, the priority of the abnormal device is set lower than the priority of the normal device using the abnormal device identification information, and priority selection is performed. , power outages and failures are automatically detected by the shared resource management circuit, making it difficult to select an abnormal device. In addition, when the abnormal device becomes normal, the identification information of this device is removed from the abnormal device identification information, based on the fact that resource usage ends without abnormality when the abnormal device is selected. This method uses a method of setting the same priority level as for a normal device.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. The diagram targets a bus as a shared resource. In the figure, 1 ₁ , 1 ₂ , ... 1n are processing units connected in parallel to the common bus 3, and are connected to a load circuit and a central control unit (not shown).
It performs predetermined program processing.

Reference numeral 2 denotes a shared resource management circuit which is also a feature of this embodiment, and is for managing usage rights so that a plurality of processing devices 1 ₁ , 1 _{2 .} . . 1n can use the common bus 3 effectively. . This shared resource management circuit 2
has the function of selecting which processing device is to use the common bus 3 based on its output signal, and also has the function of immediately identifying any abnormality in the processing device.

FIG. 2 is a specific circuit block diagram of the shared resource management circuit 2 shown in FIG.
5 is a bus monitoring circuit for monitoring a processing device; 5 is a storage circuit for detecting an abnormality in a processing device; and, when an abnormality is detected, storing identification information of the abnormal processing device; 6;
Reference numeral 7 denotes a priority circuit that obtains the abnormal device identification information from the storage circuit 5, sets the priority of the abnormal processing device lower than the priority of the normal processing device, and then outputs the priority. 8 ₁ , 8 ₂ . . . 8n are OR gates provided at the output portions of the priority circuits 6 and 7.

To describe the configuration of the common resource management circuit 2 shown in FIG. 2 in more detail, the bus monitoring circuit 4 monitors the exchange of signals between the processing devices connected to the common bus 3 shown in FIG. When the end signal is detected, a normal output signal S is output, and when the end signal is not detected within a predetermined time, an abnormality detection signal F is output. Further, the bus use permission signals of the priority circuits 6 and 7 are inputted to the information storage circuit 5 for identifying an abnormal device via OR gates 8 ₁ , 8 ₂ . . . It is configured to accumulate information on processing devices that are currently being permitted. Also,
The bus monitoring circuit 4 is configured to use the normal output S to remove information on the currently permitted device from the accumulated abnormal device identification information. Also,
The output of the storage circuit 5 is input to priority circuits 6 and 7, and in response to a bus request from each processing device, the priority circuit 7 inputs the output from the priority circuit 6 without a permission signal, and disables the connection between abnormal devices. Priority selection is made. The bus use permission signals output from the priority circuits 6 and 7 are unified by OR gates 8 ₁ , 8 ₂ . . . 8n, and are sent back to each processing device.

In the same circuit configuration, the operation will be described when there is no abnormality in any processing device after the system starts operating. First, a bus use request is made from each processing device to the inputs of the priority circuits 6 and 7, but at this time, the outputs of the storage circuit 5 are all "0". Therefore, at the input of the priority circuit 6, the bus usage requests of all processing units are recognized, the normal priority selection is carried out, and a bus usage permission signal for one processing unit is returned, for example, via the OR gate ₈₂ . be done.

At this time, if the processing device (connected to the OR gate ₈₂ ) becomes abnormal, the bus end signal is no longer generated, so the bus monitoring circuit 4 obtains the output signal F, which is used to store abnormal device identification information. A bus permission signal is sent to the storage circuit 5 via the storage pulse and the OR gate ₈₂ (all signal lines are present, but only the signal line for the OR gate ₈₂ is at "1").
is input and stored as an abnormal device.

Next, a case will be described in which bus use requests are received from an abnormal processing device and a normal processing device. In this case, the distinction between abnormality and normality is made by the output of the storage circuit 5. For example, if it is (0, 1.0...0)
Then, the bus usage request is (1, 1, 0, 1.0...0)
Then, the first and fourth bus usage requests are input to the priority circuit 6, and the second bus request, which is the abnormal processing device, is
The th bus use request is input to the priority circuit 7. The priority circuit 6 selects, for example, the fourth bus use request, outputs permission to use the bus, and prohibits the operation of the priority circuit 7. Therefore, as long as there is a request to use the bus from a normal processing device, an abnormal processing device cannot use the bus.

Next, a case will be described in which a bus use request is received from an abnormal processing device. In this case, there is no bus use request input to the priority circuit 6, and therefore,
No operation prohibition signal is output from the priority circuit 6 to the priority circuit 7. Therefore, the bus use request from the abnormal processing device input to the priority circuit 7 is selected, and a bus use permission signal is sent back to the processing device via one of the OR gates 8 ₁ , 8 ₂ . . . 8n. . This results in the use of buses, but
When the use of the bus ends abnormally, the output F of the bus monitoring circuit 4 is outputted and is accumulated as an abnormality again as described above. However, when the use of the bus ends normally, the output S is outputted from the bus monitoring circuit 4. Then, the removal pulse and the processing device identification information to be removed are stored in the storage circuit 5.
The information that has been stored up to now is discarded.

Therefore, next time a bus use request is received from a processing device which has returned to normal operation as described above, it will be processed by the priority circuit 6 in the same manner as other normal processing devices. In other words, when an abnormal processing device is discovered,
Then, the use of the shared resource bus was prohibited,
This will eliminate unnecessary bus usage.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, not only the invalid use of shared resources by abnormal devices can be significantly reduced, but also the invention can There are advantages and effects such as ease of maintenance and management.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a circuit configuration of a shared resource management system showing an embodiment of the present invention, and FIG. 2 is a circuit block diagram specifically showing the main parts of FIG. 1. 1 ₁ , 1 ₂ ...1n...processing device, 2...shared resource management circuit, 3...shared bus, 4...bus monitoring circuit, 5...
Abnormal device identification information storage circuit, 6, 7...priority circuit,
8 ₁ , 8 ₂ ...8n...or gate.

Claims (1)

[Claims] 1 A shared resource management circuit that receives a request signal to use a resource commonly used by a plurality of devices from each of the devices and grants permission to use the resource to any one of the devices, the circuit means for detecting an abnormality in a given device; means for accumulating or eliminating identification information of an abnormal processing device when the abnormality detecting means detects an abnormality; and comparing the processing device identification information with the use request signal. , means for dividing the use request signal, and means for defining priorities between the divided groups of shared resource use request signals.