JPS6360532B2 - - Google Patents
Info
- Publication number
- JPS6360532B2 JPS6360532B2 JP56076553A JP7655381A JPS6360532B2 JP S6360532 B2 JPS6360532 B2 JP S6360532B2 JP 56076553 A JP56076553 A JP 56076553A JP 7655381 A JP7655381 A JP 7655381A JP S6360532 B2 JPS6360532 B2 JP S6360532B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- psg
- insulating film
- plasma
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
Landscapes
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
本発明は絶縁膜、特に半導体装置における層間
絶縁膜として好適なリンシリケートガラス膜(以
下、PSG膜と略記する)に関するものである。
この種のRSG膜を形成する方法として、常圧
CVD(化学的気相成長)法及び低圧CVD法が知
られている。常圧CVD法はバツチ処理式の自公
転装置を用いて実施されるが、得られたPSG膜
は特に段差部での被着性(ステツプカバレジ)が
悪い上に熱によりクラツクが入り易く、層間絶縁
膜としては致命的な欠陥を有していることが分つ
た。また、低圧CVD法によるPSG膜も絶縁耐圧
が不良であり、更に膜強度小、Alヒロツクとい
つた問題があり、層間絶縁膜として不適当である
ことが分つている。なお、PSG以外の絶縁膜に
は、プラズマデポジシヨン(析出法)による窒化
シリコン膜があるが、これを層間絶縁膜に用いる
と誘電率が大であつて分極を生じ、ダメージを受
け易いという欠点がある。
従つて、本発明の目的は信頼性に優れた絶縁膜
を形成することにあり、特に、完成状態の半導体
素子の表面を保護する保護膜(フアイナルパツシ
ベーシヨン膜)としてだけでなく、それより厳し
い条件が要求される層間絶縁膜についての上述し
た諸欠陥を解消することにある。つまり、層間絶
縁膜としては、ステツプカバレジが膜質及び形状
共に良好であり、熱処理時にクラツクが入らず、
絶縁耐圧も充分であつて例えば300V/0.6μm以
上のものを形成することにある。
このために、本発明によれば、プラズマデポジ
シヨンで絶縁膜、特にPSG膜を形成するもので
あるが、その際モノシラン等の水素化珪素と共に
酸化性ガスとしてCO2を使用することを特徴とし
ている。
本発明に到達する過程で、本発明者は本出願人
が既に提案した特願昭54−124100号による方法、
即ち、PH3−SiH4−N2O−Ar系を用いたPSG膜
のプラズマデポジシヨン法を検討した結果、
N2Oに代えてCO2を用いると、膜質をも含めたス
テツプカバレジ層間耐圧が特に改善され、高品質
で充分な強度のあるPSG膜を形成できることを
見出した。更に本発明者は、その反応ガス系にホ
スフイン(PH3)を混合せず、Si及びOを主体と
するガラス膜を成長させても、上記と同等に特性
良好な絶縁膜が得られることも見出した。
以下、本発明を図面の参照下で更に詳細に説明
する。
まず第1図について、本発明の方法を実施する
のに使用するプラズマデポジシヨン用のCVD装
置を例示する。この装置は石英製ベルジヤー1の
周囲に配された誘導コイル2でプラズマ励起を行
なうように構成された誘導コイル型プラズマ励起
方式になつている。ベルジヤー1内には、Al製
のシヤワー型下部電極3と、これに対向したステ
ンレス製の平板状上部電極4とが設置されてい
る。反応ガス系はPH3−SiH4−CO2(或いは比較
例としてN2O)−Ar
=からなつていて、このうち
PH3とSiH4はArを希釈ガスとして下部電極3の
下方から導入され、他方CO2(或はN2O)はベル
ジヤー1の底部から導入されてシヤワー電極3の
幅狭の貫通孔5を通じて上方の反応室7へ供給さ
れる。半導体ウエハ6はサセプタとしての上部電
極4において、その表面側を下方に向けてセツト
される。なお、8はRF発振器、9は半導体ウエ
ハ搬送駆動部である。反応室7内においては、供
給された反応ガスが夫々プラズマ励起され、ウエ
ハ6上にPSG膜が析出する。
上記のプラズマCVD装置によつて、半導体ウ
エハ6には第2図に例示する如きPSG膜又はSiO
膜10が析出せしめられる。このウエハ6にはリ
ニアICのバイポーラトランジスタを構成する各
半導体領域が予め形成されていて、11はP型シ
リコン基板、12はN-型エピタキシヤル層、1
3はN+型埋込み層、14は素子分離用のP+型ア
イソレーシヨン領域、15はN+型コレクタ電極
取出し用オーミツクコンタクト領域、16はP型
ベース領域、17はN+型エミツタ領域、18は
表面SiO2膜である。PSG膜又はSixOy膜10は、
各エミツタ電極19、ベース電極20、コレクタ
電極21をアルミニウム蒸着及びパターニングに
よつて形成した後に、上記プラズマCVDで全面
に成長せしめられる。22は2層目のアルミニウ
ム配線であつて、PSG膜又はSixOy膜10を層間
絶縁膜とする多層配線構造を形成している。な
お、1層目のアルミニウム電極19〜21及びそ
の配線膜厚1μm、幅6μm、配線間隔2μmとし、
PSG膜10の膜厚を0.8μmとし、更に2層目配線
22は膜厚1μm、幅10μm、配線間隔2μmとして
よい。
上記のプラズマCVDによる析出膜(PSG膜、
SixOy膜)の諸特性を他の常圧、低圧CVDによる
PSG膜と比較したデータを下記表に示した。こ
れによれば、プラズマデポジシヨンにより成長せ
しめられた析出膜は、熱応力が小さく、ステツプ
カバレジ、絶縁耐圧共に良好であつて、特に多層
配線構造における層間絶縁膜として優れているこ
とが分る。
The present invention relates to an insulating film, particularly a phosphosilicate glass film (hereinafter abbreviated as PSG film) suitable as an interlayer insulating film in a semiconductor device. As a method to form this type of RSG film, atmospheric pressure
CVD (chemical vapor deposition) methods and low pressure CVD methods are known. The atmospheric pressure CVD method is carried out using a batch-processing type rotation-revolution device, but the resulting PSG film has poor adhesion (step coverage), especially at step portions, is prone to cracks due to heat, and is prone to cracks between layers. It was discovered that the insulating film had a fatal defect. Furthermore, the PSG film produced by the low-pressure CVD method also has poor dielectric strength, low film strength, and problems such as Al hillocks, making it unsuitable as an interlayer insulating film. Insulating films other than PSG include silicon nitride films made by plasma deposition, but when used as interlayer insulating films, they have the disadvantage of having a high dielectric constant, causing polarization, and being easily damaged. There is. Therefore, an object of the present invention is to form an insulating film with excellent reliability, and in particular, it can be used not only as a protective film (final protection film) to protect the surface of a semiconductor element in a completed state, but also as a The object of the present invention is to eliminate the above-mentioned defects in interlayer insulating films that require more severe conditions. In other words, as an interlayer insulating film, the step coverage is good in both film quality and shape, and there are no cracks during heat treatment.
The dielectric strength is also sufficient, for example, 300 V/0.6 μm or more. To this end, according to the present invention, an insulating film, particularly a PSG film, is formed by plasma deposition, and the feature is that CO 2 is used as an oxidizing gas together with silicon hydride such as monosilane. There is. In the process of arriving at the present invention, the present inventor discovered the method according to Japanese Patent Application No. 124100/1983, which the present applicant had already proposed,
That is, as a result of examining the plasma deposition method of PSG film using PH 3 −SiH 4 −N 2 O−Ar system,
We have found that when CO 2 is used in place of N 2 O, the step coverage interlayer breakdown voltage including film quality is particularly improved, and a PSG film of high quality and sufficient strength can be formed. Furthermore, the present inventor has also found that an insulating film with properties as good as those described above can be obtained even if a glass film containing Si and O as the main component is grown without mixing phosphine (PH 3 ) into the reaction gas system. I found it. Hereinafter, the present invention will be explained in more detail with reference to the drawings. First, referring to FIG. 1, a CVD apparatus for plasma deposition used to carry out the method of the present invention is illustrated. This device is of an induction coil type plasma excitation system configured to excite plasma using an induction coil 2 disposed around a quartz bell gear 1. Inside the bell gear 1, there are installed a shower-type lower electrode 3 made of Al and a flat plate-shaped upper electrode 4 made of stainless steel facing thereto. The reaction gas system consists of PH 3 −SiH 4 −CO 2 (or N 2 O as a comparative example) −Ar =.
PH 3 and SiH 4 are introduced from below the lower electrode 3 using Ar as a diluent gas, while CO 2 (or N 2 O) is introduced from the bottom of the bell gear 1 through the narrow through hole 5 of the shower electrode 3. It is supplied to the upper reaction chamber 7. The semiconductor wafer 6 is set on the upper electrode 4 as a susceptor with its front side facing downward. Note that 8 is an RF oscillator, and 9 is a semiconductor wafer transport drive section. Inside the reaction chamber 7, each of the supplied reaction gases is excited by plasma, and a PSG film is deposited on the wafer 6. With the plasma CVD apparatus described above, the semiconductor wafer 6 is coated with a PSG film or SiO2 film as illustrated in FIG.
A film 10 is deposited. Each semiconductor region constituting a bipolar transistor of a linear IC is formed in advance on this wafer 6, and 11 is a P-type silicon substrate, 12 is an N - type epitaxial layer, and 1 is a P-type silicon substrate.
3 is an N + type buried layer, 14 is a P + type isolation region for element isolation, 15 is an ohmic contact region for taking out the N + type collector electrode, 16 is a P type base region, and 17 is an N + type emitter region. , 18 is a surface SiO 2 film. The PSG film or SixO y film 10 is
After each emitter electrode 19, base electrode 20, and collector electrode 21 are formed by aluminum vapor deposition and patterning, they are grown over the entire surface by the plasma CVD described above. Reference numeral 22 denotes a second layer of aluminum wiring, forming a multilayer wiring structure using a PSG film or Si x O y film 10 as an interlayer insulating film. In addition, the first layer aluminum electrodes 19 to 21 and their wiring film thickness is 1 μm, width is 6 μm, and wiring spacing is 2 μm,
The thickness of the PSG film 10 may be 0.8 μm, and the second layer wiring 22 may have a thickness of 1 μm, a width of 10 μm, and a wiring interval of 2 μm. The above plasma CVD deposited films (PSG film,
Characteristics of Si x O y film) by other normal pressure and low pressure CVD methods
The data compared with PSG membrane is shown in the table below. According to this, it can be seen that the precipitated film grown by plasma deposition has low thermal stress, good step coverage and dielectric strength, and is particularly excellent as an interlayer insulating film in a multilayer wiring structure.
【表】【table】
【表】
次に、上記のプラズマCVDによる折出膜に関
し、酸化性ガスの種類及びリン濃度に応じた
PSG膜のエツチング速度(エツチヤントは例え
ばバツフアHF)を第3図に示した。この結果か
ら、酸化性ガスがN2Oの場合よりCO2である方が
エツチング速度が大幅に小さく、また膜中のリン
濃度が低くなるにつれてエツチング速度が減少
(リンが0mol%で最小)することが分る。このこ
とは、本発明のようにCO2を使用するプラズマ
CVDによつて、得られたPSG膜又はSixOy膜
(例えばSiO膜)の耐エツチング性が充分となり、
上記第2図で示した2層目アルミニウム配線22
のパターニング(エツチング)工程時において侵
食され難くなる。また、上記表に示した他の
CVDによるPSG膜と比べても、エツチング速度
が小さくなることも分る。第4図には、反応ガス
中の酸化性ガス(オキサイドガス)の濃度による
PSG膜のエツチング速度が示されているが、CO2
を使用した場合、上記のように耐エツチング性が
増し、酸化性ガスの増量(リン濃度の減少)と共
にエツチング速度が低下することが分る。なお、
O2を使用すると更にエツチング速度が低下する
ようであるが、逆に反応が激しすぎて異物、欠陥
が増加して実際には使用るることが不可能であ
る。
なお、上記のデータから、本発明の方法におい
ては反応ガス組成として、ホスフイン(PH3)と
モノシラン(SiH4)との合計流量に対してCO2
を20〜40の割合で供給するのが望ましいことが分
つた。即ち、CO2が20未満であると、PSG膜中の
酸素含有量が少なくなつてPSGとしての化学量
論的組成比がくずれると共にエツチング速度も上
昇程度が大きくなり、またCO2が40%を越える
と、上記と同様にPSGの酸素含有量が多くなり
すぎてその化学量論的組成比がくずれてしまう。
従つて、CO2量はPH3+SiH4に対して20〜40とす
るのが好適である。
第5図には、熱処理(アニール)を施した場
合、各生成速度によるPSG膜の欠陥数クラツク
数)が示されている。これによれば、酸化性ガス
としてCO2を用いると、生成速度は遅いものの膜
中のクラツク数が大幅に減少していることが分
る。また、CO2を用いると熱処理前後においても
クラツク数は殆んど変化せずに共に非常に少ない
が、N2Oを用いる場合には欠陥数が著しく多い
上に熱処理条件で大きく変化している。
第6図には、CO2を用いる本発明のプラズマ
CVDによるPSG膜の絶縁耐圧を、その値毎のペ
レツト数(耐圧分布)で示した結果が示されてい
る。これによれば、上述の常圧CVDによるPSG
膜の耐圧が400V程度であるのに比較して、CO2
系のプラズマCVDによるPSG膜の耐圧が大幅に
向上している。
更に第7図には、本発明によるPSG膜の赤外
線吸収スペクトルが示されているが、これによれ
ば、Aの部分でP−O結合のピークがみられ、P
が充分に反応して結合していることが分り、非常
に良好なPSG膜が形成されている。
上述したように、本発明の方法によつて形成し
た絶縁膜は特に半導体デバイスに適用した場合、
次の如き顕著な効果を奏することが理解されよ
う。
(1) ステツプカバレジが良好であるから、電極又
は配線用のアルミニウム膜の段切れを防止で
き、歩留が向上する。
(2) 熱処理時にクラツクが入り難く、膜強度が大
きくなる。
(3) 層間絶縁膜として絶縁耐圧が充分となり、耐
圧不良をなくすことができる。
(4) 半導体チツプ又はウエハの信頼性が向上す
る。
(5) 酸化性ガスとしてCO2を用いるので、低コス
ト化が可能となる。
なお、本発明で得られた絶縁膜は上述した層間
絶縁膜としてだけでなく、フアイナルパツシベー
シヨン膜や、電気的に絶縁の必要な箇所に形成す
る絶縁膜としても用いることができ、その用途は
広いものである。[Table] Next, regarding the deposited film by plasma CVD described above, the
The etching rate of the PSG film (the etchant is, for example, buffer HF) is shown in FIG. From this result, the etching rate is much lower when the oxidizing gas is CO2 than when it is N2O , and the etching rate decreases as the phosphorus concentration in the film decreases (minimum at 0 mol% phosphorus). I understand. This means that plasma using CO 2 as in the present invention
By CVD, the etching resistance of the obtained PSG film or SixOy film (for example, SiO film) is sufficient,
Second layer aluminum wiring 22 shown in Figure 2 above
It becomes difficult to be eroded during the patterning (etching) process. In addition, other
It can also be seen that the etching rate is lower than that of the PSG film produced by CVD. Figure 4 shows the concentration of oxidizing gas (oxide gas) in the reaction gas.
The etching rate of the PSG film is shown, but CO 2
It can be seen that when phosphorus is used, the etching resistance increases as described above, and as the amount of oxidizing gas increases (the phosphorus concentration decreases), the etching rate decreases. In addition,
It seems that the etching rate is further reduced when O 2 is used, but on the other hand, the reaction is too violent and foreign matter and defects increase, making it impossible to actually use it. Furthermore, from the above data, in the method of the present invention, the reaction gas composition is CO 2 relative to the total flow rate of phosphine (PH 3 ) and monosilane (SiH 4 ).
It has been found that it is desirable to supply 20 to 40 parts of That is , if CO 2 is less than 20%, the oxygen content in the PSG film will decrease, the stoichiometric composition ratio as PSG will collapse, and the etching rate will also increase to a large extent. If it exceeds this, the oxygen content of PSG will become too large and its stoichiometric composition will be disrupted, as described above.
Therefore, it is suitable that the amount of CO 2 is 20 to 40 relative to PH 3 +SiH 4 . FIG. 5 shows the number of defects (cracks) in the PSG film at each generation rate when heat treatment (annealing) is performed. This shows that when CO 2 is used as the oxidizing gas, the number of cracks in the film is significantly reduced, although the generation rate is slow. Furthermore, when CO 2 is used, the number of cracks does not change much before and after heat treatment and is very small, but when N 2 O is used, the number of defects is significantly higher and changes greatly depending on the heat treatment conditions. . Figure 6 shows the plasma of the present invention using CO2 .
The results show the dielectric breakdown voltage of the PSG film produced by CVD, expressed as the number of pellets (withstand voltage distribution) for each value. According to this, PSG by the above-mentioned atmospheric pressure CVD
Compared to the membrane's withstand voltage of about 400V, CO 2
The withstand voltage of the PSG film has been significantly improved due to the plasma CVD system. Furthermore, FIG. 7 shows the infrared absorption spectrum of the PSG film according to the present invention, and according to this, a peak of P-O bond is seen in the part A, and P
It was found that the PSG film reacted sufficiently and bonded, and a very good PSG film was formed. As mentioned above, when the insulating film formed by the method of the present invention is applied to a semiconductor device,
It will be understood that the following remarkable effects are produced. (1) Good step coverage prevents breakage of the aluminum film for electrodes or wiring, improving yield. (2) Cracks are less likely to occur during heat treatment, increasing film strength. (3) The dielectric strength is sufficient as an interlayer insulating film, and breakdown voltage defects can be eliminated. (4) The reliability of semiconductor chips or wafers is improved. (5) Since CO 2 is used as the oxidizing gas, costs can be reduced. The insulating film obtained by the present invention can be used not only as the above-mentioned interlayer insulating film, but also as a final insulation film and an insulating film formed at locations where electrical insulation is required. It has a wide range of uses.
図面は本発明を例示するものであつて、第1図
はプラズマCVD装置の概略断面図、第2図は
PSG膜を層間絶縁膜として形成した半導体ウエ
ハの断面図、第3図はプラズマCVDによる析出
膜のリン濃度によるそのエツチング速度の変化を
示すグラフ、第4図はプラズマCVD時の反応ガ
ス組成によるPSG膜のエツチング速度の変化を
示すグラフ、第5図はプラズマCVDによるPSG
膜について熱処理温度と欠陥(クラツク)数との
関係を示すグラフ、第6図は本発明によるPSG
膜の絶縁耐圧分布を示すグラフ、第7図は本発明
によるPSG膜の赤外線吸収スペクトル図である。
なお、図面に用いられている符号において、2
は誘導コイル、3はシヤワー電極、4はサセプ
タ、6は半導体ウエハ、7は反応室、10は
PSG膜、19はエミツタ電極、20はベース電
極、21はコレクタ電極、22は2層目アルミニ
ウム配線である。
The drawings illustrate the present invention, and FIG. 1 is a schematic sectional view of a plasma CVD apparatus, and FIG. 2 is a schematic sectional view of a plasma CVD apparatus.
A cross-sectional view of a semiconductor wafer on which a PSG film is formed as an interlayer insulating film. Figure 3 is a graph showing the change in etching rate depending on the phosphorus concentration of the deposited film by plasma CVD. Figure 4 is a graph showing the change in etching rate of the PSG film as a function of the reaction gas composition during plasma CVD. A graph showing changes in film etching rate, Figure 5 shows PSG by plasma CVD.
A graph showing the relationship between the heat treatment temperature and the number of defects (cracks) for the film, Figure 6 is a PSG according to the present invention.
A graph showing the dielectric strength distribution of the film, and FIG. 7 is an infrared absorption spectrum diagram of the PSG film according to the present invention. In addition, in the symbols used in the drawings, 2
is an induction coil, 3 is a shower electrode, 4 is a susceptor, 6 is a semiconductor wafer, 7 is a reaction chamber, and 10 is a
In the PSG film, 19 is an emitter electrode, 20 is a base electrode, 21 is a collector electrode, and 22 is a second layer aluminum wiring.
Claims (1)
プラズマ化することによつて、Si及びOを含有す
るガラスからなる絶縁膜を基体上に形成するに際
し、前記酸化性ガスとしてCO2を使用することを
特徴とする絶縁膜の形成方法。 2 反応ガス中に所定量のホスフインを混合し、
これによつてリンシリケートガラス膜を形成する
ようにした、特許請求の範囲の第1項に記載した
方法。 3 ホスフインとモノシランとの合計流量に対し
て20〜40の容量比でCO2を供給する、特許請求の
範囲の第2項に記載した方法。[Scope of Claims] 1. When forming an insulating film made of glass containing Si and O on a substrate by turning a reactive gas containing silicon hydride and an oxidizing gas into plasma, the oxidizing gas A method for forming an insulating film, characterized in that CO 2 is used as an insulating film. 2 Mix a predetermined amount of phosphine into the reaction gas,
A method according to claim 1, whereby a phosphosilicate glass film is formed. 3. A method according to claim 2, in which CO2 is supplied in a volume ratio of 20 to 40 relative to the total flow rate of phosphine and monosilane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56076553A JPS57192032A (en) | 1981-05-22 | 1981-05-22 | Forming method for insulating film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56076553A JPS57192032A (en) | 1981-05-22 | 1981-05-22 | Forming method for insulating film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57192032A JPS57192032A (en) | 1982-11-26 |
| JPS6360532B2 true JPS6360532B2 (en) | 1988-11-24 |
Family
ID=13608443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56076553A Granted JPS57192032A (en) | 1981-05-22 | 1981-05-22 | Forming method for insulating film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57192032A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0419053B1 (en) * | 1989-08-31 | 1997-12-29 | AT&T Corp. | Dielectric film deposition method and apparatus |
| DE69231390D1 (en) * | 1991-06-10 | 2000-10-05 | At & T Corp | Anisotropic deposition of dielectrics |
| FR2704558B1 (en) * | 1993-04-29 | 1995-06-23 | Air Liquide | METHOD AND DEVICE FOR CREATING A DEPOSIT OF SILICON OXIDE ON A SOLID TRAVELING SUBSTRATE. |
| JP4533304B2 (en) * | 2005-11-29 | 2010-09-01 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
-
1981
- 1981-05-22 JP JP56076553A patent/JPS57192032A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57192032A (en) | 1982-11-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0015694B1 (en) | Method for forming an insulating film on a semiconductor substrate surface | |
| JP2682403B2 (en) | Method for manufacturing semiconductor device | |
| EP0572704B1 (en) | Method for manufacturing a semiconductor device including method of reforming an insulating film formed by low temperature CVD | |
| US4647472A (en) | Process of producing a semiconductor device | |
| JPH10335322A (en) | Method of forming insulating film | |
| JPH0766186A (en) | Anisotropic depositing method of dielectric | |
| EP1168425A2 (en) | Method for selectively etching a SiOF film | |
| JPS6360532B2 (en) | ||
| JPH04233731A (en) | Integrated circuit soluble oxide | |
| JP2702430B2 (en) | Method for manufacturing semiconductor device | |
| US7488693B2 (en) | Method for producing silicon oxide film | |
| JPH0964025A (en) | Method for manufacturing semiconductor device | |
| JPH08167601A (en) | Method for manufacturing semiconductor device | |
| JP2937998B1 (en) | Wiring manufacturing method | |
| JP3332063B2 (en) | Method for forming SiNx / PSG laminated structure | |
| JPH04343456A (en) | Manufacture of semiconductor device | |
| JPH0574763A (en) | Method for forming gate insulating film | |
| JP2002289609A (en) | Semiconductor device and manufacturing method thereof | |
| JPH05206282A (en) | Manufacturing method of multilayer wiring structure of semiconductor device | |
| JPH05335299A (en) | Fabrication of semiconductor device | |
| JPS626348B2 (en) | ||
| JPH04162428A (en) | Manufacture of semiconductor device | |
| JP2674654B2 (en) | Method for manufacturing semiconductor device | |
| JPH06132281A (en) | Method for manufacturing silicon oxide film | |
| TW516159B (en) | Method for forming insulating layer of integrated circuit |