JPS6360915B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frame display method for a display using a cathode ray tube.

Conventionally, when displaying a frame to draw a table, etc. on the screen of a display device using a cathode ray tube, various frame display patterns are programmed, and the corresponding program is read out and displayed on the screen of the cathode ray tube. The desired frame is displayed.

However, in such a device, all the frame display patterns must be stored as a program, which requires a large capacity program memory, and in order to draw a new frame display pattern, the program must be changed for the entire display pattern. There was a problem that the change operation was troublesome.

This invention was made in order to solve these problems, and it provides a frame display method for a display using a cathode ray tube, which can reduce the capacity of the program memory and make it easy to change the frame display pattern. The purpose is to provide.

Embodiments of the present invention will be described below with reference to the drawings.

1 is CPU (central processing unit), 2 is memory,
3 is a DMA (direct memory access) controller, 4 is a CRT (cathode ray tube) controller, and 5 is a CRT, that is, a cathode ray tube. The CPU 1 is electrically coupled to the memory 2 by an address bus 6 and a data bus 7, and is connected to the DMA controller 3 by a signal line 8.
and the CRT controller 4 through a signal line 9.
The memory 2 serves as an image data memory having a memory area in one-to-one correspondence with each section obtained by partitioning the screen of the CRT 5 into a plurality of sections vertically and horizontally.
A CRT register 201 is provided. Said
The DMA controller 3 has an address counter 10,
11, DMA transfers the block image data in the CRT register 201 to the refresh memory 12, and transfers line shading data, etc. to the memory 2.
DMA transfer is performed from there to the character modification memory 13. 14 is a clock pulse CP that determines the scanning timing of the pixel dots of the CRT 5.
The clock pulse CP from the oscillator 14 is converted by a dot counter 15 into a pulse with a cycle necessary for the clock pulse CP to scan one section and is supplied to the CRT controller 4, and the clock pulse CP is transferred to a shift register. 16 directly. Said
The CRT controller 4 drives the DMA request control circuit 17 and sends the request to the DMA controller 3.
Control to start DMA transfer, control to drive multiplexers 18 and 19 in synchronization with pulses from dot counter 15, control to drive character generator 20, and control to drive character generator 20;
Control is performed to drive the CRT5. The multiplexers 18 and 19 select the refresh memory 12 and the character modification memory 1 according to the contents of the address counters 10 and 11.
3 address control is performed. The segmented image data in the refresh memory 12 is converted into display pattern information by the character generator 20 and supplied to the video signal control circuit 21 via the shift register 16, and is also modified such as shading in the character modification memory 13. The information is supplied to the video signal control circuit 21 while being timed with display pattern information by a timing circuit 22. The video signal control circuit 21 supplies the CRT 5 with a desired video signal created from display pattern information and modification information. The CRT 5 is controlled by the CRT controller 4 to display the video signal from the video signal control circuit 21 on the screen.

Various frame display patterns each consist of a horizontal line parameter and a vertical line parameter, and the horizontal line and vertical line parameters each consist of a start address and line length data for a plurality of horizontal lines and vertical lines, and these are programmed. ing. Said
When the CPU 1 sets block image data of a certain framed display pattern in the CRT register 201, it performs processing based on the flowchart of FIG. First, a plurality of horizontal line section image data are set in the CRT register 201 based on the horizontal line parameters of the frame display pattern to be displayed. This brings in the start address and length data of the first horizontal line from the horizontal line parameters. In this case, the start address is an address indicating the section on the screen where the tip of the horizontal line is located, and the length data is data indicating how many sections the length of the horizontal line is. and CRT register 2 specified by the start address
Section image data set for a horizontal line is set in the memory area of a predetermined section 01. The block image data at this time is a code indicating the address of the horizontal line display pattern stored in the character generator 20. Then, when the first section image data is set, the horizontal line is composed of the same section image data consecutively horizontally for the length section, so
The same divided image data is continuously inserted into the memory area next to the memory area in which the divided image data is set. In this way, the block image data for one horizontal line is first transferred to the CRT register 2.
It will be stored in 01. Next, the start address and length data of the second horizontal line are obtained from the horizontal line parameters. Then, block image data for a horizontal line is set in a memory area of a predetermined block of the CRT register 201 specified by the start address, and the block image data for the horizontal line is continuously set in the memory area of the read length data in the memory area next to the memory area. Insert the same section image data. Regarding all horizontal lines of the frame display pattern that should be displayed in the same way from now on
Insert section image data into the CRT register 201. When the setting of section image data for horizontal lines in the CRT register 201 is completed, setting of section image data for vertical lines is then started. This first brings the start address and length data of the first vertical line from the vertical line parameters. Next, preparations are made to check the parameters of the next vertical line, and FLAG is set to "1" and LCODE is set to "0". Then, it is checked whether the brought length data is "0" or not. Since the length data is not "0" now, "1" is subtracted from the length data and it is checked whether "1" is set in FLAG. If FLAG=1, FLAG is cleared, and if FLAG≠1, it is checked whether the position corresponding to the position where a frame line is to be drawn is a frame line, as shown in a of FIG. 4. If the position is on the frame line, set the first bit of LCODE to "1". In other words, LCODE is b in Figure 4.
It is composed of 8 bits b ₀ to b ₇ shown in , and the b ₀ bit is set to “1”. After clearing FLAG, a check is made to see if the next vertical line is located at the left edge of the screen. If it is not at the left end, check whether the position shown in a in Figure 4 is on the frame line, and if the position is on the frame line,
Set the second bit of LCODE to “1”. i.e.
Set b ₁ = 1. Next, it is checked whether the next vertical line is located at the right edge of the screen. If it is not the right end, it is checked whether the position shown in a in FIG. 4 is a frame line, and if the position is a frame line, the third bit of LCODE is set to "1". That is, b ₂ =1. Next, it is checked whether the length data is "0" or not, and if it is not "0", the fourth bit of LCODE is set to "1".
In this way, b ₀ to _{b 3} of LCODE indicate 0 to F, and b ₄ to
_b7 indicates 0, and the LCODE indicates 00 to 0F. The LCODE determined in this way is referred to the frame pattern table shown in Figure 5 to determine the frame that should be included in the position, and the character code that draws that frame corresponds to the position.
Store at address of CRT register 201. The position is then set as the next position and prepared for the next frame selection check. The routine then returns to zero-checking the length data and performs the same process again. Therefore, for example, the third
When storing the block address image data shown in the figure, check the positions , , , , and the length data as shown in b ₀ in Figure 4.
= 1, b ₁ = 1, b ₂ = 1, b ₃ = 1, b ₄ to b ₇ = 0, and LCODE = OF. choose,
"+" in the corresponding address of CRT register 201
The character code for displaying the frame pattern of is stored as section image data. When the character code for the vertical line parameter has been stored in the CRT register 201, the CRT
The contents of the register 201 are DMA-transferred to the CRT refresh memory 12 by the DMA controller 3, and a frame pattern is displayed.

By doing this, what you need to program is the horizontal line, each horizontal line as a vertical line parameter, the start address and length data of each vertical line, the pattern code of the horizontal line, and the pattern code of 00 to OF for the frame of the vertical line. It is not necessary to program the frame display pattern for all sections, and the capacity of the program memory can be sufficiently reduced. In addition, when changing the frame display pattern, all you have to do is change the start address and length data for each horizontal line and each vertical line, making the change operation easy as there is no need to change the data for all sections of the display pattern. .

Furthermore, if you want to frame with vertical or horizontal lines,
Only lines in one direction are drawn before lines in the other direction. Therefore, since the lines drawn first do not intersect with each other, there is no need to check the data of each adjacent section during the drawing process. Therefore, the program required for framing can be simplified and processing efficiency can be improved.

As described in detail above, according to the present invention, when a plurality of lines are drawn on the screen of a cathode ray tube and are displayed in a frame, the screen of the cathode ray tube is partitioned into a plurality of sections vertically and horizontally. An image data memory having a memory area in one-to-one correspondence with each division is provided, and the division of each line is first determined from the start address and length data of each line for multiple lines in one direction. Image data is set for each section, and then the start address of each line is set for each section based on the length data for multiple lines in a direction perpendicular to each line in one direction, and the section image of the adjacent section is set for each section. A corresponding framing section pattern is selected from a plurality of preset framing section patterns while checking the presence or absence of data, and section image data of the selected framing section pattern is sequentially set. Frame display is performed on the screen based on the image data of each section in the image data memory, so the capacity of the program memory can be reduced and the frame display pattern can be easily changed using a cathode ray tube. It is possible to provide a frame display method for the display.

[Brief explanation of drawings]

The figures show an embodiment of the present invention. Fig. 1 is a block diagram, Fig. 2 is a flowchart showing the main processing, and Fig. 3 shows the storage state of data in the CRT register.
Figure 4 shows a diagram corresponding to a CRT screen. Figure 4 a shows the check position when storing one section of image data. Figure 4 b shows the LCODE determined by the position check in Figure 4. The figure shown in FIG. 5 is a diagram showing the relationship between the vertical line framing pattern and the LCODE. 1...CPU (central processing unit), 201...
CRT register, 3...DMA controller.

Claims (1)

[Claims] 1. When displaying a frame by drawing a plurality of lines perpendicular to each other vertically and horizontally on the screen of a cathode ray tube, the screen of the cathode ray tube is divided into a plurality of vertically and horizontally, and a memory area that corresponds one-to-one with the named divisions is provided. An image data memory having an image data memory is provided, and a segmented image of each line is first calculated from the start address and length data of each line for a plurality of lines in one of the vertical and horizontal directions. The data is set for each section, and then, based on the start address and length data of each line for multiple lines in the direction perpendicular to each line in the above one direction, for each section, the sections adjacent to that section are set. The presence or absence of section image data is sequentially checked,
Based on the check results, corresponding framing section patterns are sequentially selected from a plurality of preset framing section patterns, and section image data of the selected framing section patterns are sequentially set and displayed on the screen of the cathode ray tube. A frame display method for a display device using a cathode ray tube, characterized in that frame display is performed based on the image data of each section set in the image data memory.