JPS636138B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for growing silicon using a mass transfer reaction.

In the manufacturing process of semiconductor devices, it is sometimes necessary to grow a polycrystalline silicon layer on the surface of a semiconductor substrate and to perform etching or polishing on the back surface. For example, NPN type and
When manufacturing a complementary semiconductor device including both PNP type elements using the dielectric separation method, anisotropic etching is performed on a silicon substrate with a plane orientation of (100), selectively etching one main surface of the silicon substrate. After forming a groove by removing the silicon substrate to a predetermined depth, a silicon oxide film is formed on this one main surface, polycrystalline silicon is grown thereon, and then the back surface of the silicon substrate is polished. Through this process, as shown in FIG. 1, an element substrate is obtained in which island-like regions 2 and 2' made of silicon crystal are disposed on the surface of a polycrystalline silicon layer 1 and are insulated and separated from each other by a silicon oxide film 3. . Thereafter, NPN type and NPN type elements are formed in the island regions 2 and 2', respectively, to obtain a complementary semiconductor device.

The above-mentioned conventional method requires a large amount of man-hours because growing the polycrystalline silicon layer and polishing the back surface are separate processes, and there is a risk of damaging the substrate in the polishing process, so it is not always satisfactory. It's hard to say.

The purpose of the present invention is to solve the above-mentioned difficulties, and it is an object of the present invention to make it possible to simultaneously grow a silicon layer on one main surface of a semiconductor substrate and to perform etching on the other main surface. .

Therefore, in the method for manufacturing a semiconductor device of the present invention, a substrate to be processed made of silicon and a source substrate made of silicon are brought close to each other so that their principal surfaces face each other, and a silicon vapor phase etching reaction system (or growth reaction system) is performed. The temperature T ₁ of one principal surface of the source substrate and the temperatures T 2 and T 3 of one principal surface and the other principal surfaces of the substrate to be processed are adjusted such that _{T 1 >} T ₂ > _{T 3 (} or
T ₁ < T ₂ < T ₃ ), thereby causing a mass transfer reaction between one main surface of the substrate to be processed and one main surface of the source substrate. It is characterized by

The present invention will be explained in detail below using examples.

2 to 6 are sectional views and curved views of essential parts showing one embodiment of the present invention.

In this embodiment, an example of manufacturing a high breakdown voltage complementary bipolar semiconductor device will be described. A high-voltage semiconductor device requires a low concentration region in which the depletion layer greatly expands. In this example, NPN type and
The structure of PNP transistor is NPN ^- N ⁺ and
PNN ^- P ⁺ structure, both of the above low concentration regions
N ^- area. This N ^- region is composed of N ^- type silicon single crystal.

Therefore, first, as shown in Figure 2, the surface orientation (100)
One principal surface (upper surface in the figure) of the N ^- silicon substrate 11 is selectively removed by anisotropic etching using a potassium hydroxide (KOH) solution or the like to form a groove 12. In this way, a large number of plateau-like protrusions 13 and 13' surrounded by the groove 12 are formed on one main surface of the silicon substrate 11. Next, an N-type impurity such as arsenic (As) or phosphorus (P) is applied to the surface of the convex portion 13, and a P-type impurity such as boron (B) is applied to the surface of the convex portion 13' by ion implantation or vapor phase diffusion. N ⁺ layer 14 and P ⁺ layer 15 are selectively introduced using a method etc.
form. Next, a dielectric layer 16 made of silicon dioxide (SiO ₂ ) or the like is formed on one main surface of the silicon substrate 11 including the surfaces of the convex portions 13 and 13'. The process up to this point is no different from the conventional process.

As shown in FIG. 3, the element substrate 21 formed as described above is placed on a source substrate 22 made of silicon with a small piece of quartz 23 interposed therebetween, and then placed on a susceptor 24. At this time, the element substrate 21 has one principal surface on which the plateau-like protrusions 13 and 13' are formed facing downward, and by appropriately selecting the size of the quartz pieces 23, one principal surface of the element substrate 21 and the source substrate The distance between the main surface and the main surface is set to a desired value. In this example, this interval is approximately 300 [μ
m]. The susceptor used was a carbon base coated with silicon carbide (SiC), which is commonly used in epitaxial growth processes. Next, as described above, the susceptor 24 on which the element substrate 21 and the like are mounted is placed in the quartz tube 25, and hydrogen (H ₂ ) is introduced into the quartz tube 25 at a rate of 30
) and hydrochloric acid gas (HCl) at a rate of 3.5 [/min], and heated by high frequency heating method. Then, the susceptor 24 is heated by induction and its temperature increases, the source substrate 22 is heated by heat conduction from the susceptor 24, and the element substrate 21 is further heated mainly by radiation from the source substrate 22. As a result, the temperature of one principal surface of the source substrate 22, one principal surface of the element substrate 21 (lower surface in the figure), and the other principal surface (upper surface in the figure)
Let T ₁ , T ₂ , and T ₃ be the temperatures of T ₁ > T ₂
>T ₃ . In this example, T ₃ was adjusted to 1085 [°C].

As is well known, the above conditions are originally conditions for vapor phase etching of silicon (Si). Therefore, in the above state, the element substrate 21 made of silicon
Basically, an etching reaction progresses on the surface of the source substrate 22.

First, the other main surface of the element substrate 21 (the upper surface in the figure)
is etched by HCl in the atmosphere. That is, Si and HCl react as Si+HCl→SiCl ₄ , SiCl ₃ , SiH ₂ Cl ₂ , and the products such as SiCl ₄ are quickly discharged out of the system by the gas flow. Therefore, it can be considered that only the etching reaction proceeds on the other main surface of the element substrate 21, without causing a large change in the component composition ratio of the atmosphere within the system due to the reaction product.

A microspace formed by one main surface of the element substrate 21 (lower surface in the figure) and one main surface of the source substrate 22 (upper surface in the figure), which are arranged close to each other and have a temperature difference. Inside, the situation is slightly different. The etching reaction described above also proceeds on the two main surfaces, but since the space between these two main surfaces is minute, the composition of the atmosphere in the space is greatly influenced by the reaction products, and the quartz The composition will be significantly different from that of the atmosphere inside the pipe. In other words, within the microscopic space, the reaction products
As the concentration of SiCl ₄ etc. increases, a reaction (SiCl ₄ , SiHCl ₃ , SiH ₂ Cl ₂ )+H ₂ → Si+HCl occurs on one main surface of the element substrate 21 on the low temperature side of the two main surfaces, and the element Polycrystalline silicon grows on one main surface of substrate 21 . This is what is called a mass transfer phenomenon.

As described above, in this embodiment, a mass transfer reaction system space is formed within a silicon vapor phase etching reaction system space, and the element substrate 21 of the object to be processed is
This made it possible to grow polycrystalline silicon on one main surface while simultaneously etching the other main surface.

Figure 4 shows a hydrogen flow rate of 30 [/min] and an element substrate 21.
When the temperature T ₃ of the other main surface of is 1085 [℃],
The flow rate of HCl, the growth rate of polycrystalline silicon on one main surface of the element substrate 21 (solid line A) [μm/min], and the etching speed on the other main surface (dotted chain line B) [μ
m/min]. As seen in the figure, even if the temperature and hydrogen flow rate are constant, the growth rate and etching rate change depending on the HCl flow rate. The above-mentioned conditions used in this example are conditions in which both conditions substantially match. Therefore, the thickness of the element substrate 21 is approximately the same before and after the above-described growth and etching reaction treatment, which is convenient for handling the element substrate in subsequent steps.

Therefore, by carrying out the process until the bottom of the groove 12 is removed in the above step, N ^- type plateau-like protrusions 13, 13' are buried in the form of islands on the surface of the polycrystalline silicon layer 17, as shown in FIG. formed by
The same element substrate 21 as shown in FIG. 1 was obtained. (FIG. 5 is drawn upside down from FIG. 2.) Therefore, according to this embodiment, compared to the conventional process, a polishing step is not necessary, and therefore the number of man-hours is reduced, and the substrate to be processed is Therefore, the element substrate 21 is not mechanically damaged. Furthermore, since the substrate to be processed is heated mainly by radiation, the warpage is very small, and since etching proceeds simultaneously with the growth, no bulge (crown) of the grown layer occurs at the edge of the substrate to be processed.

The subsequent steps may be carried out according to normal manufacturing methods. That is, a P-type region (base) 31 is formed on the surface of the island-shaped N ^- type region 13, and an N-type region (emitter) is formed on the surface of the P-type region (base) 31.
32, further form the N ⁺ layer 33 which will be the contact part of the collector electrode connected to the N ⁺ layer 14 to form the NPN ^- N ⁺ structure.
An NPN transistor is configured. On the other hand, an N ^- type region 34 is formed on the surface of the island-like N-type region 13' to form an N ^- type region.
13' together with the base of the NN ^- structure, and furthermore, a P type region (emitter) 35 is formed on the surface of the N type region 34, and a P ⁺ layer 36 connected to the P ⁺ layer 15 is formed as a collector electrode contact part ^. A PNP transistor with a P ⁺ structure is constructed.

As described above, a high breakdown voltage complementary bipolar semiconductor device could be manufactured using the present invention.

Next, another embodiment of the present invention will be described using main part sectional views shown in FIGS. 7 to 9. This example is an IC, LSI
VIP (Vee Isolation with
This is an example of forming a polycrystalline silicon) structure.

First, as shown in FIG. 7, an SiO _{2 film 42 is grown on an n-type epitaxial layer 41' grown on the surface of a P-type silicon substrate 41 with a plane orientation of (100), and a silicon nitride film is deposited on the SiO 2} film 42 in accordance with a predetermined pattern. (Si ₃ N ₄ ) film 43 is formed and anisotropic etching is performed using this as a mask to form a V-shaped groove 44 that penetrates the epitaxial layer 41' and reaches the upper part of the silicon substrate 41.
will be established. Then, a heating oxidation treatment is performed on the surface of this V-shaped groove 44 to form a SiO ₂ film 45.

Next, a polycrystalline silicon layer 46 is grown on the surface of this silicon substrate 41, as shown in FIG. 8, using the same method as that used in the above-mentioned embodiment, but with a flow rate of HCl gas of about 1 [/min]. The only difference is that they are the same; everything else is the same. In the case of this embodiment, the purpose is to fill the groove 44 with polycrystalline silicon, and it is not essentially necessary to remove the back surface of the silicon substrate 41 by etching. Therefore, it is necessary to select the HCl gas flow rate in a region where the etching rate is smaller than the growth rate (see FIG. 4). For this reason, in this example,
The HCl gas flow rate was 1 [/min].

When this step is carried out by the usual chemical vapor deposition (CVD) method, as is well known, polycrystalline silicon thickly adheres to the peripheral edge of the silicon substrate, creating a crown. In contrast, in this example, the back side of the silicon substrate is etched at a low rate as described above, but since it is in the etching reaction system, polycrystalline silicon does not adhere to it, and even on the front side, the periphery of the silicon substrate is etched. Since the composition of the atmosphere near the tube is close to the composition of the atmosphere inside the tube, the etching reaction is dominant and the growth of polycrystalline silicon is suppressed. Therefore, according to this embodiment, a polycrystalline silicon layer without a crown can be obtained.

The subsequent steps may be carried out according to normal manufacturing methods. That is, the Si ₃ N ₄ film 43 is removed by polishing or the like.
The polycrystalline silicon layer 46 is removed to expose
Next, the surface of the polycrystalline silicon layer 46 is oxidized by a thermal oxidation method to form a thick SiO ₂ film 4 on the surface of the polycrystalline silicon layer 46 that fills the grooves, as shown in FIG.
7 is formed, and then the Si ₃ N ₄ film 43 is removed to form a VIP
The structure is completed.

The present invention is not limited to the above embodiments, but can be implemented with various modifications.

For example, in the above two examples, an atmosphere containing hydrogen (H ₂ ) as a carrier gas and hydrochloric acid (HCl) gas mixed therein was used to form the etching reaction system space. The atmosphere may be a mixture of other hydrogen halides, such as hydrogen fluoride (HF), hydrogen bromide (HBr), and hydrogen iodide (HI). In addition, the carrier gas is a rare gas such as helium (He) or argon (Ar),
An atmosphere in which silicon tetrachloride (SiCl ₄ ) or iodine (I ₂ ) vapor is mixed therein, or an atmosphere in which hydrogen (H ₂ ) and bromine (Br ₂ ) vapor are mixed can also be used.

Furthermore, although the above two embodiments have been described with reference to an example in which a mass transfer reaction system space is formed within an etching reaction system space, instead of this, a mass transfer reaction system space is formed within a growth reaction system space. It is also possible to implement the present invention. In that case, the following two points may be made different from the above two embodiments.

One is to change the atmosphere inside the tube to helium (He) and bromine (Br ₂ ) vapor, or hydrogen (H ₂ ) and chlorine (Cl ₂ ).
By making the gas mixture T ₁ < T ₂ < T ₃
That is to say. In order to make the temperature opposite to that of the two embodiments described above, the substrate to be processed may be heated by radiation from the upper surface side (upper side in FIG. 3) using an infrared lamp or an electric heater. In this case, growth progresses on the upper surface of the substrate to be processed (the surface exposed to the atmosphere inside the tube), and etching progresses on the lower surface (the surface that faces and approaches the source substrate).

Also in the above two embodiments, instead of the high frequency heating method, a method of heating from the source substrate side (lower side in FIG. 3) using an infrared lamp, electric heater, etc. may be used.

Further, in the above two embodiments, the source substrate and the susceptor were made separate, but it is also possible to make the source substrate larger and make it also serve as the susceptor.

Furthermore, the treatment temperature is not limited to 1085 [°C], but can be carried out at 900 [°C] or higher.

If the above temperature conditions etc. are selected appropriately and the crystal plane is exposed without any oxide film etc. on the surface to be grown,
It is also possible to grow single crystal layers.

As explained above, according to the present invention, it has become possible to simultaneously grow a silicon layer on one main surface of a silicon substrate and perform etching on the other main surface. Therefore, the number of steps is significantly reduced and the silicon substrate is not damaged. Further, since no crown is generated and warpage of the silicon substrate is not increased, subsequent manufacturing steps are facilitated.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part for explaining a conventional method of manufacturing a semiconductor device, and FIGS. 2 to 6 are views showing an embodiment of the present invention. 5
6 is a sectional view of the main part, FIG. 4 is a curve diagram showing the growth rate and etching rate, and FIGS. 7 to 9 are sectional views of the main part showing other embodiments of the present invention. In the figure, 11 and 41 are silicon substrates, 1
7 and 46 are polycrystalline silicon layers, 21 is a substrate to be processed, 22 is a source substrate, 23 is a quartz piece, 24 is a susceptor, and 25 is a reaction tube.

Claims (1)

[Claims] 1. A convex portion is formed at a portion of one main surface of a substrate to be processed made of silicon where an island-like region will be formed in the future, and an insulating layer is formed on one main surface of the substrate to be processed including the projecting portion. forming a film, holding the substrate to be processed and a source substrate made of silicon in a space of a silicon vapor phase etching reaction system (or growth reaction system) in a state in which one principal surface of the two faces each other and in close proximity to each other; Temperature T ₁ of one main surface of the source substrate and temperature of one main surface of the target substrate facing the source substrate
T ₂ and the temperature T ₃ of the other main surface of the substrate to be processed is T ₁
<T ₂ <T ₃ (or T ₁ >T ₂ >T ₃ ), and the space sandwiched between one principal surface of the substrate to be processed and one principal surface of the source substrate is defined as a mass transfer reaction system space. A method of manufacturing a semiconductor device, comprising the step of growing polycrystalline silicon on one main surface of the substrate to be processed, and etching the surface of the other surface.