JPS6362006B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention When data is exchanged between an input/output device and a central processing unit that have different operating speeds, processing is performed to temporarily store the data and absorb the data transfer speed difference. The present invention relates to a buffer storage device, and particularly relates to a data storage method of a buffer storage device when writing padding data to a designated area of the buffer memory to absorb data transfer speed differences.

(b) Background of the technology For example, since the input/output devices in a computer system have different characteristics from the central processing unit, etc., in the computer system, these different types of devices should be operated without constraining each other as much as possible. An input/output control method for improving system efficiency has become one of the key points in computer system configuration.

In this input/output control, the central processing unit is separated and independent as much as possible, an input/output control device is provided for each input/output device, and each device operates in parallel. System efficiency can be further improved by adjusting the balance using a buffer storage device or the like.

As the use of such computer systems progresses, the way they are used has become more sophisticated and complex, and demands for improving the efficiency of the entire system have become even stricter. There has been a strong demand for greater efficiency.

(c) Prior art and problems FIG. 2 shows a block explaining a conventional example.
Incidentally, FIG. 2 shows a schematic configuration of a buffer storage device which will be explained below.

For example, a magnetic disk device, which is one of the input/output devices in a computer system, and a central processing unit have different operating speeds, and the difference in the transfer speed of data exchanged between the magnetic disk device and the central processing unit is In order to absorb and adjust the data, the buffer storage device performs a process of padding arbitrary length padding data between transferred data.

The transfer processing of this transfer data and the processing of padding data are controlled by a magnetic disk control device (not shown), and in particular, the processing of padding data is directly controlled by the controller 10 in the buffer storage device according to instructions from the magnetic disk control device. A method of writing to a buffer memory circuit within a buffer storage device is generally adopted.

That is, as shown in FIG. 2, the controller 10 transmits padding data of a bit length determined based on instructions from the magnetic disk controller according to the amount of data to be transferred from the central processing unit to the input/output device, for example. Write directly to the buffer memory circuit 7 from the buffer memory circuit 7.

At this time, the control unit 10 switches the multiplexer circuit (MPX) 5 from the side that selects transfer data to the side that selects padding data in response to an instruction signal from the control unit 10.

At the same time, the instruction signal from the control section 10 is used as a start signal, and control for writing padding data into the address area specified by the control section 10 is performed at each address step until the write process is completed.

That is, the control unit 10 issues a start instruction to the address of the first step, confirms its end, outputs the address of the second step, issues the start instruction, and confirms its end, all the way to the final address. Repeat.

However, in this case, if the number of bytes of padding data is large, the above-described processing is repeated, which increases the processing time, and the time during which the control unit 10 is bound to this padding processing increases. This becomes a factor that deteriorates the overall processing efficiency.

(d) Purpose of the Invention The purpose of the present invention is to enable the control unit to only instruct the start of padding and confirm the end of padding, and to execute subsequent padding processing at high speed using dedicated hardware for padding processing. An object of the present invention is to realize a data storage method for a buffer storage device that reduces the required time, improves the processing capacity of the buffer storage device, and improves the processing efficiency of the entire system.

(e) Structure of the Invention The present invention provides a read/write control instruction for transfer data to a buffer memory circuit, as well as a control instruction for writing padding data of an arbitrary length between the transfer data, and confirms the completion state of the write. A control unit, a buffer memory circuit that reads/writes transfer data and arbitrary length padding data output from the control unit, and temporary start and stop addresses that specify the padding data to be written to the buffer memory circuit and the write area. a padding data register, a buffer address counter, and a padding stop address register to be stored in the padding data register, a timing control circuit that outputs the timing to start writing padding data to the buffer memory circuit, and an output from the buffer address counter to be stored in the padding stop address register. It is equipped with a comparison circuit that detects a match with the output of the address register, and a status display register that holds the completion state of writing padding data to the buffer memory circuit, and the buffer address counter sequentially increments the address. The padding data is automatically written at high speed in the area until it matches the stop address according to the timing based on the instruction signal from the control section, until the control section outputs the instruction signal and confirms the end of the padding process. This is achieved by a data storage method of a buffer storage device, which is characterized in that the time required for padding processing is shortened and the efficiency of the entire system is improved by configuring the buffer storage device so that other processing can be executed during the processing. I can do it.

(f) Embodiments of the Invention The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 1 shows a block diagram illustrating an embodiment of the invention. Note that the same reference numerals indicate the same objects throughout the figures.

This embodiment shows one embodiment of a buffer storage device. In the figure, 1 is a padding data register, 2 is a buffer address counter, 3 is a padding stop address register, 4 is a transfer control register, and 5 is a buffer storage device. is a multiplexer circuit (MPX), 6 is a comparison circuit, 7 is a buffer memory circuit, 8 is a timing control circuit, 9 is a status display register circuit, 10
indicates the control unit, respectively.

It is assumed that the buffer memory circuit 7 of this embodiment has a capacity to store data for one track of a magnetic disk.

The configuration of this embodiment includes a padding data register 1 that stores padding data output from a control unit 10 according to instructions from a magnetic disk control device (not shown), and a padding data register 1 that stores padding data output from a control unit 10 according to an instruction from a magnetic disk control device (not shown), and a padding data register 1 that stores padding data output from a control unit 10 according to an instruction from a magnetic disk control device (not shown). A buffer address counter 2 that automatically increments the address of the buffer memory circuit 7; a padding stop address register 3 that stores a padding stop address instructed by the control section 10; and a padding stop address register 3 that stores a padding stop address instructed by the control section 10; Multiplexer circuit (MPX) 5 for instruction signal
and the transfer control register 4 to be output to the timing control circuit 8, and transfer data from another device (for example, a magnetic disk device or a central processing unit), which is usually not shown, are selected, and the instruction signal from the transfer control register 4 is used to select the transfer data. A multiplexer circuit (MPX) 5 that selects the output data (padding data) of the padding data register 1 controls the timing of the comparison result of comparing the output from the buffer address counter 2 and the output from the padding stop address register 3. A comparison circuit 6 that outputs to the circuit 8, a buffer memory circuit 7 that stores transfer data and padding data from other devices (magnetic disk device or central processing unit, not shown), an address comparison circuit 6, and a transfer control register 4. a timing control circuit 8 that starts supplying a strobe signal instructing data write start to the buffer memory circuit 7 in response to an output signal from the buffer memory circuit 7, and outputs a padding end signal to the status display register circuit 9 when supply of the strobe signal is stopped; It is composed of a status display register circuit 9 that stores data in a state that can be read by the control unit 10, and the control unit 10 described above.

In this embodiment, when data is normally transferred from a magnetic disk device or central processing unit (not shown), the MPX5 is connected to the buffer memory circuit 7.
For example, transfer data from a magnetic disk device or central processing unit (not shown) is selected and sent to the buffer memory circuit 7 via a data bus.

At this time, the address of the buffer memory circuit 7 is supplied by the buffer address counter 2, and the buffer address counter 2 has an initial value set by the control unit 10, and outputs an address that is automatically incremented sequentially for each 1-byte transfer. .

When an instruction is given, for example, from a magnetic disk control device (not shown) to perform padding processing on padding data of a predetermined byte length during processing of this transfer data, the control unit 10 performs padding processing on padding data of a predetermined byte length. Set padding data to padding data register 1.

At the same time, after setting initial values in the buffer address counter 2 and padding stop address register 3, the padding instruction bit of the transfer control register 4 is turned on to release the connection thereto.

Note that the initial setting value of the buffer address counter 2 becomes the padding start address.

Next, the multiplexer circuit (MPX) 5, which receives the instruction signal for padding processing from the transfer control register 4, sends data output from the padding data register 1 as write data to the buffer memory circuit 7, that is, padding data. Select and output.

At the same time, the timing control circuit 8 that has received the instruction signal supplies a strobe signal to the buffer memory circuit 7 to cause the buffer memory circuit 7 to start writing padding data.

On the other hand, the comparison circuit 6 compares the buffer address sequentially incremented and outputted from the buffer address counter 2 with the padding stop address outputted from the padding stop address register 3, and transmits the comparison result to the timing control circuit. Output to 8.

Then, when the buffer address output from the buffer address counter 2 matches the padding stop address, the timing control circuit 8 stops supplying the strobe signal to the buffer memory circuit 7, and at the same time, the timing control circuit 8 stops supplying the strobe signal to the buffer memory circuit 7. A padding end signal is sent to the display register circuit 9 and stored.

As described above, after instructing the start of padding, the control unit 10 in this embodiment only needs to read the status display register circuit 9 and detect the reception of the padding end signal, and during this time, each of the above-mentioned functional blocks performs high-speed operation. Execute padding processing.

On the other hand, the control unit 10 can perform other processes (for example, read processing of transfer data, etc.) while the padding process is being executed.

(g) Effects of the Invention According to the present invention as described above, padding processing can be performed at high speed in any area of a buffer storage device, so the time required for padding is shortened, and the processing capacity of the buffer storage device and, ultimately, the system performance are improved. This has the effect of improving processing capacity.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating an embodiment of the present invention, and FIG. 2 is a block diagram illustrating a conventional example. In the figure, 1 is a padding data register;
2 is a buffer address counter, 3 is a padding stop address register, 4 is a transfer control register, 5 is a multiplexer circuit (MPX), 6 is a comparison circuit, 7 is a buffer memory circuit, 8 is a timing control circuit, 9 is a status display register The circuit and 10 indicate a control section, respectively.

Claims (1)

[Scope of Claims] 1. In a buffer storage device that reads/writes transfer data exchanged between an input/output device and a central processing unit, each having a different operating speed, the transfer data is controlled to read/write to the buffer memory circuit. A control unit that issues a control instruction for writing padding data of an arbitrary length between the transfer data according to the read/write processing status of the transfer data together with the instruction, and confirms the completion of the write based on the content read from the status display register. a padding data register, a buffer address counter, and a padding data register for temporarily storing padding data of arbitrary bit length outputted from the control section and start and stop addresses of the buffer memory circuit to which the padding data is written; a padding stop address register; a timing control circuit that outputs a write start timing of the padding data to the buffer memory circuit based on a start address output from the buffer address counter according to an instruction from the control section; and the timing control circuit. A status display register is provided to store a padding processing end signal from a control circuit in a state where it can be read from the control section, and while the transfer data is being written to the buffer memory circuit, padding data of an arbitrary length is written to the buffer memory circuit. In this case, the control section outputs a start address and a stop address of the buffer memory circuit at the same time as issuing a padding data write instruction, and the buffer address counter to which the start address is set sequentially increments and outputs the buffer memory circuit. Writing the padding data to the address area of the buffer memory circuit, detecting in a comparison circuit whether the output from the buffer address counter matches the output from the padding stop address register, and detecting a match from the comparison circuit. In response to the signal, the timing control circuit stops writing the padding data to the buffer memory circuit, and the control circuit confirms the stoppage of writing the padding data from the status display register storing the stop signal. A method for storing data in a buffer storage device.