JPS6362141B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention requires obtaining a composite signal from a relatively slow information signal and a pseudorandom code sequence generated using a clock signal synchronized with the signal. For example, it relates to a spread signal generation circuit used in a spread spectrum system.

Spread spectrum demodulation includes demodulation of spread spectrum modulation (despreading, bandwidth restoration) and demodulation of signals that carry information (baseband demodulation). The spread spectrum demodulation process requires synchronization between pseudorandom codes, and the baseband demodulation process requires bit synchronization. These 2
Performing the two synchronizations separately is disadvantageous in terms of hardware and also in terms of the time required to establish synchronization. In order to eliminate this disadvantage, it is possible to use the position signal (pattern synchronization pulse) of the code pattern of the pseudorandom code that has established synchronization as the bit synchronization signal without using a dedicated synchronization circuit for bit synchronization. Conceivable. In order to perform this operation on the receiving side, on the transmitting side, each bit of the information signal and each bit of the pseudo-random code for spreading must be matched in phase, and each bit of the information signal must be synchronized with the pattern synchronization pulse of the pseudo-random code. It is necessary to maintain a predetermined phase relationship with

In response to such demands, conventional spread signal generation circuits generate a pseudo-random signal from a relatively low-speed clock signal synchronized with the information signal, and then combine this pseudo-random signal with the information signal sampled by the clock signal using exclusive logic. A spread signal is obtained by summation. In this conventional circuit, the phase relationship between each bit of the information signal and each bit of the pseudorandom code is not established, and therefore, as described above, the receiving side uses pattern synchronization pulses of the pseudorandom code to It is not possible to eliminate the bit synchronization circuit or to eliminate the synchronization establishment time. In addition, if the low-speed clock contains jitter, for example, if the transmission path is long and is affected by external noise, the sampled information signal will also contain jitter due to the jitter, and this will result in pseudo-random The spread signal combined with the code will lack accuracy and stability.

SUMMARY OF THE INVENTION An object of the present invention is to provide a spread signal generation circuit that eliminates the drawbacks of such conventional circuits.

According to the present invention, there is a means for generating a pseudorandom code having the same period as the clock signal in response to a clock signal, and a pattern synchronizing pulse is generated by detecting a certain pattern in the pseudorandom code from the output of the pseudorandom code generating means. means for outputting a reclocked information signal by synchronizing the information signal synchronized with the clock signal with the pattern synchronization pulse; and means for generating a spread spectrum signal in response to the pseudorandom code and the reclocked information signal. and means for shifting the phase of the pattern synchronization pulse with respect to the phase of the clock signal so that the phase relationship between each bit of the pseudorandom code and each bit of the information signal is constant. can get.

The spread signal generation circuit of the present invention has a relatively simple circuit configuration, and can set the phase relationship between the information signal and the pseudo-random code as desired even for low-speed information signals containing jitter, and is accurate. A stable spread signal can be generated.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a conventional spread signal generating circuit. A pseudo-random code generation circuit 1 has exclusive logic between a multi-stage shift register 2 which receives a high-speed clock signal a obtained by multiplying a clock signal CLK by a multiplier circuit 8, and an output b of the final stage of this shift register 2 and an output c between the stages. It includes a circuit 5 that calculates the sum and feeds the result back to the first stage. Here, the shift register 2 has n stages, the code length period is 2 ⁿ -1, and the multiplier circuit 8 is multiplied by N (N=m[2 ⁿ -
1]; m is an integer) circuit. slow clock signal
A low-speed information signal IN synchronized with CLK is sampled (reclocked) by a delay flip-flop 10, and then combined with a pseudorandom code PN from a pseudorandom code generator 1 and an exclusive OR circuit 11.
are combined to form the spread signal SS. This circuit has the drawbacks mentioned above.

FIG. 2 is a block diagram of an embodiment of a spread signal generation circuit according to the present invention. Low speed clock signal CLK
is the N multiplier circuit 8 (here, N=m[2 ⁿ −1]; m is an integer, and n indicates the number of stages of the multistage shift register 2)
The signal is converted into a high-speed clock signal and supplied to the multi-stage shift register 2 of the pseudo-random code generation circuit 1 through the clock gate circuit 13, and a specific pseudo-random code string PN is generated from an arbitrary output stage. At the same time, the output of each stage of the multistage shift register 2 is applied to a pattern detection circuit 14 that detects a certain special pattern in the pseudorandom code string PN. This pattern detection circuit 14 generates a pattern synchronizing pulse d for each code length period of the code sequence, and sends an m-divided pulse e to a pulse phase comparison circuit 18 and a delay flip-flop 10 through an m-divided circuit 16, respectively. In the pulse phase comparator circuit 18, the low-speed clock signal CLK and m of the same frequency are used.
A phase comparison with the frequency-divided pulse e is performed. That is,
This pulse phase comparator circuit 18 receives an information signal f reclocked using the slow clock signal CLK.
An aperture (pulse detection section) is set approximately at the center of each bit of the clock signal CLK, and if the m-divided pulse e can be detected in that section, it is determined that the phases of the clock signal CLK and the pulse e match. Conversely, if the m-divided pulse e cannot be detected within the set aperture, the comparison circuit 18 detects the clock signal CLK.
It is determined that the phases of the pulse e and the pulse e do not match, and the clock gate circuit 1
In response to this pulse, the clock gate circuit 13 cuts off one cycle of the high speed clock signal. In this case, the state of the multistage shift register 2 of the pseudorandom code generation circuit 1 is 1.
The bit is retained, and the code sequence PN is shifted in phase by one bit from the previous cycle.
Similarly, the m-divided pulse e is also shifted by 1 bit width. This state is shown in FIG. 3A. By repeating these steps, the m-frequency divided pulse e approaches the aperture, and when it is finally detected within the aperture, the clock gate circuit 13 continuously supplies the high-speed clock signal CLK to the multistage shift register 2 without controlling it. do. At this time, a code sequence PN with a normal period is obtained from the pseudo-random code generation circuit 1. At the same time, the m-divided pulse e, which has undergone the above phase shift control, is sent to the delay flip-flop 10.
The information signal f is reclocked at an optimal point not affected by jitter. The phase relationship between the reclocked information signal g and the spreading code sequence PN is automatically set by the phase relationship determined by the pattern detection circuit 14, ie, by selection of a special pattern. Furthermore, since the phase relationship between each bit of the reclocked information signal g, which is no longer related to jitter, and each bit of the code sequence PN is constant, an accurate and stable spread signal SS can be obtained by exclusive OR 11. . This situation is shown in the timing diagram of FIG. 3B. (however,
Let m=1. ) As is clear from the above explanation,
By appropriately selecting the pattern detection circuit 14, the phase relationship between the information signals f, g and the pseudorandom code sequence PN can be set arbitrarily.

As explained above, according to the present invention, the phase relationship between each bit of the information signal and each bit of the pseudo-random code made from the clock signal synchronized therewith is kept constant, and the phase relationship between the information signal and the pseudo-random code is maintained constant. A spread signal with arbitrary settings can be obtained. In particular, the present invention exhibits great effects when the influence of jitter cannot be ignored.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional circuit for generating a spread signal from an information signal and a pseudorandom code sequence, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is the circuit operation of Fig. 2. FIG. 3 is a timing diagram of each part for explaining the operation. In the figure, 2...
Multi-stage shift register, 8...N multiplier circuit, 10...
. . . delay flip-flop, 11 . . . exclusive OR, 13 . . . clock gate circuit, 14 . . . pattern detection circuit, 16 .

Claims (1)

[Claims] 1. Means for generating a pseudo-random code having the same period as the clock signal in response to a clock signal, and detecting a certain pattern in the pseudo-random code from the output of the pseudo-random code generating means and outputting a pattern synchronization pulse. means for synchronizing an information signal synchronized to the clock signal to the pattern synchronization pulse to output a reclocked information signal; and means for outputting a reclocked information signal in response to the pseudorandom code and the reclocked information signal. and means for shifting the phase of the pattern synchronization pulse with respect to the phase of the clock signal so that the phase relationship between each bit of the pseudorandom code and each bit of the information signal is constant. Diffusion signal generation circuit.