JPS6363932B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a CPU runaway monitoring method for monitoring program runaway in a microprocessor (hereinafter abbreviated as CPU) system.

Conventional technology and problems Consists of CPU, read-only memory, random access memory, input/output (I/O) ports, etc.
In a CPU system, if the CPU runs out of control while executing a program, the contents of the I/O port or data may be damaged due to accesses other than the original purpose using addresses or data generated by the runaway. Because of this, correct processing cannot be performed from now on. For this reason, in CPU systems, a method is used to monitor program runaway and immediately stop the CPU operation if runaway occurs.

As one method for detecting such runaway, a watchdog timer (hereinafter abbreviated as WDT) circuit has been used. Normally, interrupts are periodically applied to the CPU, and accesses are made from the CPU in response to these interrupts, but WDT
The circuit responds to periodic interrupts by
It detects an abnormality in the access interval time from the CPU, and an abnormality detection signal is generated when the CPU access interval is longer than the upper limit of a certain set time, or conversely, when it is shorter than the lower limit of a certain set time. This outputs the following.

In the WDT circuit, a timer circuit configured using a monostable multivibrator has conventionally been used as means for setting the abnormality detection time as described above. However, monostable multivibrators tend to malfunction due to noise, and because they use a time constant circuit consisting of C and R to determine the operating time, errors tend to occur in the set time, so it is difficult to adjust C and R. is required and is time-consuming to manufacture. As described above, conventional WDT circuits are composed of monostable multivibrators, and therefore have problems with noise resistance and time constant errors.

Purpose of the Invention The present invention is intended to solve the problems of the prior art, and its purpose is to provide a system that does not cause noise resistance and setting time error problems in a WDT circuit. be.

Structure of the Invention The CPU runaway monitoring method of the present invention uses a counter and a read-only memory (hereinafter abbreviated as ROM) to detect an abnormality by determining whether the interval time of the CPU response to a periodic interrupt is good or not. At this time, by switching the upper address of the ROM and selecting the output data using a register that can be set from the CPU, the range of detection setting time can be selected, and detection or non-detection can be selected. This makes it possible to make such selections.

Embodiment of the Invention FIG. 1 shows the configuration of an embodiment of the CPU runaway monitoring system of the present invention. In the same figure, 1 is the CPU,
2 is a data bus of the CPU 1, and 3 is a counter which receives a constant cycle clock at a terminal CK and counts it. 4 is a flip-flop which latches the contents Do...Dm of the data bus 2 by inputting the access pulse B output from the CPU 1 to the clock terminal CK, and outputs the encoded data.
Qo…Qm is generated. 5 is a ROM in which the output of the counter 3 is inputted to the lower address, and the output Qo...Qm of the flip-flop 4 is inputted to the upper address.
Output data according to these addresses Ao…Am
Generates D ₁ and D ₂ . Output D ₁ is written so that logic “1” is output in the abnormality detection range on the lower limit side of the access interval time, and output D ₂
is written so that logic "1" is output in the abnormality detection range on the upper limit side of the access interval time. 6 is an AND gate, and ROM5
The output of the AND of the D1 output of the CPU ₁ and the access pulse A output from the CPU 1 is generated. 7 is an OR gate, which connects the _D2 output of ROM5 and AND gate 6.
Generates the output of the logical sum with the output of . 8 is a clear pulse generation circuit, which includes an inverter I and a resistor R.
It consists of a differentiator circuit consisting of a capacitor C and a NAND gate G, and generates a pulse by the trailing edge of the access pulse A to clear the counter 3's clear terminal.
Clear this by inputting it as a clear pulse to CLR.

FIG. 2 shows the embodiment shown in FIG.
An example of outputs D ₁ and D ₂ corresponding to the upper and lower addresses of the ROM is shown.

The operation of the CPU runaway monitoring system of the present invention will be explained below based on both figures. The CPU 1 selects the operation mode in advance and outputs a switching signal to the data bus 2, and this output signal is latched to the flip-flop 4 by the access pulse B output from the CPU 1 for each access in response to the interrupt signal IRQ.
It is input to ROM 5 as its upper address.
For example, operation mode “STOP”, “High”, “Low”
The upper addresses input to ROM5 corresponding to “TST” and “TST” are “00”, “01”,
“10” and “11”.

Also, while the CPU is running the program,
Periodic interrupts are activated in the CPU, and the CPU
accesses the address where access pulse A is generated within this interrupt routine. At the trailing edge of the access pulse A in the previous access, the counter 3 is cleared by the clear pulse output from the clear pulse circuit 8, and at the time of the current access, the clock count value between the previous access and the current access is It is input to the ROM 5 as the lower address n.

In correspondence with the upper address selected in this way, the ROM is output according to the lower address n.
A pattern as shown in FIG. 2 is selected based on data D ₁ and D ₂ outputted from 5, and an abnormality in the access interval time is detected based on this pattern. In other words, when access pulse A is output when data D ₁ is "1", it means that the current access was too early and an abnormality on the lower limit side, and that data D ₂ is output because the access pulse A is output at the time of the current access. This is determined to be an abnormality on the upper limit side because it is over, and the OR gate 7 calculates the logical sum of both cases and outputs the result as an abnormality detection signal. After the CPU 1 accesses, the counter 3 is cleared at the trailing edge of the access pulse A and starts the next count.

The upper and lower limit abnormality detection range of the access interval time can be switched to two types of time by mode "High" and "Low". In Figure 2, the mode "STOP" corresponds to when no runaway is detected or when the motor is stopped.
Furthermore, the mode "TST" is provided for testing detection circuits, etc.

Effects of the Invention As explained above, according to the CPU runaway monitoring method of the present invention, a counter is used to detect an abnormality in the CPU access interval time in response to periodic interrupts.
Since the range of abnormality detection time is set using ROM, problems such as noise resistance and circuit adjustment for time setting can be solved, and the ROM
Write some types of data in advance to the CPU
By setting and switching the ROM address via the flip-flop, the abnormality detection time range can be changed, and various operation modes such as stopping monitoring operation and setting test status can be changed. I am now able to do it. Furthermore, even if it is necessary to change the abnormality detection time range, there is no need to adjust C and R of the monostable multivibrator as in conventional circuits.
This is advantageous because it can be handled simply by changing the ROM address or replacing the ROM.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the CPU runaway monitoring system of the present invention, and FIG. 2 is an explanatory diagram showing the outputs D ₁ and D ₂ in the embodiment of FIG. 1. 1...Microprocessor (CPU), 2...Data bus, 3...Counter, 4...Flip-flop, 5...Read-only memory (ROM),
6...and gate, 7...or gate, 8...
Clear pulse generation circuit.

Claims (1)

[Claims] 1. A microprocessor (hereinafter referred to as CPU) that performs access operations in response to periodic interrupts.
In a method for monitoring runaway of a program by detecting an abnormality in the interval time of the access time, a memory circuit reads, encodes, and outputs a CPU instruction for each access;
A counter that is cleared every time the CPU accesses and counts a constant period of clocks, and the output of the storage circuit is input to the upper address and the output of the counter is input to the lower address to output a signal indicating the lower and upper limits of the set time. a read-only memory, and generates an abnormality detection signal when a CPU access signal occurs before the lower limit or after the upper limit of the set time.