JPS6364000B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address input buffer circuit for semiconductor memory devices, particularly MOS ROMs of the electrically programmable type.

BACKGROUND OF THE INVENTION Electrically programmable floating gate ROM or EPROM devices are generally described in US Pat. Nos. 4,112,509 and 4,112,544 and US Pat. Produced using the cell layout seen. There are several manufacturers that produce EPROM devices in 8K, 16K, 32K, and recently 64-bit size layouts. However, the continuing desire for high speed and low cost has created a need to reduce cell size or increase bit density while maintaining process compatibility with existing dual-level polysilicon N-channel fabrication methods. Ta. One classic technique for increasing the array density of ROMs is to use a virtual ground configuration instead of providing a ground line for each column or output line. Virtual ground memory is described in the Fisher and Rogers patents, both of Texas Instruments.
3934233 and ERCaudel U.S. Patent No. 4021781
Disclosed in the issue. The virtual ground EPROM layout was developed by Texas Instruments' David J.
Disclosed in McElroy US Pat. No. 4,151,021. Because programming floating gate EPROMs requires transient high voltages and high currents,
More stringent requirements are placed on the decoding circuit than circuits conventionally employed in virtual grounding devices. Traditional EPROMs therefore used separate contacts and wires for each cell, thus requiring extra space on the chip. However, with the separate ground selection and column selection functions required for virtual ground memory operation, the column decoding employed has different complexities than dedicated ground memory devices. This column and ground selection addressing of large high speed devices, along with row addressing, imposes new requirements on the decoding circuitry. Customer demands for low power operation of EPROM devices have created a need to provide a power down mode distinct from the normal standby mode of operation. Although the EPROM device does not respond to addresses in power-down mode, there should not be an unduly long period of time before normal access is allowed when power-down mode is exited. Improved EPROMs have been designed within these constraints and conflicting conditions.

It is an object of the present invention to provide an improved electrically programmable memory device with low power consumption or power-down operation.

DESCRIPTION OF MEANS AND EMBODIMENTS FOR SOLVING PROBLEMS In one embodiment of the invention, an electrically programmable memory array having rows and columns of floating gate memories has output lines alternating between columns of cells. It has a ground wire and provides a virtual ground configuration. Rows are selected by one part of the address input, columns by other parts. The output wire on one side of the selected column is energized and the ground wire on the other side is energized. A differential sense amplifier is responsive to the voltage on the selected output line and the reference voltage. The number of transistors required for the row selection function of the decoder is determined by employing a predecoder that performs a 1-to-4 selection for each address bit pair, and then using one of these selection outputs to activate the N multiplexer and the other. is significantly reduced by using all of the N outputs as decoder inputs and the N outputs as multiplexer inputs.

The predecoder receives two pairs of true and complementary address voltages for each address bit.
An OR circuit, each pair containing address voltages that are logically the same but separated by a low threshold transistor. The predecode circuit uses the high end of each pair to drive the input transistors of the AND/OR circuit between V _CC and the output node, and the low end of each pair to drive the input transistors of the AND/OR circuit between the output node. The speed is increased by driving between the ground and ground. The former input transistor has a lower capacitive loading than the latter.

FIG. 1 shows a block diagram of a memory system employing features of the present invention. Although the invention can be used with various types and sizes of memory devices, the embodiment shown here is a 32K memory device partitioned into 8x16x256 partitions.
i.e. N-channel floating gate electrically programmable ROM with 32768 bits.
In other words, it is EPROM. In a commercial implementation, column decoding is further provided to provide 8x32 instead of 8x8x256.
Defining a 16-bit device partitioned into x64 partitions, a 32K-bit device partitioned into 8 x 32 x 128, and a 64K-bit device partitioned into 8 x 32 x 256, the illustrated embodiment takes advantage of the row decoding circuitry. selected to show. In FIG. 1, the cell array 10 has 256 rows and 128 rows.
Contains 32,768 floating gate memory cells arranged in columns, where the columns are 10-1 to 10
-8 separate cell groups. Each group has a separate input/output terminal 11. 8
An 8-bit row address applied to each address input terminal 12 is decoded to activate only one of the 256 row lines 13. The cell array is a virtual ground type, with only one ground wire from 10-1 to 10-8.
are connected to ground for each group, and adjacent column lines are used as outputs for selected cells in each group.
The 4-bit string address applied to the integrated circuit device by 4 terminals 14 is decoded by eight separate selection circuits 15 to one of the nine ground wires in each group from 10-1 to 10-8. is selected, and one of the eight output column lines is selected by eight separate selection circuits 16. Differential sense amplifiers 17 in each group from 10-1 to 10-8 sense the data bit for the selected cell and apply an output to one of the terminals 11 for a read operation, and for a program operation, the differential sense amplifiers 17 in the circuit 17 An input buffer and selection circuit 16 adds the data bits on terminal 11 to the selected bits within each group.

The integrated circuit device of the embodiment has 5 terminals in addition to 8 data terminals and 12 address terminals. One +5 ^V supply voltage V _cc is applied by terminal 18 and ground or V _ss is applied to terminal 19 .
The programming voltage V _pp of approximately +25 ^V is applied to terminal 2.
Applied to 0. Chip selection command is sent to terminal 21
Power down/Program command PD/
PGM is applied to terminal 22. the latter three
_Vpp , and PD/ are connected to a control circuit 23, which generates control voltages to define the mode of operation of the system.

In read mode, V _pp and PD/ are logic 0 and active low, logic 0.
These conditions are shown on the left side of FIGS. 2a-2e. As shown in Figure 2a, is low and the second
If _Vpp and PD/ are low as shown in FIG. 8 bits are selected (one bit in each group from 10-1 to 10-8) and these 8 bits appear on terminal 11 as shown in FIG. 2e.

The other state is standby mode, where all inputs are the same as in read mode except that at logic 1 is high. The chip is now in a read state, but even if an address occurs, as shown in the center of FIG. 2b, it is not so selected, and the data out of FIG. 2e does not occur.

A power-down mode of operation occurs when the PD/input is a logic 1, as shown on the right side of FIG. 2c. As shown in FIG. 2d, V _pp is low and can be both low and high, ie, it is a state that does not require attention. If the address occurs, no output occurs.

As shown in Figure 2'd (left side), the V _pp input is +
25V, PD/ is active low as shown in Figure 2'e, and PD/ is active low as shown in Figure 2'a.
A programming mode of operation occurs when CS is active low. In this state, a row address applied to terminal 12 produces a high voltage (V _pp -V _t ) on one row line 13 (all others low). The column address generated on terminal 14 as shown in FIG. 2'b selects one of the eight columns in each group. 10-1 to 1, depending on whether a 0 or a 1 is present at each terminal 11 during the time shown in Figure 2'e.
A high voltage V _pp -V _t or a low voltage is applied to the selected column line of each of the eight selected bits in groups 0-8.
This condition causes the floating gates of the eight selected bits to be charged or uncharged depending on the data input on terminal 11.

Program mode occurs only when _Vpp is high and PD/ are both low. All other conditions generate a program inhibit mode as shown on the right side of FIG. 2'. The inhibit mode exists when either or both inputs or PD/ are high as shown in Figure 2'a or Figure 2'c. Here terminals 12 and 1
Regardless of the address occurring on terminal 4 or the data present on terminal 11, the chip is in power down mode.

The row selection circuitry in the system of FIG. 1 includes predecoding and multiplexing capabilities, which provide important advantages. Each of the eight row address bits A0-A7 on terminal 12 is applied to one of eight buffer circuits 30, each of which is applied to a pre-decoder 32 for A2 to A7 bits or to a row split decoder 33 for A0 and A1. generates address and complementary voltages A and on line 31. Three predecoders 32 input six address bits A2
to A7, each of these circuits produces four outputs on line 34 which is the input of a 1-of-64 row decoder 35. Decoder 35 has 64 output lines 36, of which only one is high and all others are low for a given address A2-A7. Lines 36 are applied separately to 64 1-of-4 selection circuits 37, each having 4 outputs 13, which are the row lines of array 10 and 8 of 10-1 to 10-8.
It extends throughout the group. Each selection circuit 37 receives four input lines 38 from the row division decoder 33 and functions to select one of the four lines 13 according to the A0 and A1 bits of the address.

In FIG. 3, which shows a detailed circuit diagram of two buffer circuits 30, the input terminal 12 is connected to the gates of two enhancement transistors 40, 41. A first input transistor 40 has a depletion load 42 and is connected to ground via a transistor 43 whose gate is at _Vcc . 1st
The output 44 of the stage is connected to the gate of a natural transistor 45 which shares a ground transistor 43 as well as a second input transistor 41 and its parallel ground gate depletion transistor 46 . In this way, all transistors 40, 41, 4
Currents 5 and 46 flow through transistor 43. Node 44 is also connected in series with input transistor 41 to the gate of depletion transistor 47, and in series with these transistors a natural transistor 48 has a CE signal on its gate and serves to put it into power down mode. . The source of transistor 47 provides output line 31-1 and the drain of transistor 41 provides ^* output line 31-2. If input 12 is high, transistor 41 is on and ^* is low. Another inverter transistor 49 with a depletion load 50 receives ^{the *} signal on its gate, and this inverter drives the gate of the depletion load 51 in the final stage. 1st inverter 4
0 output node 44 is connected in this final stage to the gate of an enhancement transistor 52, which has a grounded gate depletion mode transistor 53 in parallel as well as a power-down operating transistor 46. . Natural transistor with CE on the gate 5
4, like transistor 48, provides a pull-down function during power-down periods.

The purpose of transistor 45 is to balance the current through transistor 43 between the 0 and 1 inputs, so the voltage on node 55 is approximately constant. The voltage on node 55 provides a small back bias to transistor 40, and operation for low input values is sufficient with reasonable TTL margin even at low _Vt .

Transistors 47 and 51 have the inverted outputs of the previous stage on their gates, speeding up operation compared to standard gate-source shorted depletion loads. In this way, the gates rise earlier than if they were connected to each source, and the transistors 47 and 47
51 turns on early.

In power down operation transistor 48,
54 is turned off by the CE input shown in FIG. 2g. The control circuit generates CE from PD/, and this voltage is complementary to PD/. When transistors 48 and 54 are off, and A are both high and A ^* and ^* are low during power down mode. The function of transistors 46 and 53 is to hold output ^* and A ^* low by leakage during power down. In active reading mode
CE is high and transistors 48 and 54 are fully conductive, so that and ^* are at the same logic state as are A and A ^* .

FIG. 4 shows one of the three predecoders 32. The circuit has four parallel, low-threshold natural transistor pairs 56, which have outputs A, B, on their gates. These four parallel pairs are in series with four natural transistors with A ^* and ^* on their gates. transistor pair 57
is grounded through an enhancement transistor 58 having ^* and B on its gate. Four outputs 34 are taken at node 59 between transistors 56 and 57. All A ^* and B ^*
The signals are below node 59 and the A and B signals are above node 59. This is advantageous in power down operation.

The input buffer 30 for the A0 and A1 bits is shown in FIG. 4a along with the row splitting decoder 33. The input buffer circuit is similar to that of FIG. 3 except that transistors 48 and 54 are not present and depletion transistors 46 and 53 are omitted since the power down function is not used. No A ^* or B ^* output occurs.

The row division decoder 33 includes four NOR circuits having transistors 60, A0 and A0.
1 address bit buffer 30 to A...
B and output pair 31, respectively. each
The NOR circuit has a depletion load 61, an inverter stage 62 and a pair of push-pull transistors 6.
4 by push-pull output circuit with 3,64
outputs 38.

FIG. 5 shows a 1-in-64 decoder 35 along with a 1-in-4 decoder 37 and circuitry for applying programming voltage V _pp to the row lines. Three sets of four wires 34 extend along the decoder and provide inputs to the gates of three transistors 65 in the 64 NOR circuits. 3
Different combinations of one input on each line of the set are used in each NOR circuit, and only one is selected for a given code on line 34. Three parallel transistors are connected in series with a power down control transistor 66 having CE on its gate and a depletion load 67. In power-down mode CE is low and transistor 6
Since transistor 65 is off, the output becomes high and no current flows through any of the 3×64, or 192, transistors 65. In normal mode, CE is high,
Since it is a natural or low threshold transistor, the drop is very small. All gates of the three transistors are low for the selected NOR circuit and line 36 is high. Also, for all others, at least one gate input is high and line 36 is low. When line 36 is low, inverter 68 in decoder 37 produces a high output to the gates of four transistors 69, which cause the four row lines 13 of this decoder 37 to
keep everything low. One line that is high 3
6, a set of four transistors 70 are turned on to connect four lines 38 to four row lines 13. Since only one of these four lines 38 is high, only one of the 256 row lines 13 is high. Depression transistors 71 with _Vcc on their gates serve to prevent the high voltages present during programming from destroying the driver transistors 69, and these devices 71 have a high voltage on their drains. Turn off.

For programming, a selected one of the 256 row lines is set near V _pp and the rest are set low. The _Vpp input 20 is connected to each row line 13 via several sets of three series transistors 72, 73, 74. V _pp , and the VPR command derived from PD/ is connected to the gates of all transistors 72 and is therefore programmable only when PD/ is low and V _pp is high, and in all other states. VPR is low and transistor 72 is turned off. Transistors 73 and 74 are all unregulated depletion devices with thresholds of -4V. The effect of the series combination is to pull the 1 line 13, which is at logic 1, to _Vpp , and for everything else it remains at _Vss because transistor 69 is on.

The row decoder circuits of FIGS. 3, 4, and 5 have several advantageous features. The slowest output A (or B) in the address buffer 30 is only two inversions from the address input terminal 12, so the speed is good. The second input transistor 47 is also used to speed up the response of positive input transitions. separate A and A ^* ,
By supplying outputs such as A and ^* , the buffer can be powered down to a minimum power state and at the same time the predecoder 32 can be brought to a zero power state. The pre-decoder 32 is connected to the row decoder 35
By using this together, the number of driver devices 65 used for the NOR circuit can be halved, and then one NOR circuit can be used for each of the four row lines 13 to further reduce the number of required drivers by two. can. Thus, a 1 in 256 decoder requires only 64 NOR circuits, each with 3 transistors 65. The reduction in device loading compared to standard 256 NOR circuits of 8 input transistors each is highly desirable. The row split or multiplex decoder 33 includes a push-pull output stage 63,
A simple NOR circuit with two input transistors 60 employing 64 is used to improve the drive. The row decoder 35 is a 3-input NOR circuit,
Each NOR circuit has another transistor 6 whose gate is connected to CE for power down control and CE is low for power down.

In Figure 1, the column selection circuit is a 4-input buffer 3.
0, which is the same input buffer used for the A0 and A1 address bits. The eight address and complementary outputs from the four buffers on line 75 are applied to a 1 of 9 decoder 76;
The decoder energizes one of nine output lines 77 to ground selection circuit 15. Thus, one of the nine ground wires in each group 10-1 through 10-8 is first selected before the output column line is selected. Line 77 is also an input to column select decoder 78;
This decoder is connected to A8 and 8 on two lines 70.
is used as input to select either side of one of the nine lines 77 that is high. 8 on line 79
The middle 1 output is connected to the column selector 16.

It is important that the virtual ground selection on line 77 be decoded and obtained as quickly as possible to minimize access time. A delay may be allowed to activate column selection on line 79. The operating time of the virtual ground selector 15 has a greater influence on access time than the operating time of the column selector 16, which can tolerate delays. Thus, the virtual ground selection is decoded directly from address inputs A8-A11 and used to activate the ground selector 15, and the ground selection on line 77 is then used in decoder 78 with the LSB of the column address, A8, to select the column. Occur.

FIG. 6 shows the decoder 76 in detail. The addresses and complements of A8 through A11 from buffer 30 on line 75 are used as gate inputs to driver transistors 80 in a set of nine NOR circuits;
Two NOR circuits are illustrated. In order to select 1 out of 9, 7 of the NOR circuits have 3 transistors 80 and the remaining 2 have 4 transistors 80.
It has 0. The NOR circuit has a depletion load 81 and a power down transistor 82 which is continuously driven by CE. Output node 83 is connected to a modified push-pull circuit having an inverter transistor 84 driving one output transistor 85 and a direct drive threshold output transistor 86. Transistors 87, 88 with CE on their gates provide a power down mode in which all lines 77 are held low. Transistor 89 is transistor 7 in the row decoder.
Provides the same functionality as 1. The circuit for applying a high voltage to the 1-of-9 line 77 selected during programming includes the three series transistors 72, 73, 74 used for the row lines of FIG. However, in this case transistor 72 has VPC on its gate rather than VPR.

FIG. 7 shows the selector 78 in detail. eight four-input and/or logic circuits having input transistor pairs 90 are responsive to nine ground selection lines 77;
A transistor pair 91 common to all eight logic circuits is responsive to A8 and 8 on line 75. Each logic circuit has a depletion load 92 and drives an output transistor 93. This output stage has a depletion load 94 and a common power down gate 95 common to all eight. Column select line 79 is connected to these output circuits via a series transistor 96 having a gate on its gate. The high voltage for programming is connected to the transistors 72, 73, 74 connected to each line 79 as before.
Generated by a series circuit including transistor 9
6 isolates the high voltage on line 79 that is high during programming to prevent the high voltage from discharging through depletion load 94 to _Vcc .

In FIG. 8, the cell array 10 is the memory cell 1
0' matrix array, each of which has a control gate 101, a source 102, a drain 103 and a channel between the source and drain and the control gate 101.
It is an electrically programmable insulated gate field effect transistor having a floating gate 104 between.

The control gates 101 of all cells in each row are connected to a set of row lines or x-rays 13. The example has 256 lines 13 from the X decoding circuit,
As mentioned above, they select 1 out of 256 based on the 8 bits X on line 12, the row address. In the read mode, a selected one of the lines 13 goes high and the others remain low.

The drain 103 of the adjacent cell 10' is connected to the Y output line 1
05, and in the exemplary embodiment 64 lines 105 are partitioned to produce an 8-bit parallel output 11 from the device, each line 105 connecting two rows of cells 10'.
output, so that each group has 16 cells of 8
There are groups, each group containing eight lines 105.
Line 105 is connected to V _cc via load transistor 121
Also, eight transistors 16-1 to 16-8
and is thus connected to the Y output line 106. (There are eight separate lines 106, one in each group of 16 cells wide.) Transistor 16-
Gates 1, 16-2, etc. are connected to receive the column select voltage on line 79, and they send a logic 1 voltage to one of these gates based on the 4-bit column address on input pin 14. (i.e., _Vpp for programming) and maintains the rest at _Vss . The 4-bit address is used to select 1 cell 10' out of 16 in a group, and to select 1 line out of 8, the 4-bit Y address A8-A11 is used.
Only the MSB3 bits A9-A11 are required, but the virtual ground configuration requires the LSB address bit A8.

The sources 102 of adjacent cells 10' are commonly connected to another set of column lines 107 which act as ground lines. Nine lines 107 are required for each group of 16 cells 10'. That is, the number of ground lines for the M×N array is (N/2)+1. Each line has a load device 10
8 to _Vcc , and grounded via ground selection transistors 15-1, 15-2, etc., that is, _Vss
It is connected to the. The gates of all these transistors 15-1 etc. forming the ground selection 15 are connected to line 7.
7 to the selector 76. Ground selection 76 acts to energize only one of lines 77 for a given Y address, so only one of transistors 15-1, 15-2, etc. is conductive.

A small portion of the cell array of FIG. 8 is shown in FIG. 9, consisting of 16 cells 10' and four X address lines 13.
5 forming the Y output line 105 or ground line 107.
Contains a piece of metal. Figures 9 and 10
As shown in the cross-sectional views of Figures A-10D, source and drain regions 102, 103 are formed by N+ diffusion regions within a continuous web of X-shaped moat regions, said moat regions being channel regions between each source and drain. 109 and contact areas 110, 111 for contacting the metal moats. Metal output wire 105 contacts the common N+ region 112 of the mote at contact region 110, and metal ground wire 107 contacts the common N+ region of the mote at region 111. Each common region 112 or 113 forms the source or drain of four transistors 10', respectively. The cell array is formed in the plane of a silicon bar 114, with a thick field oxide 15 covering the entire plane except for the moat region.
A P+ channel stop region 116 underlies the field oxide in the conventional manner. The shallow N+ arsenic implanted regions 102', 103' act as extensions of the source and drain regions 102, 103 where the control gate 111 overlaps the floating gate 104, and the P region 11 formed by rapidly diffusing boron.
7 offers advantageous programming efficiency with conventional P+ tanks. A thin layer of gate oxide 118 insulates the floating gate from channel 109 and a thin layer of oxide 119 insulates the floating gate from control gate 101 . A thin layer of deposited interlevel oxide 120 separates the second level polysilicon forming the x-rays 13 and control gate 101 from metal lines 105,107.

EPROM cell 10' is programmed by applying a high voltage of approximately +18V between drain 103 and source 102 and holding the control gate of the selected cell at _Vpp . The high current flowing through the cell causes electrons to be emitted through gate oxide 118 and charge floating gate 104 . This acts to increase the threshold voltage of the cell by approximately _Vcc (typically +5V). The charge on the floating gate remains indefinitely. Erasing is accomplished by exposing the device to ultraviolet light and discharging the floating gate 104.

For proper operation, the selection circuit and cell matrix must meet certain conditions. To program the cell, place approximately + on drain 103.
Requires 18V voltage and 0.5-3.0mA source-drain current. Reading an EPROM matrix cell requires sensing a current in the range of 15-60 μA.

For example, for a read operation in the circuit of FIG. 8, Xa (one of the row address lines 13) is high ( _Vcc - _Vt ) and transistors 15-2 and 16-2 are turned on by ground and the column selector. Ru. All other transistors 15 and 16 are off. transistor 15
-2 must be large enough to pull down the load device 108a on this line, forcing the current in transistors 10a', 10c' to ground and maintaining node 111a at a very low level of approximately 0.2-0.3V. Load 108b needs to charge node 111b to the point where cell 10'b is turned off. This eliminates the need for sense amplifier 17 connected to output line 106 to charge to and beyond the capacitance of node 111b. Cell 10'b is connected to node 1 due to the body effect of transistor 10'.
Turn off at low voltage on 11b. Body effects are large due to the P+ regions in the channels used in the fabrication of these transistors.

To program cell 10'a, the same transistors 15-2, 16-2 are turned on for a read operation (the others are off), but in this case the ON transistors 15-2, 16-2 are turned on as described above. A circuit with transistors 72, 73, 74 has a large positive voltage V _pp on its gate. Transistor 15-2 connects node 111a to approximately
It must be large enough to hold 0.3V and pass 1-3mA. Transistor 16-2 has a large voltage +V _pp on its drain and node 110
produces a large voltage on a. Load 108b again charges node 111b, in this case cell 10'b
does not program. + on node 111b
A voltage of 3V inhibits programming of cell 10'b.

Each column line 105 is connected by a load transistor 121.
V _cc and the gates of these load transistors have a reference voltage Rh. Column line 105 is thus connected to output node 12 of the inverter circuit.
2, the selected one node 122 will be at a voltage level that depends on the ratio of the load transistor to the selected storage cell 10'. For programmed cells with floating gates charged, transistor 10' is not conducting and line 105 (node 122) is at maximum voltage; for erased cells 10' with floating gates discharged, line 105 is at maximum voltage.
Let be the minimum voltage. Approximately midway between these extremes is the reference point for differential sense amplifier 17. One input to each sense amplifier 17 is from node 122 via line 106 to Y select transistors 16-1, 16-2, etc. The other input is from the reference voltage generator circuit described below.

FIG. 11 shows the sense amplifier 1 along with a circuit for generating the reference voltage Rh used for the load 121 of the cell array, the voltage Vref of the differential sense amplifier, and the reference voltage R1.
7 is shown.

The reference voltage Vref used as one input of the sense amplifier 17 is connected to the transistor 1 in the cell array.
EPROM transistor 1 manufactured similarly to 0'
0'' and a load transistor 121' similar to load transistor 121 (but with twice the channel width to create the midpoint). Load transistor 108' and ground transistor 15' are connected to a "virtual ground" column. Simulate a load 108 and a grounding device 15-1, etc. for line 107. The voltage to the gate of transistor 15' on line 77' is approximately ( _Vcc - _Vt ), i.e.
is the same as the selected voltage of one of the wires 77,
The line 107' in the reference generator therefore exhibits exactly the same voltage, impedance, etc. as the selected line 107 in the array. Transistor 10'' has a voltage on its gate (generated by transistor 123), which is also approximately ( _Vcc - _Vt ) and equal to the voltage on selected x-ray 13. Thus node 12
The circuit under node 122 in the cell array on one side of 2' is simulated, and the operation is the same as that of the cells in the array, with changes in supply voltage, temperature,
Track any variations due to aging, process variations in threshold voltage, etc. On the load side, node 122' is connected to _Vcc via two load devices. On the load side, node 122' is connected to _Vcc via two load devices. First, one of the load transistors 121 of the column line 105 of the array
A load transistor 121' is used corresponding to each one. Transistor 121' has the same reference voltage Rh on its gate as transistor 121. This reference voltage Rh on line 124 is approximately 4V for a device where _Vcc = +5V. Rh is node 12
2 is chosen to optimize the voltage change on the voltage drop, which is sufficient to be sensed but not at a full logic level. A load transistor 125, which has a different reference voltage R1 on its gate, is then in parallel with load transistor 121'.

In the exemplary embodiment, load transistor 121' has a channel twice as wide as transistor 121, and thus has half the impedance. Another way to achieve the same effect is to use the same load transistor 121' as 121 with two transistors 10'' instead of one in series. Both produce a Vref voltage at node 122', which This is half the voltage change on node 122 between the programmed and erased states for select transistor 10'. At time 126, select x-ray 13 goes high, as shown by line 127 in FIG. 11a. X selection voltage is full wave from V _ss to V _cc
From V _cc or smaller V _ss (V _cc −V _t )
up to. As shown by line 128, the voltage on node 122 will be lower than line 129 because transistor 10' will not turn on if the selected cell is programmed (floating gate charging).
The level is determined by the Rh voltage shown in . On the other hand, if selected transistor 10' is erased, node 122 starts discharging at time 130 when voltage 127 on selected row line 13 exceeds the threshold voltage of transistor 10'. As voltage 127 continues to increase, the current through transistor 10' increases and the voltage on node 122 increases as shown by curve 131.
Increases until leveled off at levels dependent on Rh level. If Rh is too low, node 122 must be grounded and the column lines must be charged, which is unnecessary and undesirable.
If Rh is too high, level 128 will be too high and will be close to V _cc . It can be seen that Vref is at an intermediate level between voltage level 132 (for programmed transistor 10') and level 133 (which is the final level at node 122 for erased transistor 10').

Second load transistor 125 and reference voltage
The function of R1 is to offset Vref to a level above the normal level 134 of Figure 11a during the time the device is in power down mode. This is because in power down mode all row lines 13 and virtual ground selection 77 are at _Vss , so all column lines 105 are at maximum level. When exiting power down mode, select column line 1
05 can be discharged or not discharged depending on the state of the selected cell 10'. If column line 105 is not discharged (ie, selected cell 10' is programmed), valid data is already present on line 106.
When the selection line 105 starts discharging (that is, the selection cell 1
0' is erased), line 106 at the input of sense amplifier 17 until line 105 is below the Vref value.
There is no valid data. R1 and load 12
The function of 5 is to make Vref higher than normal, so that when the column line 105 discharges along the curve 131, it crosses the Vref level 134 early, so that valid data can be detected early. In the power-up state, the load transistor 121'
Vref is controlled, and R1 is a DC level smaller than that of Rh. Thus, under power-up conditions, transistor 125 in the Vref generator
is cut off and Vref is controlled only by Rh. When the device is in power down mode, R1 is Rh
Load transistor 1 becomes higher than level 129
25 takes control and Vref becomes higher. Upon exiting the power down mode, the second load 125 is slowly turned off as R1 becomes lower due to the RC delay. This gradual turn-off is Vref
This is necessary to prevent Vref from returning to normal too quickly, but Vref must be around the normal level 134 within the access time, so subsequent cycles that sense the column line transition from low to high are abnormal. Don't be too lenient.

The circuit used to generate Rh and R1 is shown in FIG. Rh is a fixed level 129 produced by a divider having three transistors, a depletion load 135, a low threshold device 136, and an enhancement transistor 137. Output node 124 is at Rh level. A similar set of differently sized transistors 135-137 develops the R1 level on line 138, and for power down, transistor 139 in parallel with transistor 135 turns on to increase the voltage on R1.
Therefore, the signal CE becomes low and the transistor 14
0 is turned off and node 141 is brought to _Vcc by depletion load 142. MOS diode pair 143 acts as a resistor, keeping the gate of transistor 139 near _Vcc as long as the power down mode exists. At the end of power down, CEC goes high, node 141 goes low, and the gate of transistor 139 is connected to resistor 143.
Then, the MOS capacitor 144 is discharged according to the time constant of the RC circuit.

Sense amplifier 17 may be any of a number of differential amplifiers known to those skilled in the art. For example, a differential amplifier circuit is shown in FIG. 11, which can be used as a sense amplifier. The circuit consists of a balanced pair of driver transistors 145 along with depletion load transistors 146. Transistor 147 grounds both driver transistors and has a bias on its gate to operate it as a current source. One input 148 is connected by output line 106 to node 122 on select column line 105, and the other input 149 is connected to node 122', the Vref voltage. Outputs 150 and 151 are input 14
Depending on the polarity of the voltage difference on 8,149, it will become _Vcc or _Vss . Typically, several stages of the circuit shown in FIG. 11 are cascaded to form a high gain sense amplifier. In other words, outputs 150 and 151 are the next stage 1
52 inputs 148, 149, and so on. Final output 11 is one of the last lines 150 or 151 and represents a full wave logic level.

It is important to note that differential sense amplifiers sense voltage rather than current. The voltage on node 122 or 122' is the voltage on input transistor 14.
Only the gate of 5 needs to be charged and there is no significant current loading other than this transition. By using a different selection mechanism in this manner, no voltage drop occurs across Y selection transistor 16-2 or other decode transistors.

All wires 105 are charged through load 121 and all ground wires 107 are charged through load 108. Only selected column lines 105 are discharged during a read cycle; they are not necessarily grounded.
In the power down state, all the X selection wires 13 are grounded, and all the ground selection wires 77 are also grounded,
Therefore, the column line 105 is not discharged and DC power is not lost. All column lines 105 are held at bias point 128 in Figure 11a, so there is no delay in precharging the array at the end of power down. The access time at the end of power-down must be the same as in normal operation.

The floating gate device 10' can be programmed only when operating at sufficiently high drain 103 and gate 101 voltages in the saturation region.
It is a characteristic of The device does not program in linear mode. When applying a programming voltage to the virtual ground array, the selection device 1 to be programmed
Care must be taken that only 0' receives a sufficiently high voltage in the saturation region.

FIG. 12 shows a circuit diagram of the high voltage programming control circuit. When V _pp on pin 20 goes to a high voltage level of approximately +21V, five transistors 15
A voltage divider formed by 4 generates a voltage on node 155 which switches two inverters 156 to generate a write enable command WE on line 157. Thus, if V _pp is low, WE is low, and if V _pp is high, WE is high.
Also, commands are generated by other inverters.
Logic circuit 158 provides chip selection and power down/program PD/
It receives the WE (or) command along with the PGM command and generates a program enable command in line 159 in response. When _Vpp is high, the program enable command is active low, and PD/ is a logic 0, and if one or both of pins 21, 22 are high, a program inhibit condition exists. Transistor 160 receives the PE command on its gate and produces an output on node 161 with a series load, which is the VPR command used in the high voltage circuit of row address output 13 of FIG. thus
When PE is low, node 161 will be near V _pp
All 256 transistors 7 of 256 row lines 13
Turn on 2. Node 161 also drives the gate of transistor 162 in series with four transistors 163 in the voltage divider, which together with inverter 164 generates a voltage on the gate of transistor 165 to generate VPC. A natural depletion transistor 166 in series with transistor 165 and short transistor 167 develops a voltage on node 168 that is high near _Vpp when VPR is low, and is somewhat lower because VPR is high. It's delayed. As shown in Figures 6 and 7, each transistor on all lines 77 and 79 for ground selection and column output selection of the high voltage circuit.
VPC is applied.

A programming circuit that applies high voltage input data to select column line 105 is shown in FIG. 8 pin 1
1 each have 8 separate data buffers 17
0 on line 159, and data inbuffer 170 is enabled only when line 159 is low. The output of buffer 170 is connected to each line 106 by a high voltage circuit including an inverter stage having a driver transistor 171 with two series loads 172, 173, and when the data input bit is low transistors 174, 17
A high voltage is generated at the gate of 5. This results in
A _Vpp voltage is applied to line 106 via line 176. Transistor 177 in the high voltage circuit operates similarly to transistor 71 described above. Array discharge command
Transistor 178 is connected to line 176 when ARD is high.
ground.

In operation, the programming circuit operates to apply a high voltage to only one cell in each group in the programming mode, but there is no high voltage in other modes. Since V _pp can be held high, there is no need for external circuitry to quickly switch this high voltage, and in expensive circuits this external circuitry is necessary and creates undesirable transients. When the device is deselected (in power-down mode)
The command on node 159 is high and VPR and
VPC is held at ground voltage via transistors 160 and 167. The high voltage supply is then brought from the low state to the high state _Vpp , and this high voltage is sensed at node 155 to generate WE. _Vpp remains high for the duration of the programming sequence. When the device is selected (ie, powered up) and PD/ is low and WE is high, programming mode is entered low. Before VPR goes high, all column lines 105 except the select line and virtual ground line 107 are normal biased near _Vcc by load transistors 108 and 121. Selected row line 13 is at _Vcc , but all cells 10' on this line are in triode operation, even if the data input bit is low and line 1
No programming occurs when 06 charges high via line 176. Selection transistor 16-2
etc. has only V _cc on the gate, so the line 105 is
Do not allow voltages near V _pp to reach. Here node 1
The VPR command on 61 begins charging towards the _Vpp level through the depletion load, and VPC is held at ground voltage by transistor 165. When VPR on node 161 rises above approximately 10V, timing circuits 162-164 begin to release VPC. Approximately for VPR to reach V _pp
It takes 10 μS, and the delay from when VPR starts rising until VPC starts changing is approximately 1.5 μS. The selected row line 13 reaches the programming voltage earlier than the selected column line 105, so that the source-drain paths of all transistors 10' in the selected row are highly conductive (whether the floating gate is precharged or not). ), the balanced charge sharing state is reached before one column goes high. Then VPC
When is near V _pp , data in is low or logic 0.
Assuming , a high voltage will occur on select line 79 and a high voltage from line 106 can reach select line 105. This selection line 105 voltage is
To increase towards V _pp , the adjacent unselected column line 105 and virtual ground line V _pp are pulled up by the high voltage of the control gate on line 13 . However, only the selected cell 10a' is saturated with sufficient voltage to perform programming, and the cell 10b' on the other side of the selected column line 105 from the selected cell 10a' is also saturated, but since it has a large voltage at the source node 111b, programming is performed. cannot conduct sufficiently to do so. On the other hand, the source of cell 10c' is grounded at node 111a via transistor 15-2, the gate is at V _pp via line 13, but the drain is at near V _cc via load 121;
This cell does not program. VPR and VPC
is high, up to 50 mA, but tends to deprogram through the mid-level oxide 119. All nodes 11 (excluding the selected node 111a)
This tendency is significantly reduced since a charge of 1 causes the voltage across this oxide to be low except for cells 10' in a given row. The deprogramming effect is reduced because only one wire 107 is grounded, allowing other nodes to charge and select cell 1.
This is because the gate-to-source or drain voltage of cells other than 0a' is reduced. When the selected cell is held at the programming voltage for a sufficient period of time (perhaps 10-50 mS), the PD/(i.e.) voltage goes high and transistors 160,
167 is turned on and VPR and VPC go low. At this point, the high voltage on select column line 105 must be carefully removed. If large array capacitance is discharged through the storage cells, programming will occur in unselected cells. Thus, bleeder transistor 178 provides a path for removing excess voltage from the common line through select transistor 16-2, etc., and common line 106. The extra voltage on virtual ground line 107 does not represent parasitic programming disturbances due to bias on the column lines. The array discharge voltage ARD is essentially complementary to PD/, but occurs only when _Vpp is high, and thus in the program inhibit mode of operation. The device is powered down during the program inhibit period.

A semiconductor device including the entire system of FIG. 1 is a dual level polysilicon, N-channel,
Made with a self-aligning process and advantageously employing a double diffusion step, Texas Instruments patent application SN072504 dated September 4, 1979
Generates a programming enhancement P+ region as disclosed in No.

Standard enhancement mode MOS transistors (40, 41, 49, etc. in Figure 5, etc.) generated in the process used have a threshold voltage of approximately +0.8 to +1.0V, assuming _Vcc to be +5V. This threshold is the result of a conventional blanket boron implant of a photoresist protected native transistor. Natural transistors 45, 48, 54, etc. are unimplanted and have thresholds of approximately +0.2 to +0.3 V, resulting in low source-to-drain voltage drops, which are advantageous in many parts of the illustrated circuit. It is. The third type of transistor is 42, 47, 5
A standard depletion transistor such as 0, with a blanket boron implant for standard enhancement equipment, accepts a selected N-type implant to produce a threshold of approximately -3.4V. A fourth type is a "natural depletion" device, which has a threshold of approximately -3.8 to -4.0V to accept an N-type implant rather than a boron implant, and these devices are used, for example, in high voltage circuits to
Used as 3,74.

The decoding circuit described above can be used not only in EPROM but also in other types of memory devices such as ROM and read/write memory. Similarly, the input buffer as well as sense circuit and power down features are useful in other types of devices.

Therefore, although the invention has been described in terms of embodiments, this description is not to be construed in a limiting sense. Other embodiments and various modifications of the invention will be apparent to those skilled in the art upon reviewing this description. The appended claims cover all such modifications and embodiments that fall within the true scope of the invention.

[Effects of the Invention] According to the circuit configuration of the present invention, a transistor circuit can quickly start up from a power-down state.

[Brief explanation of drawings]

FIG. 1 is an electrical block diagram of a floating gate EPROM type semiconductor memory device using features of the present invention; FIGS. 2 and 2' are timing diagrams showing voltages at various points in FIG. 1 as a function of time; FIG. 3 is an electrical circuit diagram of the input buffer used in the device shown in FIG. 1, and FIG. 4 is an electrical circuit diagram of the predecoder circuit used in the device shown in FIG.
Figure a shows the input buffer for A0 and A1 bits, Figure 5 shows the electric circuit diagram of the row decoder and selection circuit used in the device shown in Figure 1, and Figure 6 shows the decoder used for virtual ground selection in the device shown in Figure 1. electrical circuit diagram,
7 is an electrical circuit diagram of the column selection decoder used in the system of FIG. 1, FIG. 8 is an electrical circuit diagram of the cell array of the device of FIG. 1, and FIG. 9 is a physical diagram of the cell array of the device of FIG. An enlarged view of a small part of the semiconductor chip showing the layout; FIGS. 10A to 10D are cross-sectional elevational views taken along lines A-A, B-B, CC, and D-D in FIG. 9; FIG. 11 11a is an electrical diagram of the sense amplifier and reference voltage generator of the device of FIG. 1, FIG. 11a is a schematic diagram of the column line bias points, and FIG. 12 is a circuit diagram of the high voltage programming control circuit. 15...Ground selection, 16...Column selection, 17...Sense amplifier and data buffer, 23...Control and clock generator, 30...Input buffer, 32
...Pre-decoder, 33...Shared decoder, 35...64
Middle 1 row decoder, 37...Multiplex, 76...
1st ground selection out of 9, 1st row selection out of 78...8.

Claims (1)

[Scope of Claims] 1. A transistor circuit having a first input terminal, a second input terminal, and a circuit activation terminal, the transistor circuit having: (a) a source, a drain, and a gate, the gate of which is connected to the first input terminal; (b) an enhancement mode MOS transistor having a source, a drain, and a gate, the gate of which is connected to the second input terminal; (c) the depletion mode MOS transistor connected to the second input terminal; A MOS transistor connected between the transistor and the enhancement mode MOS transistor to provide a power-down function, the drain of the power-down function MOS transistor being connected to the source of the depletion mode MOS transistor for output. make,
The transistor circuit, wherein the source is connected to the drain of the enhancement mode MOS transistor, and the gate is connected to the activation terminal. 2. The transistor circuit according to claim 1, wherein the power-down function MOS transistor has a lower threshold in absolute value than the enhancement mode and depletion mode MOS transistors. 3. The transistor circuit according to claim 1, wherein the input signals applied to the first and second input terminals are mutually inverted signals.