JPS6364055B2 - - Google Patents
Info
- Publication number
- JPS6364055B2 JPS6364055B2 JP58171992A JP17199283A JPS6364055B2 JP S6364055 B2 JPS6364055 B2 JP S6364055B2 JP 58171992 A JP58171992 A JP 58171992A JP 17199283 A JP17199283 A JP 17199283A JP S6364055 B2 JPS6364055 B2 JP S6364055B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- substrate
- semiconductor chip
- powder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
- H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
- H10W74/473—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins containing a filler
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07236—Soldering or alloying
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
- H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/321—Structures or relative sizes of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/877—Bump connectors and die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
〔発明の利用分野〕
本発明は、半導体チツプの電極端子をCCB法
(Controlled Collapse Bonding法)により基板
上の電極端子に接合した後、樹脂により被覆して
なる構造の半導体装置に関する。
〔発明の背景〕
このような構造の半導体装置が適用された具体
的な一例として、第1図に示す要部断面構造図の
ように、液晶表示素子の形成されたガラス基板上
に、その液晶表示素子を駆動する半導体チツプを
載置して一体形成したものが知られている。即
ち、ガラス基板1の上面に形成された電極端子2
と、シリコン半導体からなる半導体チツプ(以
下、Siチツプと称する)3の下面に形成された電
極端子4とを対向配置し、これらの電極端子2,
4間をCCB法により形成されるはんだバンプ5
によつて接合し、次にシリコンゲル等の如き柔軟
性を有する樹脂6を、ガラス基板1とSiチツプ3
の空〓部に充填し、さらに、Siチツプ3の上及び
側面を炭酸カルシウムを混入したビスフエニール
型の低膨張エポキシ系樹脂7により被覆した構造
となつている。
ところが、上述構造の半導体装置について、−
40℃←→100℃の温度条件で温度サイクル試験を行
つたところ、被覆のないもの(以下、裸チツプと
称する)よりも耐熱疲労性がかなり劣るという結
果が得られた。そこで、その原因を実験等により
検討した結果、(1)樹脂材料、(2)樹脂被覆構造、及
び(3)はんだバンプ構造の3点について、次に述べ
るような欠点があることが判つた。
即ち、炭酸カルシウム粉をエポキシ樹脂に混入
すると、膨張係数を大きく下げることができる
が、Siチツプやガラス基板に比較するとまだ大で
あること、しかも炭酸カルシウムの混入率を増す
と樹脂の硬度が増大することから、必らずしも耐
熱疲労性は向上しない。
また、低膨張エポキシ樹脂を用いた樹脂被覆の
形状、及びはんだバンプの形状に関する応力分
布、特に応力集中及びはんだバンプの柔軟性は、
耐熱疲労性に大きく影響する。
〔発明の目的〕
本発明の目的は、耐熱疲労性を向上させること
ができる被覆樹脂の材料、被覆の形状、及びはん
だバンプの形状を有してなる半導体装置を提供す
ることにある。
〔発明の概要〕
本発明は、被覆樹脂はエポキシ樹脂を主材料と
し、これにエポキシ樹脂よりも小さい熱膨張係数
を有する無機材料からなる第1の粉粒体、及びゴ
ム状弾性材料からなる第2の粉粒体を少なくとも
混入したものとし、
また、前記被覆樹脂は半導体チツプの周囲とそ
の上面を被い、且つ前記半導体チツプ周辺の基板
上面に形成する樹脂被覆の幅は、その幅方向の半
導体チツプ幅の1倍以上1.5倍以下とし、
さらに、はんだバンプの形状は円柱型又はつづ
み型に形成することによつて、耐熱疲労性を向上
させようとするものである。
〔発明の実施例〕
以下、本発明を実施例に基づいて説明する。
まず、本発明の被覆樹脂材料について説明す
る。エポキシ樹脂の熱膨張係数αROは約100×
10-6/℃であり、半導体チツプ、例えばSiチツプ
の熱膨張係数αSi;3×10-6/℃や、基板、例えば
ガラス基板のソーダガラスの熱膨張係数αG;9.33
×10-6/℃に比べて大きい。一般に、耐熱疲労性
を向上させるには、熱膨張係数が半導体チツプや
基板のそれに近い被覆樹脂を適用することが望ま
しい。
そこで、エポキシ樹脂に炭酸カルシウムや石英
粉等の如き、熱膨張係数の小さな無機材料(以
下、低膨張化材と称する)を混入して低膨張化す
るようにしている。例えば、体積にして50%の石
英粉を混入すると、熱膨張係数αRは約25×10-6/
℃に低下する。しかし、混入率を高くするにした
がつて樹脂の粘度が高くなり、流動性が低下す
る。流動性が低下すると、被覆工程において、は
んだバンプ周囲の空隙部に樹脂が侵入しにくくな
つて、空隙部が残つたり、基板との密着性が低し
たり、被覆の作業性が低下するという問題が生ず
る。この結果、逆に耐熱疲労性及び耐湿性が低下
してしまうことがある。また、混入率を高くする
と樹脂の柔軟性が低下して、基板との接着部に応
力が集中するため、この応力によりガラス等の基
板が破損されてしまうことがある。
したがつて、単に低膨張化材を混入して低膨張
化するだけでは、耐熱疲労性の向上に一定の限度
があるため、さらにその流動性及び柔軟性を改善
する必要がある。
そこで、本発明は低膨張化材に加て粒状の弾性
材料、例えばポリブタジエンやシリコン等のゴム
粒子を分散混入し、これによつて柔軟性及び流動
性を向上させようとするものである。つまり、被
覆樹脂内のゴム粒子は応力緩衝材として作用する
ので柔軟性が向上して応力集中や歪が緩和される
ことから、これによつて耐熱疲労性を向上させよ
うとするものである。また、粒状のゴム粒子の作
用によつて流動性を向上させようとするものであ
る。
しかし、後述するように、ゴム粒子の混入率に
も最適な範囲がある。例えば、粒径1μmレベル
のポリブタジエン(CTBN 1300×9)からなる
ゴム粒子を混入した場合、エポキシ樹脂に対する
ゴム粒子の重量比を100対20以上(以下、重量部
又は単に部と称し、例えば20部以上と表現する)
にすると、ゴム粒子の分散が不均一になつてしま
うとともに、ポリブタジエンの熱膨張係数αPBは
約80×10-6/℃と大きいので、混入後の被覆樹脂
の熱膨張係数αRが大となつてまい、耐熱疲労性を
低下させる原因となるのである。また、流動性向
上の効果にあつても、飽和現象があるので大幅向
上は期待できない。
これらのことを、実施例を用いて行なつた実験
結果に基づいて説明する。第1表に、エポキシ樹
脂(EP−828)を主材料とし、粒径約1μmの石英
粉を低膨張化材とし、粒径約1μmのポリブタジ
エンの均一なゴム粒子を緩衝材とし、それらの混
入率の異なる種々の樹脂により被覆した半導体装
置を試料として、前述と同一の温度サイクル試験
を行なつた判定結果を示す。なお、基板、半導体
チツプ及びはんだバンプは第1図図示と同一構成
のものとし、判定は、樹脂被覆を施さない裸チツ
プのものに比較して、早いサイクルにて故障に至
つた試料を不合格として×印で示し、合格したも
のについては故障率を基準に、優れている順に
〇、△印で示した。故障率の一例として、第2図
Aに石英粉の混入率を35体積%に固定し、ポリブ
タジエンゴム粒子の混入率を変化させた場合を、
第2図Bにポリブタジエンゴム粒子の混入率を10
部に固定し、石英粉の混入率を変化させた場合
を、それぞれ示す。なお、第2図A,B図中実線
で示したものは、1サイクル/1時間の温度サイ
クル試験を900サイクル行なつた例であり、図中
点線で示したものは同様に500サイクルの例であ
る。
また、被覆樹脂には硬化温度を低くするための
添加剤、例えば硬化促進剤としてイソダゾル
(2P4MHz)を5重量%、硬化剤としてジシアン
アミドを10重量%、シランカツプリング剤(A−
187)を2重量%等を混入し、硬化温度130℃、硬
化温度1時間として基板の熱的影響を避けるよう
にした。
[Field of Application of the Invention] The present invention relates to a semiconductor device having a structure in which electrode terminals of a semiconductor chip are bonded to electrode terminals on a substrate by a CCB method (Controlled Collapse Bonding method) and then coated with a resin. [Background of the Invention] As a specific example to which a semiconductor device having such a structure is applied, as shown in the cross-sectional structural diagram of main parts shown in FIG. A device in which a semiconductor chip for driving a display element is placed and integrally formed is known. That is, the electrode terminal 2 formed on the upper surface of the glass substrate 1
and electrode terminals 4 formed on the lower surface of a semiconductor chip (hereinafter referred to as Si chip) 3 made of a silicon semiconductor are arranged facing each other, and these electrode terminals 2,
Solder bump 5 formed between 4 by CCB method
Then, a flexible resin 6 such as silicon gel is applied to the glass substrate 1 and the Si chip 3.
Furthermore, the top and side surfaces of the Si chip 3 are coated with a bisphenylic low expansion epoxy resin 7 mixed with calcium carbonate. However, for the semiconductor device with the above structure, -
When a temperature cycle test was conducted under the temperature conditions of 40℃←→100℃, the result was that the thermal fatigue resistance was considerably inferior to that of chips without coating (hereinafter referred to as bare chips). As a result of examining the causes of this through experiments and the like, it was found that there are three drawbacks as described below regarding (1) the resin material, (2) the resin coating structure, and (3) the solder bump structure. In other words, when calcium carbonate powder is mixed into epoxy resin, the expansion coefficient can be significantly lowered, but it is still large compared to Si chips or glass substrates.Moreover, increasing the mixing rate of calcium carbonate increases the hardness of the resin. Therefore, thermal fatigue resistance does not necessarily improve. In addition, stress distribution related to the shape of the resin coating using low expansion epoxy resin and the shape of the solder bump, especially stress concentration and flexibility of the solder bump,
Significantly affects thermal fatigue resistance. [Object of the Invention] An object of the present invention is to provide a semiconductor device having a coating resin material, a coating shape, and a solder bump shape that can improve thermal fatigue resistance. [Summary of the Invention] According to the present invention, the coating resin is mainly made of epoxy resin, and a first granular material made of an inorganic material having a coefficient of thermal expansion smaller than that of the epoxy resin, and a first part made of a rubber-like elastic material. The coating resin covers the periphery and the top surface of the semiconductor chip, and the width of the resin coating formed on the top surface of the substrate around the semiconductor chip is such that the width of the resin coating is in the width direction. The solder bumps are designed to have a width of 1 to 1.5 times the width of the semiconductor chip and to form the solder bumps into a cylindrical or cylindrical shape in order to improve thermal fatigue resistance. [Examples of the Invention] The present invention will be described below based on Examples. First, the coating resin material of the present invention will be explained. The coefficient of thermal expansion α RO of epoxy resin is approximately 100×
10 -6 /℃, the thermal expansion coefficient α Si of a semiconductor chip, such as a Si chip; 3×10 -6 /℃, and the thermal expansion coefficient α G of a substrate, such as a glass substrate, soda glass; 9.33.
It is larger than ×10 -6 /℃. Generally, in order to improve thermal fatigue resistance, it is desirable to use a coating resin whose coefficient of thermal expansion is close to that of semiconductor chips and substrates. Therefore, an inorganic material with a small coefficient of thermal expansion (hereinafter referred to as a low-expansion material), such as calcium carbonate or quartz powder, is mixed into the epoxy resin to reduce the expansion. For example, when 50% by volume of quartz powder is mixed, the coefficient of thermal expansion α R is approximately 25×10 -6 /
The temperature drops to ℃. However, as the mixing rate increases, the viscosity of the resin increases and fluidity decreases. When fluidity decreases, it becomes difficult for the resin to penetrate into the voids around the solder bumps during the coating process, resulting in voids remaining, poor adhesion to the board, and reduced coating workability. A problem arises. As a result, thermal fatigue resistance and moisture resistance may be adversely reduced. Furthermore, when the mixing rate is increased, the flexibility of the resin decreases and stress is concentrated at the bonded portion with the substrate, which may damage the substrate such as glass. Therefore, there is a certain limit to the improvement of thermal fatigue resistance simply by mixing a low expansion material to lower the expansion, so it is necessary to further improve the fluidity and flexibility. Therefore, the present invention attempts to improve the flexibility and fluidity by dispersing and mixing particulate elastic material, for example, rubber particles such as polybutadiene or silicone, in addition to the low expansion material. In other words, the rubber particles in the coating resin act as a stress buffer, improving flexibility and alleviating stress concentration and strain, thereby improving thermal fatigue resistance. Further, it is intended to improve fluidity through the action of granular rubber particles. However, as will be described later, there is an optimum range for the mixing ratio of rubber particles. For example, when rubber particles made of polybutadiene (CTBN 1300 x 9) with a particle size of 1 μm are mixed, the weight ratio of the rubber particles to the epoxy resin should be 100:20 or more (hereinafter referred to as parts by weight or simply parts; for example, 20 parts). (expressed as above)
If this is done, the rubber particles will not be uniformly dispersed, and since the coefficient of thermal expansion α PB of polybutadiene is large at approximately 80×10 -6 /℃, the coefficient of thermal expansion α R of the coating resin after mixing will be large. This causes fatigue and reduces thermal fatigue resistance. Furthermore, even if the fluidity is improved, a significant improvement cannot be expected because of the saturation phenomenon. These matters will be explained based on the results of experiments conducted using Examples. Table 1 shows that the main material is epoxy resin (EP-828), quartz powder with a particle size of about 1 μm is used as a low-expansion material, and uniform rubber particles of polybutadiene with a particle size of about 1 μm are used as a buffer material. The results of the same temperature cycle test as described above are shown below, using semiconductor devices coated with various resins with different ratios as samples. Note that the substrate, semiconductor chip, and solder bumps have the same configuration as shown in Figure 1, and the judgment is that samples that fail in an earlier cycle than those of bare chips without resin coating will be rejected. Those that passed were marked with an "X" mark, and those that passed were marked with a "○" or "△" mark in order of superiority based on the failure rate. As an example of the failure rate, Figure 2A shows the case where the mixing rate of quartz powder is fixed at 35% by volume and the mixing rate of polybutadiene rubber particles is varied.
In Figure 2 B, the mixing rate of polybutadiene rubber particles is 10
The graph shows the cases where the quartz powder is fixed at a certain area and the mixing rate of quartz powder is varied. The solid line in Figures 2A and B is an example of 900 cycles of 1 cycle/1 hour temperature cycle test, and the dotted line in the figure is an example of 500 cycles. It is. The coating resin also contains additives to lower the curing temperature, such as 5% by weight of isodazole (2P4MHz) as a curing accelerator, 10% by weight of dicyanamide as a curing agent, and a silane coupling agent (A-
187) in an amount of 2% by weight, etc., and the curing temperature was set at 130° C. for 1 hour to avoid thermal effects on the substrate.
【表】【table】
以上説明したように、本発明によれば、耐衝
撃、耐振動等に優れている樹脂被覆型の効果に加
えて、耐熱疲労性が向上されるという効果があ
る。
As explained above, according to the present invention, in addition to the effects of the resin-coated type which are excellent in shock resistance, vibration resistance, etc., thermal fatigue resistance is improved.
第1図は従来例の断面構造図、第2図A,Bは
それぞれ本発明の一実施例の故障率を示す線図、
第3図Aは被覆厚と応力との関係の一例を示す線
図であり、同図B,Cはその説明図、第4図Aは
半導体チツプ幅に対する被覆幅と応力との関係の
一例を示す線図であり、同図B,Cはその説明
図、第5図ははんだバンプの形状図、第6図はは
んだバンプ形状と熱疲労寿命及び機械的強度との
関係を示す線図、第7図A,Bははんだバンプの
応力分布図、第8図は本発明の一実施例の断面構
造図、同図Bは説明図、第9図は本発明の他の実
施例の断面構造図、第10図は本発明法の適用さ
れたCCB接合法による装置の構成図、第11図
は第10図図示実施例の動作説明のためのはんだ
バンプ温度を示す線図、第12図A〜C、第13
図及び第14図は本発明の他の実施例の構造図で
ある。
1……ガラス基板、2……電極端子、3……半
導体チツプ、5……はんだバンプ、7,11……
被覆樹脂、10……はんだバンプ、15……アク
リル樹脂膜、31……多層プリント基板。
FIG. 1 is a cross-sectional structural diagram of a conventional example, and FIGS. 2A and B are diagrams showing the failure rate of an embodiment of the present invention, respectively.
FIG. 3A is a diagram showing an example of the relationship between coating thickness and stress, FIG. 3B and C are explanatory diagrams, and FIG. Figures B and C are explanatory diagrams, Figure 5 is a diagram of the shape of a solder bump, Figure 6 is a diagram showing the relationship between solder bump shape, thermal fatigue life, and mechanical strength; 7A and 7B are stress distribution diagrams of solder bumps, FIG. 8 is a cross-sectional structural diagram of one embodiment of the present invention, FIG. 7B is an explanatory diagram, and FIG. 9 is a cross-sectional structural diagram of another embodiment of the present invention. , FIG. 10 is a block diagram of a device using the CCB bonding method to which the present invention is applied, FIG. 11 is a diagram showing the solder bump temperature for explaining the operation of the embodiment shown in FIG. 10, and FIG. 12 A- C, 13th
14 are structural diagrams of other embodiments of the present invention. 1... Glass substrate, 2... Electrode terminal, 3... Semiconductor chip, 5... Solder bump, 7, 11...
Coating resin, 10...Solder bump, 15...Acrylic resin film, 31...Multilayer printed circuit board.
Claims (1)
る基板と、該基板と前記半導体チツプとの対向す
る電極端子間に形成されたはんだバンプと、該は
んだバンプ周囲の空〓部を充填して形成された樹
脂被覆とを有する半導体装置において、前記樹脂
被覆は該樹脂よりも小さい熱膨張係数を有する無
機材料からなる第1の粉粒体及びゴム状弾性材料
からなる第2の粉粒体が少なくとも混入された樹
脂からなることを特徴とする半導体装置。 2 特許請求の範囲第1項記載の発明において、
前記樹脂はエポキシ樹脂、前記第1の粉粒体は石
英、炭化シリコン、窒化シリコン、炭酸カルシウ
ム、及び酸化ベリリウムの混入された炭化シリコ
ンの少なくとも1つからなるものとし、前記第2
の粉粒体はポリブタジエンゴム及びシリコンゴム
の少なくとも1つからなることを特徴とする半導
体装置。 3 特許請求の範囲第1項又は第2項記載の発明
において、前記第1の粉粒体の混入率を30乃至55
体積%とし、前記第2の粉粒体の混入率を1乃至
20重量部としたことを特徴とする半導体装置。 4 特許請求の範囲第1項乃至第3項記載のいず
れかの発明において、前記樹脂被覆は半導体チツ
プの周囲とその上面を被い、且つ前記半導体チツ
プの周辺の基板面に形成する樹脂被覆の幅は、当
該幅方向の半導体チツプ幅の1倍以上1.5倍以下
としたことを特徴とする半導体装置。 5 特許請求の範囲第1項乃至第4項記載のいず
れかの発明において、前記樹脂被覆の周辺部領域
は、予め前記基板面に形成されたアクリル薄層を
介して当該基板に接合形成されることを特徴とす
る半導体装置。 6 特許請求の範囲第1項乃至第5項記載のいず
れかの発明において、前記基板はガラスもしくは
セラミツク材料からなる単一基板、又はガラス繊
維含有エポキシ、ガラス繊維含有ポリイミドもし
くは高弾性率高強力繊維を含有するエポキシ又は
ポリイミド多層基板であることを特徴とする半導
体装置。 7 特許請求の範囲第1項乃至第6項記載のいず
れかの発明において、前記はんだバンプの形状は
円柱型又はつづみ型に形成されたものであること
を特徴とする半導体装置。[Scope of Claims] 1. A semiconductor chip, a substrate on which the semiconductor chip is mounted, solder bumps formed between opposing electrode terminals of the substrate and the semiconductor chip, and a space around the solder bumps. In the semiconductor device, the resin coating includes a first particulate material made of an inorganic material having a coefficient of thermal expansion smaller than that of the resin, and a second part made of a rubber-like elastic material. 1. A semiconductor device comprising a resin mixed with at least powder or granular material. 2 In the invention described in claim 1,
The resin is an epoxy resin, the first powder is made of at least one of quartz, silicon carbide, silicon nitride, calcium carbonate, and silicon carbide mixed with beryllium oxide;
1. A semiconductor device, wherein the powder is made of at least one of polybutadiene rubber and silicone rubber. 3. In the invention set forth in claim 1 or 2, the mixing rate of the first powder or granular material is 30 to 55.
% by volume, and the mixing rate of the second granular material is 1 to 1.
20 parts by weight of a semiconductor device. 4. In the invention according to any one of claims 1 to 3, the resin coating covers the periphery and upper surface of the semiconductor chip, and the resin coating is formed on the substrate surface around the semiconductor chip. A semiconductor device characterized in that the width is 1 to 1.5 times the width of the semiconductor chip in the width direction. 5. In the invention according to any one of claims 1 to 4, the peripheral region of the resin coating is bonded to the substrate via an acrylic thin layer previously formed on the substrate surface. A semiconductor device characterized by: 6. In the invention according to any one of claims 1 to 5, the substrate is a single substrate made of glass or ceramic material, or made of glass fiber-containing epoxy, glass fiber-containing polyimide, or high-modulus high-strength fiber. A semiconductor device characterized by being an epoxy or polyimide multilayer substrate containing. 7. The semiconductor device according to any one of claims 1 to 6, wherein the solder bump has a cylindrical shape or a cylindrical shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58171992A JPS6063951A (en) | 1983-09-16 | 1983-09-16 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58171992A JPS6063951A (en) | 1983-09-16 | 1983-09-16 | Semiconductor device and manufacture thereof |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1325234A Division JPH0639563B2 (en) | 1989-12-15 | 1989-12-15 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6063951A JPS6063951A (en) | 1985-04-12 |
| JPS6364055B2 true JPS6364055B2 (en) | 1988-12-09 |
Family
ID=15933514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58171992A Granted JPS6063951A (en) | 1983-09-16 | 1983-09-16 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6063951A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6250180A (en) * | 1985-08-29 | 1987-03-04 | Mitsubishi Electric Corp | Thermal head drive unit |
| JPS62136865A (en) * | 1985-12-11 | 1987-06-19 | Hitachi Ltd | Module mounting structure |
| JPS62295332A (en) * | 1986-06-12 | 1987-12-22 | Fujitsu Ltd | Lead wire fixing structure for display panel |
| JPH01214032A (en) * | 1988-02-22 | 1989-08-28 | Canon Inc | Electric circuit device |
| US5121190A (en) * | 1990-03-14 | 1992-06-09 | International Business Machines Corp. | Solder interconnection structure on organic substrates |
| US4999699A (en) * | 1990-03-14 | 1991-03-12 | International Business Machines Corporation | Solder interconnection structure and process for making |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6018145B2 (en) * | 1980-09-22 | 1985-05-09 | 株式会社日立製作所 | Resin-encapsulated semiconductor device |
| JPS5821417A (en) * | 1981-07-29 | 1983-02-08 | Shin Etsu Chem Co Ltd | Curable epoxy composition |
| JPS5834824A (en) * | 1981-08-26 | 1983-03-01 | Sumitomo Bakelite Co Ltd | Epoxy resin composition and its production |
-
1983
- 1983-09-16 JP JP58171992A patent/JPS6063951A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6063951A (en) | 1985-04-12 |
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