JPS6364809B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic recording and reproducing apparatus, and more particularly to an improvement in an automatic azimuth adjustment device for a reproducing head thereof.

For example, if the azimuth of the playback head is not appropriate, a phase shift will occur between the playback signals from the left and right recording tracks, and high-frequency playback characteristics will deteriorate. To solve this problem, a device for adjusting the azimuth of a playback head using a recording signal has been proposed, for example, in Japanese Patent Laid-Open No. 14597/1983.

This device divides the recording track of one of the channels of the recording tape to be played back, for example the right channel, into an upper half and a lower half using a specially constructed playback head and scans them separately, and the playback obtained from each half is scanned separately. The amount of phase difference between signals is detected, and the azimuth of the reproducing head is automatically adjusted based on this amount of phase difference.

However, according to such conventional devices,
It is necessary to detect the amount of phase difference between the playback signals, but the amount of phase difference obtained by dividing the recording track of one channel into upper and lower parts and detecting it is usually extremely small, and based on this, the azimuth of the playback head is feedback-controlled. If adjustment is attempted by a system, the circuit configuration of this control system must be extremely complicated, which is difficult to realize in practice, and practicality is always an issue from the viewpoint of cost.

The present invention has been made in order to improve the problems of such conventional devices, and provides first and second signals formed from divided playback signals obtained by a playback head that divides and plays back the same recording track of a recording tape in the width direction of the recording track. By comparing the phases of the two phase comparison signals, generating an inverted signal that inverts to a high level and a low level in response to the phase lead or lag of one of the signals relative to the other, and applying the inverted signal to the azimuth adjustment means. The azimuth adjustment means is configured to adjust the azimuth of the reproduction head, and the azimuth adjustment means includes a dead zone setting circuit that monitors integral information of the inverted signal to start and stop adjustment, and the dead zone setting circuit detects the input of the dead zone setting circuit. The feature is that the sensitivity can be changed.

The present invention will be described below with reference to embodiments shown in the drawings.

In FIG. 1, reference numeral 1 indicates a playback head, and only the portion corresponding to the recording track of the right channel is shown. Figure 5a shows the configuration of the core of the head in this part, and Figure 5b shows the waveform of the playback signal. The core 1a and the lower half core 1b scan separately, and reproduced signals Sa and Sb are obtained in the coils a and b wound around each core.
These coils are connected in series and one end is connected to ground. Therefore, the playback signal Sa+Sb obtained from the other end is the playback signal of the entire recording track of the right channel,
The signal is sent as an audio reproduction signal from the output terminal O to an audio signal reproduction circuit (not shown). Furthermore, the reproduced signal Sb obtained from the connection point of each coil is a reproduced signal of only the lower half of this track. Therefore, when the azimuth of the reproduction head shifts, the phase of the reproduction signal Sb leads or lags the reproduction signal Sa+Sb depending on the direction, as shown in FIG. 5b.

Note that the waveform shown in FIG. 5b shows the case where a sine wave signal of a predetermined frequency is reproduced for ease of explanation.

These composite signals Sa+Sb and signal Sb are used as azimuth adjustment signals, and are used for amplifiers 2 and 3.
After the signals are made to have the same level, signal components of 2 kHz to 8 kHz are extracted through band pass filters 4 and 5, and further converted into rectangular wave signals by waveform conversion circuits 6 and 7. and diode D ₁ ,
The positive component of each rectangular wave signal passing through D ₂ is input to the phase comparison circuit 8 as a phase comparison signal.

The phase comparison circuit 8 compares the phases of the two phase comparison signals, and outputs an inverted signal whose level state is inverted to a high level Va or a low level 0 in response to the phase lead or lag of one of the signals relative to the other.
Occurs on O ₁ . The phase comparator circuit 8 consists of a D-type flip-flop circuit FF ₁ , a NOR circuit NOR, and diodes D ₃ and D _{4 .}
are a data terminal D ₁ to which the output of the waveform conversion circuit 7 is input via the diode D ₂ , a clock terminal CL ₁ to which the output of the waveform conversion circuit 6 is input via the diode D ₁ , a reset terminal R ₁ , and an output terminal Q ₁ , an inverting output terminal ₁ and a grounded set terminal S ₁ . The output terminal Q ₁ is directly connected to the output point O ₁ via the diode D ₃ , and the inverted output terminal ₁ is connected to the NOR circuit.
They are each connected to one input terminal of the NOR circuit, and the output terminal of the NOR circuit NOR is further connected to the output point _O1 via a diode _D4 . The reset terminal _R1 and the other input terminal of the NOR circuit NOR are respectively connected to an output terminal _Q2 and an inverting output terminal ₂ of a D-type flip-flop circuit _FF2 , which will be described later. D
type flip-flop circuit FF ₁ is a clock terminal
The low level to high level inversion timing of the signal input to CL ₁ , that is, the reproduction signal Sa+ shown in Figure 5b.
Data terminal every Sb zero cross timing T ₀
Capture the signal input to _D1 . Therefore, while the phase of the reproduced signal Sa is ahead of the reproduced signal Sa+Sb, a high level Va and a low level 0 are output from the output terminal Q ₁ and the inverted output terminal ₁ , respectively, and the phase of the reproduced signal Sa is ahead of the reproduced signal Sa+Sb. While lagging behind Sa+Sb, low level 0 and high level Va are output from output terminal Q ₁ and inverted output terminal ₁ , respectively.

The level detection circuit 12 enables the phase comparator circuit 8 to operate when the reproduction head 1 is reproducing an audio signal, that is, when the level of the reproduction signal is above a predetermined value, and responds to the presence or absence of an audio reproduction signal. The detection sensitivity switching circuit 13 is controlled via the time constant circuit 14 to raise or lower the detection sensitivity of the dead zone setting circuit 15. The level detection circuit 12 is D
_The reset terminal _R2 is connected to a bandpass filter 4,
The positive component of the composite output obtained by combining the outputs of 5 is given, and the data terminal
D ₂ and clock terminal CL ₂ are both grounded, and their set terminal S ₂ is connected to the power supply +Vcc. Here, the D-type flip-flop circuit _FF1 and
FF ₂ is commercially available from Tokyo Shibaura Electric Co., Ltd.
DUAL D-TYPE FLIP FLOP (product number
TC4013BP) is preferably used.

The time constant circuit 14 consists of resistors R ₁ , R ₂ , R ₃ , capacitor C ₁ , and diode D ₅ , and is the output terminal of FF _2.
Diode _D5 and resistor _R2 in response to the output state of _Q2
Charging of capacitor C ₁ through or resistors R ₁ and R ₃
The constants of _each resistor and capacitor are set so that the charging time is short and the discharging time is long.

The detection sensitivity switching circuit 13 consists of a switching transistor Tr ₁ , a diode D ₆ , a NAND circuit N, capacitors C ₂ , C ₃ , and resistors R ₄ , R _{5 ,} etc., and is particularly connected between the output point O ₁ of the phase comparison circuit 8 and the ground. A resistor R ₅ and a capacitor C ₃ connected to the inverter constitute a first integrating circuit that provides integral information of the inverted signal.

Furthermore, the dead zone setting circuit 15 is a transistor.
It consists of a width comparator/window circuit consisting of Tr ₂ , Tr ₃ , Tr ₄ , diode D ₇ , etc., and integrates the reference level Vb supplied from the reference power supply +Vb to the base of transistor Tr ₄ and the first integration circuit. Compare the outputs, and if this integrated output level is not within the dead zone level with respect to the reference level Vb, output a high level signal and close analog switches SW ₁ and SW ₂ of the switch circuit 16, which will be described later.
Also, when entering the dead zone level, a low level signal is output to open these switches.
Note that the dead zone level in this embodiment is set to Vb±1.2 volts by the forward potentials of the transistors Tr ₂ to Tr ₄ and the diode D ₇ .

The output point _O1 of the phase comparator circuit 8, which is connected to the reference power supply +Vb via the resistor _R0 , is the switch circuit 1.
Connected to 6. A capacitor C ₄ connected between the connection point of analog switches SW ₁ and SW ₂ and the reference power supply +Vb constitutes a second integration circuit with a resistor R ₆ . Further, the resistor _R7 connected in parallel to the capacitor _C4 is a discharge resistor when the analog switches _SW1 and _SW2 are open.

The output of the second integrator circuit is an analog switch.
When SW ₁ and SW ₂ are closed, the output is supplied to a motor drive circuit 9, and the output of this circuit 9 drives and controls an azimuth adjustment motor 10 that changes the azimuth of the reproducing head.

The motor drive circuit 9 includes an operational amplifier 17, transistors Tr ₅ , Tr ₆ , resistors R ₈ , R ₉ , etc., and is connected to the (-) input terminal of the operational amplifier 17 whose (+) input terminal is connected to the reference power supply +Vb. is input with the output of the second integrating circuit.

The voltage level of the power supply ±Vcc to which the collectors of the transistors Tr ₅ and Tr ₆ are connected is set equal to the level Va of the high-level signal output from the above-mentioned D-type flip-flop circuit FF ₁ , and the voltage levels Va and Vb are The relationship is set as Va=2Vb.
Furthermore, by setting the resistance values of resistors R ₈ and R ₉ to be equal, the output level of the motor drive circuit is proportional to the level difference between the output level of the second integrating circuit and the reference power supply Vb, and is in reverse phase. It becomes the output level, and becomes 0 level when the analog switches SW ₁ and SW ₂ are open.

Figure 2 shows an example of the azimuth adjustment mechanism, with motor 1
0 rotates, the pulley 11 is rotated via the belt 11a.
b, the gear 11c rotates, and the lever 11d, one end of which meshes with the gear 11c, rotates about the pivot 11e and moves the wedge 11g via the link 11f. As a result, the reproducing head 1 rotates around the fulcrum P, and its azimuth changes. Note that the azimuth is configured to maintain its position when no driving voltage is applied to the motor 10.

The operation of the above configuration will be explained with reference to the timing chart shown in FIG.

At time _t1 , a level signal _s1 proportional to the reproduced signal level is output from a D-type flip-flop circuit (hereinafter referred to as
Threshold of reset terminal _R2 of FF ₂ (referred to as DFF circuit)
When the state is below Vr, the output terminal of this FF ₂
Q ₂ and inverted output terminal ₂ are each at high level “H”
state, and is in the low level “L” state.
Therefore, when the DFF circuit _FF1 is in the reset state,
The output terminal Q ₁ and the inverted output terminal ₁ are in the "L" and "H" states, respectively, and the output terminal of the NOR circuit NOR is in the "H" state. Therefore, the level of the level signal _s2 at the output point _O1 of the comparison circuit 8 is at the level of the reference power supply Vb.

On the other hand, since the transistor Tr ₁ is in the closed state at this time, the output signal s ₃ of the NAND circuit N is in the "H" state, and the capacitor C ₂ is thereby grounded via the resistor R ₄ with a large resistance value. The state has become
The integral characteristic of this detection sensitivity switching circuit 13 is approximately resistance.
It has a relatively small time constant τ ₁ set by R ₅ and capacitor C ₃ . In addition, this detection sensitivity switching circuit 13
The output signal _s4 of is asymptotic to the level of the reference power supply Vb. Therefore, since it is within the range of the dead zone level Vb±1.2V determined by the dead zone setting circuit 15, this output signal _s5 maintains the "L" state, and each analog switch _SW1 , _SW2 of the switch circuit 16
is in an open state. At this time, the motor drive signal _s6 of the motor drive circuit 9 is 0V as described above, and the azimuth state of the head does not change.

At time _t2 , the level signal _s1 , which has increased as the reproduced signal level increases, exceeds the threshold Vr, and the DFF
The circuit FF ₂ is in the reset state and each output terminal Q ₂ ,
_Q2 is inverted to "L" and "H" states, respectively.
Therefore, the DFF circuit _FF1 of the phase comparator circuit 8 is released from the reset state and enters the operating state, and the output terminals are adjusted according to the azimuth state of the head as described above.
The output status of Q ₁ and ₁ changes.

Also, at this time, the other input terminal of the NOR circuit NOR is in the "H" state, so this NOR circuit NOR
Each output state of the DFF circuit FF ₁ changes in phase.

Therefore, when the level signal s ₁ exceeds the threshold Vr,
While the phase of the reproduced signal Sa is ahead of the reproduced signal Sa + Sb, the level signal s ₂ at the output point O ₁ is at a high level Va
Therefore, while the phase of the reproduced signal Sa lags behind the reproduced signal Sa+Sb, the level signal s ₂ at the output point O ₁ is at a low level of 0V. At time t ₂ , the azimuth is in a positive direction shift state where the phase of the reproduced signal Sa is ahead of the reproduced signal Sa + Sb, so at this point the output point O ₁
The level signal _s2 becomes the high level Va. Also, the time constant circuit 14 starts discharging from this point, and T ₁
After a second, the output signal _s3 of the NAND circuit N is brought to the "L" state. The first integrating circuit consisting of resistor R ₅ and capacitor C ₃ starts charging from this point, but since its time constant τ ₁ is relatively small, its output signal s ₄ quickly asymptotes to the high level Va. This output signal
When _s4 exceeds the dead zone upper limit level, the output signal _s5 of the dead zone setting circuit 15 becomes "H" and closes the analog switches _SW1 and _SW2, respectively. Therefore, the motor drive signal s ₆ has a voltage waveform obtained by integrating the level signal s ₂ by the second integrating circuit, but has a voltage waveform that is in opposite phase to this and changes around 0V. The motor 10 is driven by this motor drive signal _s6 , and rotates in a direction in which the positive deviation of the head azimuth decreases. Along with this rotation,
Eventually, at time _t3 , the azimuth changes to a state in which the phase of the reproduced signal Sa lags behind the reproduced signal Sa+Sb, and the level signal _s2 at the output point O becomes
It becomes 0V level. Therefore, the first integrator circuit starts discharging from this point, and the output signal s ₄ quickly becomes
Asymptotic to 0V. During this time, the dead zone is passed through, so the output signal _s5 of the dead zone setting circuit 15
is temporarily in the “L” state and the analog switch
SW ₁ and SW ₂ are brought into the open state, but they are brought into the "H" state again to bring them into the closed state. Along with the inversion of the level signal s ₂ at time t ₃ , the motor drive signal s ₆
The level of gradually increases until it becomes a positive voltage and the head azimuth rotates in a direction in which the negative deviation state decreases. Thereafter, as such state reversal is repeated and the proper azimuth state is approached, the reversal period of the positive direction deviation state and the negative direction deviation state becomes shorter and the average time of each state becomes closer, so that the output signal s ₄
The range of change in Vb converges within the range of the dead zone level Vb±1.2V determined by the dead zone setting circuit 15. At this point, the azimuth of the head is in a proper azimuth state, the output signal _s5 of the dead zone setting circuit 15 goes to the "L" state, the analog switches _SW1 and _SW2 are opened, and the motor drive signal _s6
is set to 0V. The time when T ₁ seconds have passed further from time t ₂
At t ₄ , the output signal s ₃ of the NAND circuit N becomes “L”
state, that is, 0V, and capacitors C ₂ and C ₃ are equivalently connected in parallel.

Therefore, by setting the time constant τ ₂ determined by the resistor R ₅ and capacitors C ₂ and C ₃ to be sufficiently larger than the time constant τ ₁ , the level change of the output signal s ₅ after this point will be slowed down, making it difficult to detect. Decrease sensitivity.

This is effective in preventing unnecessary azimuth adjustment when an exceptional phase shift occurs due to tape bending or the like even though the head is in a proper azimuth state. That is, suppose that such an exceptional phase shift occurs at time _t5 , and the level signal _s2 remains at the 0V level for a predetermined period of time. At this time, the first integrating circuit with a time constant τ ₂ including the capacitor C ₂ starts discharging, but since the rate of decrease in the level of its output signal s ₄ is slow, while this phase shift occurs, the output The level of signal _s4 remains within the set dead zone. Therefore, the motor drive signal _s6 remains at 0V and unnecessary azimuth adjustment is prevented.

Next, at time t ₆ when the recording tape reaches a non-recorded part such as between songs, the level of the level signal s ₁ becomes lower than the threshold value Vr, and each output terminal Q ₁ , ₁ of the DFF circuit FF ₁ becomes as follows.
Return to “L” and “H” states, and the NOR circuit again.
The output terminal of NOR is set to "H", and the level signal _s2 at the output point O becomes the level of the reference power supply Vb.

On the other hand, the time constant circuit 14 starts charging from time _t6 , and after a relatively short period of _T2 seconds, sets the output signal _s3 of the NAND circuit N to the "H" state again and sets the time constant of the first integrating circuit. Increase detection sensitivity as τ ₁ . However, since the level signal _s2 is at the level of the reference power supply Vb, its output signal _s4 also maintains the level of Vb.

The next song is played and along with this the level signal s ₁
Assuming that the azimuth is in a negative direction shift state where the phase of the reproduced signal Sa lags behind the reproduced signal Sa+Sb at time _t8 when the signal exceeds the threshold value Vr again, the level signal _s2 at the output point O becomes It becomes 0V. Therefore, the first integrating circuit starts discharging with the time constant τ ₁ and its output signal s ₄ quickly approaches 0V.
Accordingly, the output signal _s5 of the dead zone setting circuit 15 becomes "H" state, and _SW1 and _SW2 are closed again. Therefore, the motor drive signal s ₆ becomes a positive voltage, and the motor 10 driven by the motor drive signal s ₆ rotates in a direction in which the head azimuth deviation in the negative direction decreases.

At time _t3 , the head azimuth shifts in the positive direction, but since the circuit operation thereafter is the same as the operation between time _t3 and _t4 described above, a description thereof will be omitted.

As explained above, according to the apparatus according to the embodiment of the present invention, the playback head can be adjusted by detecting the lead or lag in the phase of one of the playback signals obtained by dividing and playing back different areas of the same recording track with respect to the other. The azimuth can be automatically adjusted.

Furthermore, once the azimuth is adjusted to an appropriate position, the detection sensitivity is reduced, and unnecessary adjustments based on phase difference detection due to external factors such as tape bending can be prevented. Furthermore, if there is a low-level reproduction signal state such as between songs, the detection sensitivity is set high again, and regular azimuth adjustment is performed from the recording section at the beginning of the subsequently played song.

In addition, FIG. 3 shows another embodiment of the phase comparator circuit, in which FF ₃ is connected to its data terminal D ₃ and clock terminal CL _{3 .}
It is a D-type flip-flop circuit to which a phase comparison signal is input, respectively, and each output from its output terminal Q ₃ and inverted output terminal ₃ is connected to a NAND circuit together with both phase comparison signals and the inverted output of FF ₂ of the level detection circuit 12. Input to N ₁ and N ₂ , NAND circuit N ₁
The output of is through the inverter, diode _D8 ,
Further, the output of the NAND circuit _N2 is outputted to the output point _O3 via the diode _D9 .

According to the above configuration, this output point _O3 becomes high level because the phase of the reproduced signal Sa is the reproduced signal Sa+
This occurs only when the phase comparison signal input to the data terminal D ₃ and the clock terminal CL ₃ are both in the “H” state, and the output point O ₃ is at a low level when the reproduction signal Sa phase is the reproduced signal
This occurs only when the signal is delayed from Sa+Sb and the phase comparison signals input to the data terminal _D3 and the clock terminal _CL3 are both in the "H" state. At other times, the level of the output point _O3 is the level of the reference power supply Vb, which is set to an intermediate level between the high level and the low level.
Therefore, it changes between three levels.

However, output terminal ₂ of flip-flop circuit FF ₂
When the output of is low level, NAND circuit N ₁ , N ₂
Each output becomes high level, and during this time the level of the output point _O3 is forcibly maintained at the reference power supply Vb, making the series of operations described above possible.

In the above embodiment, the azimuth is configured to maintain its position when the drive voltage of the motor 10 is not applied. Therefore, when maintaining a certain azimuth position constant, the voltage applied to the motor must be set to 0V. However, the present invention is not limited to this. For example, if a detector is provided to detect the azimuth position of the head, and the detection signal follows the input control signal. Various aspects can be considered, such as configuring the control signal level to be kept constant.

As described above, according to the present invention, since the azimuth adjustment operation is stopped when the azimuth error is within the allowable range, it is possible to eliminate auditory discomfort such as sound fluctuation caused by the azimuth adjustment operation during signal reproduction. be able to.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a circuit configuration of one embodiment of the present invention, FIG. 2 is a diagram showing an example of an azimuth adjustment mechanism used in the present invention, and FIG. 3 is a circuit diagram showing another embodiment of the phase comparator circuit. 4 is a timing chart for explaining the present invention, and FIG. 5 is a configuration diagram showing an example of a reproducing head and a waveform diagram of a reproduced signal for explaining the present invention. 1... Reproduction head, 2, 3... Amplifier, 4, 5
... Bandwidth filter, 6, 7 ... Waveform conversion circuit, 8
... Phase comparison circuit, 9 ... Motor drive circuit, 10
... Motor, 12 ... Level detection circuit, 13 ...
Detection sensitivity switching circuit, 14... Time constant circuit, 15...
...Dead zone setting circuit.

Claims (1)

[Scope of Claims] 1. A playback head that divides and reproduces the same recording track of a recording tape in the width direction of the recording track, and a signal in a predetermined frequency range of two divided playback signals obtained by this divided playback, respectively. ”
means for forming first and second phase comparison signals whose waveforms are shaped into binary signals consisting of respective level states of "L" and "L"; and means for comparing the phases of the first and second phase comparison signals, a phase comparing means for outputting an inverted signal that is inverted as much as possible into "H" and "L" level states in response to each state of phase lead and lag with respect to the other;
and azimuth adjustment means for changing the azimuth of the reproducing head in a direction in which the phases of the second phase comparison signal match, and monitoring the integral signal of the inverted signal to determine whether the level of the integral signal is within a set range. dead zone setting means for determining a determination signal and outputting a determination signal indicating the determination result; and inputting the determination signal while the level of the integral signal is within the set range;
An automatic azimuth adjustment device for a reproducing head, comprising: azimuth state holding means for maintaining the azimuth state of the reproducing head constant. 2. The dead zone setting means includes a reproduced signal level detection circuit, a time constant circuit, and a sensitivity switching circuit,
setting the setting range for the level of the integral signal to be relatively narrow for a predetermined period of time from the time when the level of the divided reproduction signal reaches a predetermined level or higher;
2. The automatic azimuth adjustment device for a reproducing head according to claim 1, wherein the setting range for the level of the integral signal is set relatively wide after the predetermined time.