JPS6364909B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high voltage MOSFET (metal oxide semiconductor field effect transistor).

As shown in FIG. 1, a high-output MOSFET has, for example, N ⁺ -type source and drain regions 2 and 3 formed by high-concentration donor impurity diffusion on one main surface of a P ^- type Si (silicon) substrate 1. A gate electrode 5 is formed on the substrate between them via a thin SiO ₂ film 4,
An N ^- type high breakdown voltage layer 6 is formed on the substrate surface between the gate and the drain, a thick insulating film 7 is formed on the gate and the high breakdown voltage layer, and an Al electrode 8 is formed in ohmic contact with the source region 2. A structure has been developed in which a part of the field plate 9 extends beyond the gate 5 and onto the insulating film 7 on the high breakdown voltage layer.

When setting the withstand voltage to about 400V in such a high-output MOSFET, the impurity concentration Nsub of the substrate wafer used is about 3×10 ¹⁴ atoms/cm ³ , but when applying voltage to the drain, the drain junction The depletion layer dl largely extends from the substrate toward the substrate. As a result, the electric field strength at point C on the substrate surface under the gate edge becomes stronger, causing a so-called weak avalanche WA as shown in Figure 2, deteriorating the output characteristics and further causing a switchback (or negative Permanent destruction may occur due to the phenomenon of (resistance). Note that in the figure, a broken line N indicates the operation in a normal case.

As a countermeasure to the above problem, if the impurity concentration of the entire semiconductor substrate is increased, the electric field strength particularly near the drain junction increases, resulting in a decrease in breakdown voltage.

The present invention was made to eliminate the above-mentioned problems, and its purpose is to provide good output characteristics and
The goal is to provide high-voltage MOSFETs.

FIG. 3 shows an embodiment in which the present invention is applied to an N-channel MOSFET.

As shown in the figure, in the present invention, in order to suppress the electric field strength at the gate end B, ^P P of the mold substrate 1a
The impurity concentration (Nsub _G ) is set higher than the P impurity concentration (Nsub _D ) of the P ^- type substrate 1b near the drain junction. By having such a structure,
The slightly higher impurity concentration of the Si substrate under the gate edge prevents the electric field strength from increasing in that area, while the lower impurity concentration of the substrate near the drain junction allows a high breakdown voltage to be maintained.

4a to 4e show each step of an embodiment of the manufacturing process of a power N-channel MOSFET according to the present invention.

(a) Low impurity concentration (Nsub _D : ~1~3×
10 ¹⁴ atoms/cm ³ ) P ^- type Si substrate 1b is prepared,
By selectively implanting acceptor impurity ions, P ^- well 1a (impurity concentration Nsub _G : 3 to 10×
10 ¹⁴ atoms/cm ³ ).

(b) An N ^- type well 3a is formed in the drain region by selective donor impurity ion implantation. After this, the SiO ₂ mask for selective diffusion is removed, and a thin SiO ₂ film 4 (about 1300 Å thick) for the gate is deposited on the entire surface.
form.

(c) A poly-Si layer is formed by depositing Si in a vapor phase, and the gate electrode 5 is formed by patterning and etching this poly-Si layer. Using this gate electrode 5 as a mask, a high breakdown voltage layer (offset gate, N: 1.5×10 ¹² atoms/cm ³ ) 6 is formed in a self-aligned manner by implanting donor impurity (for example, As) ions.

(d) Thick insulating film, such as CVD/SiO ₂ film 7
After forming to a thickness of about 0.5 to 0.7 μm and patterning and etching the source and drain parts, a high concentration donor impurity such as P (phosphorus) is deposited and diffused to form an N ⁺ source region 2 and an N ⁺ drain region (contact part) 3. form. Thereafter, if necessary, a thick insulating film, for example, a phosphorus silicate glass film 7 of about 1.2 μm is formed as a surface stabilizing film.

(e) After performing contact photoetching of the source and drain parts, unnecessary parts of Al are etched by Al vapor deposition and photoresist processing to make ohmic contact with the source and drain parts respectively.
Electrodes 8 and 10 are formed. A part of the source electrode 8 of this Al electrode is used as a field plate 9 and is terminated on the insulating film of the offset gate beyond the gate. The terminal end B of this field plate forms the boundary A between the P ^- type well 1a formed on the substrate surface and the part 1b where no well is formed.
A P ^- type well is formed in advance so that it is closer to the P - type well 1a than the P ^- type well 1a.

Figure 5 is for power as described in the above example.
The relationship between breakdown voltage and on-resistance in a MOSFET and a power MOSFET using a uniform impurity concentration substrate is shown. The withstand voltage (V _DSS ) conditions are I _S = 10 μA, V _GF
= 0V, and the on-resistance (R _ON ) condition is I ₀ =
3A, V _GS = 15V. The circle in the figure indicates the case of the present invention, that is, the P ^- type substrate (N: 1.8 × 10 ¹² atoms/
cm ³ ) into a part of the P ^- well (N: 3~10×
10 ¹² atoms/cm ³ ), the on-resistance can be set to about 1.8Ω at a withstand voltage of 420 to 430V. On the other hand, the △ and × marks in the same figure are the conventional type, that is, when the impurity concentration of the P ^- type substrate is uniform, and the △ mark is the concentration N: 17 × 10 ¹² atoms/
cm ³ , x marks are for the case where the concentration N is 2.3×10 ¹² atoms/cm ³ . In the former case, the withstand voltage is 400-430V and the on-resistance is
The latter is as high as 3.0Ω, and the on-resistance is between 2 and 2.5Ω at a withstand voltage of 400 to 450V, but it causes a so-called switchback phenomenon in which it has a negative resistance in the on state.

As described above, according to the present invention, it is possible to obtain a MOSFET that operates with low resistance, has good output characteristics and does not switch back, and can be used with high voltage resistance, thereby making it possible to expand the ASO (safe saturation area). .

The present invention is not limited to the above-mentioned embodiments, but includes other modifications.

[Brief explanation of drawings]

Fig. 1 is a sectional view of a conventional MOSFET, Fig. 2 is a MOSFET output characteristic curve diagram, Fig. 3 is a sectional view showing the principle structure of a MOSFET according to the present invention, and Fig. 4 a to e are indicative of the present invention. Figure 5 is a process cross-sectional diagram showing the MOSFET manufacturing process by
FIG. 2 is a diagram showing the relationship between breakdown voltage and on-resistance in a MOSFET. 1...P ^- substrate, 2, 3...N ⁺ source, drain, 4... gate insulating film, 5... gate, 6...
High breakdown voltage layer, 7... Insulating film, 8... Source electrode,
9...Field plate, 10...Drain electrode.

Claims (1)

[Claims] 1 A first region as a source region of a second conductivity type and a second region as a drain region are formed at positions spaced apart from each other within one main surface of a first conductivity type high resistance semiconductor substrate, and a second region as a low resistance source region of a second conductivity type and a second region as a drain region are formed. A gate electrode is formed on the surface of the substrate via an insulating film, and is connected to the second region within the surface of the substrate region between the substrate region under the gate electrode and the second region, and is connected to the second region. A second conductivity type high breakdown voltage layer with a low impurity concentration is formed, and a part of the source electrode resistance-connected to the first region extends beyond the substrate region under the gate electrode onto the insulating film on the high breakdown voltage layer. In a MOS semiconductor device, a portion of the substrate region under the gate electrode, a portion of the substrate region under the end of the source electrode extending on the high voltage layer, and a portion under the high voltage layer. 1. A MOS semiconductor device characterized in that the impurity concentration of the substrate region portion is higher than the impurity concentration of the substrate region near the junction with the second region.