JPS6365913B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time signal detection device, and particularly aims to provide a time signal detection device that can accurately detect a time signal without adjusting the characteristics of a filter or the like. It is.

<Background of the Invention> A clock with an automatic correction function corrects the time using a radio broadcast time signal. Generally in Japan
The time signal used by NHK No. 1 or No. 2 is detected, and the time display on the clock is corrected based on the detected signal.

As shown in Figure 1, the time signal used by NHK is a 440Hz forecast signal that is sent three times for 0.1 seconds at 1 second intervals, followed by an 880Hz forecast signal that continues for 1 second and continues for 2 seconds after 1 second. The signal gradually attenuates.

<Prior Art> Conventionally, a forecast signal and a correct report signal are detected by a filter, and an automatic correction operation is executed based on the detected signals. When a filter is used in this manner, it is necessary to adjust the characteristics of the filter so that it becomes a band filter with center frequencies of 440 Hz and 880 Hz, which has the disadvantage that manufacturing takes time.

Furthermore, if a filter is used to detect forecasts and correct reports at 440 Hz and 880 Hz, there is a time delay in the detection, and this time delay also has the disadvantage that accurate time adjustment cannot be performed. This delay time becomes particularly large when a mechanical filter is used to eliminate adjustment.

In order to wipe out these shortcomings, for example,
A detection method that does not use a filter is being considered, as proposed in Publication No. -44153. Special Public Service 1987
The time signal detection device proposed in Publication No. 44153 detects a no-signal period before the time signal, and a predetermined time interval between the forecast signal and true news signal sent from the end of the no-signal period. A method is used to determine whether or not there is a time signal and detect the time signal.

<Disadvantages of the Conventional Device> The time signal detection device proposed in this publication detects a no-signal period provided before the start of a time signal, and detects a time signal based on the detection of this no-signal period.
However, even if radio broadcasting becomes silent, external noise still exists, and it is difficult to ensure that there is no signal. Therefore, when this method is adopted, malfunctions occur due to noise, and it is difficult to detect the time signal reliably. In addition, if the time signal detection device is constructed using an analog circuit and is attached to a clock or the like that is installed outdoors under severe weather conditions, its characteristics will change over time, making it difficult to operate normally over a long period of time. That is difficult.

<Object of the Invention> The present invention aims to provide a time signal detection device that can reliably detect a time signal without using a filter.

<Summary of the Invention> In the present invention, a forecast signal and a true report signal are detected by measuring their cycles using a cycle measuring means, and the forecast signal and true report signal detected by the cycle measuring means continue for a predetermined period of time. It is constructed so that all arrivals are measured by digital circuits and time signal signals are detected.

<Embodiment of the Invention> FIG. 2 shows an embodiment of the invention. In FIG. 2, 1 indicates a radio receiver. In this example, the local oscillator 2 is constituted by a voltage controlled oscillator, and this voltage controlled oscillator, a crystal oscillator 3,
A phase comparator 4, a variable frequency divider 5, a low frequency filter 6, and an amplifier 7 constitute a phase lock loop,
By setting the frequency division ratio of the variable frequency divider 5 using the setting device 8, the local oscillator 2 can be oscillated at an arbitrary frequency, and a single crystal oscillator 3 can receive broadcast waves at an arbitrary frequency. The following shows a configuration that allows this. Therefore, no matter which region the self-correcting clock is installed in, it can receive the NHK 1st or 2nd broadcast broadcast in that region. Reference numeral 9 denotes a reception tuning circuit, in which a variable capacitance diode is used, and a control voltage to be supplied to the local oscillator 2 is applied to the variable capacitance diode to define the reception frequency. 11
indicates the output terminal of the radio receiver, and it is assumed that the detected low frequency signal is output to this output terminal.

Reference numeral 12 indicates a time signal detection device according to the present invention. The time signal detection device 12 according to the present invention includes a waveform shaping circuit 13 that shapes the output signal of the radio receiver 1 into a rectangular wave, and synchronized with the rising or falling timing of the rectangular wave output from the waveform shaping circuit 13. It is composed of a digital differentiating circuit 14 for extracting pulse signals and a counter, and this counter is reset periodically at time intervals corresponding to the period of the input signal by the output of the digital differentiating circuit, and the clock pulse is output within the period of this reset period. a period measuring means 15 that measures the period of the input signal depending on whether the count value reaches a predetermined value and detects a forecast signal and a true report signal having a preset period; and a measurement result of the period measuring means 15. It is composed of a delay timer 16 that removes the influence of noise from the signal, and a counter, and this counter starts counting clock pulses every time the forecast signal and the correct report signal rise, and checks whether the counted value reaches a predetermined value or not. It consists of a pulse width measuring means 17 which determines whether the forecast signal and true report signal have continued for a predetermined time by looking at the clock pulse width, and a counter, which counts clock pulses every time the forecast signal falls. pulse interval measuring means 18, which determines whether the forecast signal has arrived at a predetermined time interval by checking whether the counted value reaches a predetermined value, and pulse width measuring means, which count the judgment outputs of the pulse width measuring means. , a forecast counter 19 that outputs a time signal detection signal by detecting that a forecast signal has arrived a predetermined number of times and that a true news signal has continued for a predetermined period of time following the forecast signal, and when the forecast signal has arrived a predetermined number of times. Switching signal generating means 21 that outputs a signal for switching the period measuring means 15 to the measurement state of the correct signal.
When a switching signal is output from the switching signal generating means 21, a switching circuit 22 switches the frequency of the clock pulse supplied to the period measuring means 15, a pulse width measuring means 17 and a pulse interval measuring means 18 each output a pulse width. If the pulse interval is longer or shorter than the regular time, and when the forecast counter 19 has counted the arrival of the signal a predetermined number of times, a termination signal is output and the forecast counter 19 and the switching signal generating means 21 are reset. A clock counter 24 provides a clock pulse to a differentiating circuit 14, a period measuring means 15, a delay timer 16, a pulse width measuring means 17, and a pulse interval measuring means 18.

The clock counter 24 takes in a clock signal with a stable frequency from the crystal oscillator 3 provided in the radio receiver 1, and outputs it to the output terminal _Q1 , for example, 288KHz, and to the output terminal _Q2.
72KHz, 36KHz on Q ₃ , 1125KHz on Q ₄ , 281.25 on Q ₅
Hz, outputs a 140.625Hz clock pulse to _Q6 .

FIG. 3 shows the specific circuit structure of each part. Second
Portions corresponding to those in the figure are designated by the same reference numerals. The operation will be explained below with reference to FIGS. 2 and 3.

As shown in FIG. 3, the waveform shaping circuit 13 is composed of a saturation amplifier 13a and a Schmitt trigger circuit 13b, and the detected output of the radio receiver 1 is saturated and amplified and supplied to the Schmitt trigger circuit 13b, thereby producing a constant amplitude signal. The waveform is shaped into a square wave. Therefore, the constant frequency forecast signal and true report signal are rectangular waves with a duty ratio of 50% as shown in Figure 4A.
The waveform is shaped to Pa. Although normal broadcast content is also supplied to the waveform shaping circuit 13, here, to simplify the explanation, a case will be described in which a forecast signal and a regular report signal are input. By understanding the operation of detecting the arrival of forecast signals and true news signals, it should be understood that malfunctions do not occur due to normal broadcast content.

The forecast signal whose waveform has been shaped into a rectangular wave Pa by the waveform shaping circuit 13 is supplied to the differentiating circuit 14 .
The differentiating circuit 14 can be constructed of a counter 14a and an AND gate 14b, for example, as shown in FIG. The rectangular wave Pa output from the waveform shaping circuit 13 is sent to the counter 1 forming the differentiating circuit 14.
4a to the reset terminal R. Also counter 1
The polarity of the output terminal _Q2 of 4a is inverted and applied to the input terminal _φ1 , and a 288KHz clock pulse is applied to the enable terminal EN.

The counter 14a performs a counting operation when L logic is applied to the reset terminal R, and is reset when H logic is applied. Therefore, the counter 14a is a square wave.
Counting starts in synchronization with the falling of Pa. The counter 14a counts 288KHz clock pulses, and when the count increments by two, the output terminal _Q2 becomes H logic, and this H logic signal is inverted in polarity and given to the input terminal _φ1 .
a stops the counting operation. Due to this operation, a pulse having the same pulse width τ ₁ as one cycle of the 288KHz clock pulse Pb supplied immediately after the falling edge of the rectangular wave Pa is output from the output terminal Q ₁ of the counter 14a.
Only one Pc is taken out every falling edge of the rectangular wave Pa.
This pulse Pc is supplied to the AND gate 14b and is ANDed with the clock pulse Pb. Therefore, only one pulse Pd, which is the same as the clock pulse Pb, is obtained from the AND gate 14b, as shown in FIG. 4D. In this way, the pulse Pd with a narrow pulse width is obtained from the differentiating circuit 14 in synchronization with the fall of the rectangular wave Pa. The period T of this pulse Pd matches the period of the forecast signal.

The differential pulse Pd obtained by the differentiating circuit 14 is supplied to the period measuring means 15, and its period T is measured. The period measuring means 15 includes a counter 15a,
It can be constructed by AND gates 15b and 15c and a D-type flip-flop 15d.

The differential pulse Pd is applied to the reset terminal R of the counter 15a. A clock pulse of, for example, 36 KHz is applied from the switching circuit 22 to the enable terminal EN of the counter 15a. Therefore, the counter 15a starts counting 36KHz clocks immediately after the differential pulse Pd is supplied. AND gate 15b receives outputs from output terminals Q ₅ and Q ₇ of counter 15a and detects that both have become H logic.

The timing at which both output terminals Q ₅ and Q ₇ become H logic is from the time when 80 clock pulses of 36 KHz are supplied until the time when 36 clock pulses of 36 KHz are supplied. Converting this to time, it is the time from 2.222 milliseconds after the start of counting until 2.666 milliseconds have passed.
That is, when a signal of 375 Hz to 450 Hz is input, the AND gate 15b outputs H logic. The output of the AND gate 15b is a D-type flip-flop 15d.
is applied to the data input terminal D of. The clock input terminal φ of the D-type flip-flop 15d is connected to the output terminal _Q1 of the counter 14a that constitutes the differentiating circuit 14.
gives the output signal of

Therefore, after the D-type flip-flop 15d reads the output of the AND gate 15b, the counter 15a
is reset. As a result, the input signal is 375Hz~
When the frequency is between 450 Hz, the output terminal Q of the D-type flip-flop 15d outputs H logic.

AND gate 15c has counter 15a at 36KHz
When 90 clock pulses are counted, H logic is output. In other words, when 2.5 milliseconds or more elapse, the AND gate 15c outputs H logic. The frequency of a signal that lasts more than 2.5 milliseconds is 400Hz. Therefore, when the input signal has a frequency lower than 400 Hz, AND gate 15c outputs an H logic and resets D-type flip-flop 15d.

In this way, the output terminal Q of the D-type flip-flop 15d outputs H logic while a signal of 400 to 450 Hz is input. The output signal is shown in FIG. 5B with reference symbol Pe. In addition, when detecting a correct report signal, the switching circuit 22 selects a 72KHz clock pulse and supplies the 72KHz clock pulse to the counter 15a, so the input signal is 800 to 900.
When the frequency is within the Hz range, the D-type flip-flop 15d outputs H logic, and the input of the 880 Hz correct signal can be detected.

The output of the D-type flip-flop 15d is applied to a delay timer 16 which eliminates the effects of noise. The delay timer 16 has two counters 16a and 1
6b. The counter 16a generates an output after confirming that this state has continued for a predetermined period of time from the moment when the output of the D-type flip-flop 15d rises to H logic. The configuration is such that no signal is transmitted to the pulse width measuring means 17 and the pulse interval measuring means 18 provided in the stage.

That is, the output of the D-type flip-flop 15d is applied to the reset terminal R of the counter 16b. The counter 16b inverts the polarity of the output from the output terminal _Q3 and supplies it to the input terminal _φ1 . Furthermore, the enable terminal EN
For example, a clock pulse of 1125 Hz is applied from the clock counter 23 to the clock pulse.

The output of the output terminal _Q3 of the counter 16b is applied to the reset terminal R of the other counter 16a, and the output of the output terminal _Q8 of the counter 16a is applied to the input terminal _φ2 with its polarity inverted. 281.5Hz from the clock counter 23 to the enable terminal EN of the counter 16a.
gives a clock pulse of The output of the output terminal _Q8 of the counter 16a is applied to the reset terminal R of the counter 17a constituting the pulse width detecting means 17, and also to the reset terminal R of the counter 18a constituting the pulse interval measuring means 18.

With this configuration, the counter 16b normally performs a counting operation when the output of the D-type flip-flop 15d is in the L logic state. At this time, when a certain number of clocks, for example 7, are input to the enable terminal EN of the counter 16b, the output terminal _Q3 becomes H logic, and this H logic signal is inverted in polarity and given to the input terminal _φ1 , so that counting is performed. The operation stops in that state.

Since the output terminal _Q3 outputs H logic, H logic is applied to the reset terminal R of the counter 16a, and the counter 16a also stops operating and is reset. After all, from the output terminal _Q8 of the counter 16a,
As shown in , a pulse Pf with a slightly delayed phase is obtained from the signal Pe.

When the D-type flip-flop 15d detects the second forecast signal and outputs H logic to the output terminal Q, the counter 16b is reset. As a result of this reset, the output terminal _Q3 becomes L logic, so that the counter 16a starts operating. The counter 16a is
When 15 clocks of 281.25Hz are counted, output terminal _Q8
becomes H logic, and the polarity of this is inverted and applied to the input terminal φ ₂ , so the counter 16a stops in that state. At this time, the output of the output terminal _Q8 is supplied to the reset terminal R of the counter 17a constituting the pulse width measuring means 17 through the inverter 17b, so that the counter 17a starts counting operation. This counting operation determines whether the forecast signal has been present for 0.1 seconds. When the forecast signal exists for 0.1 seconds, the output terminal _Q7 of the counter 17a rises to H logic. This rising edge is given to the forecast counter 19a, and the forecast counter 19a increments the count value by one. When a forecast signal with a pulse width of 0.1 seconds is input three times in a row, the output terminal of the forecast counter 19a
_Q3 rises to H logic and outputs H to switching signal generation means 21.
Gives a logical signal. By supplying this H logic signal, the switching signal generating means 21 reads the H logic at timing _T3 of the signal Pi shown in FIG.
Then, a 72 KHz clock is applied to the period detection means 15 to switch to the detection state of the correct report signal.

The operations of the switching signal generating means 21 and the pulse interval measuring means 18 will now be explained. In the pulse interval measuring means 18, 18e represents an RS flip-flop. This R-S flip-flop 18e
A pulse is outputted to the set terminal S of the controller through the NAND gate 18b at a timing slightly shorter than the interval (1 second) of the forecast signal, and the RS flip-flop 18e is set at the timing immediately before the second and subsequent forecast signals. Pulse Ph shown in Figure 5E
is a pulse output from the NAND gate 18b. A NAND gate 1 provided in the delay timer 16 is connected to the reset terminal R of the R-S flip-flop 18e.
A reset pulse is given from 6c. This reset pulse is shown in FIG. 5D with the symbol Pg.

In other words, this reset pulse Pg is
6b counts up and is output at the moment when the counter 16a is reset, and this reset pulse
R-S in synchronization with the forecast signal falling due to Pg
The flip-flop 18e is being reset. The reset R-S flip-flop 18e receives the set pulse output from the NAND gate 18b.
It is set by Ph just before the next forecast signal rises. Therefore, the R-S flip-flop 18e outputs a rectangular wave Pi as shown in FIG. 5F,
At the timing of the rising edge, the switching signal generating means 21
reads the state of terminal _Q3 of the forecast counter 19a.

When the forecast signal is input three times, the output terminal _Q3 of the forecast counter 19a outputs H logic, so the state of the switching signal generating means 21 changes as shown in FIG. 5G at the timing immediately before the true report signal. The signal switching circuit 22 is switched.

By switching the signal switching circuit 22, the period measuring means 15 is switched to a state in which it detects the period of the 880 Hz regular report signal. When the regular news signal is continuously input for a regular time, the forecast counter 19a increments the state by one, outputs H logic to the output terminal _Q4 , turns on the output switch 25, and detects the time signal. Output what you have done externally.

<Explanation regarding malfunction prevention means> The explanation so far is about the operation when a regular forecast signal and correct report signal are input. 440Hz during broadcast
signal, 880Hz signal may exist. These signals must not cause malfunctions.

For this reason, various malfunction prevention circuits are provided. The delay timer 16 is one of them. That is, as explained above, the counter 16a recognizes the input only after the 440Hz signal continues for a predetermined period of time immediately after detecting the 440Hz signal, and issues an instruction to the counter 17a to measure the pulse width. At the same time, the counter 18a constituting the pulse interval measuring means 18 is reset to prepare for measuring the pulse interval.

Now assume that the forecast signal does not continue for a predetermined period of time and is input intermittently. In other words, counter 17a
If the 440Hz signal is interrupted and input again while counting, the output of the D-type flip-flop 15d of the period measuring means 15 temporarily goes to the L logic as shown as Pe' in FIG. 5H. Go down. Therefore, the counter 16b performs a counting operation while the pulse Pe' is at L logic, and when seven 1125 KHz clocks are counted, the output terminal _Q3 outputs H logic and resets the counter 16a. At this time, a reset pulse Pg' (FIG. 5I) is output from the NAND gate 16c, and this L logic pulse is output from the R-S flip-flop 18e.
It is applied to the reset terminal R of , and outputs H logic to the output terminal b. This H logic signal is passed to the NAND gate 1.
8d to one input terminal. nand gate 1
The output of the output terminal _Q7 of the counter 16a is applied to the other input terminal of the counter 8d. The counter 16a is reset in this state, but when the signal Pe' again rises to H logic, the counter 16b is reset and the counter 16a starts counting in its place. This counting operation causes output terminal _Q7 to go high.
When the logic is output, the NAND gate 18d outputs the L logic, and this L logic signal is given to one input terminal of the OR means 23, so the H logic is output to the output terminal of the OR means 23, and the counter 19a outputs the H logic.
and gives a reset signal to the switching signal generating means 21. In this way, when a signal with a frequency close to the forecast signal is intermittently input, a reset pulse is output from the OR means 23, the forecast counter 19a and the switching signal generating means 21 are reset, and malfunction can be prevented.

On the other hand, if the 440 Hz signal is input for a longer time than the regular pulse of the forecast signal, the output terminal _Q8 of the counter 17a outputs H logic. Since this H logic signal is applied to the OR means 23 as an L logic signal through the NAND gate 17c, the H logic signal is output from the OR means 23 in this case as well. Therefore, in this case as well, the forecast counter 19a and the switching signal generating means 21 are reset and malfunction can be prevented.

Furthermore, if the pulse interval of the 440 Hz signal is input at an interval shorter than the regular pulse interval of 1 second, the NAND gate 18b switches to the R-S flip-flop 18.
440Hz is input before the set signal is applied to e. As a result, the output terminal _Q7 of the counter 16a outputs H logic while the RS flip-flop 18e remains reset. Therefore, the NAND gate 18d outputs the L logic, and the NAND gate 18 supplies the L logic to the OR means 23. In response to this L logic signal, an H logic signal is output from the OR means 23, and the forecast counter 19a and the switching signal generation means 21 are reset.

Furthermore, if the pulse interval of the 440Hz signal is longer than the specified time (1 second), the pulse interval detection means 1
Since the NAND gate 18c forming part 8 outputs L logic and supplies L logic to the OR means 23, an H logic signal is output to the output terminal of the OR means 23, and this H logic signal causes the forecast counter 19a and the switching signal to be generated. The means 21 is reset and malfunction can be prevented.

<Effects of the Invention> As explained above, according to the present invention, the period measuring means 15 is
This period measuring means 15 measures 440Hz and
Distinguishes the frequency of the 880Hz forecast signal and true report signal,
Furthermore, since the duration and pulse interval are each measured and the signal is determined to be a time signal only when all of them meet the standards for a regular time signal, it will not malfunction due to a 440 Hz signal or an 880 Hz signal.

However, since the frequency is not discriminated by a filter, the time signal detection signal can be output with only a slight time delay from the rising edge of the regular signal, that is, a time delay until the counter 17a counts up. This delay time is, for example, about 85 milliseconds in the above embodiment, and does not cause a large error in correcting the time of the clock.

In addition, since all circuits can be configured with digital circuits, it is possible to obtain a product that does not require adjustment and can operate stably over a long period of time even under harsh environments. Therefore, it is possible to provide a time signal detection device that is easy to manufacture and highly reliable.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram for explaining the waveform of a time signal, FIG. 2 is a block diagram for explaining an embodiment of the present invention, and FIG. 3 is a detailed diagram showing each part of the block diagram shown in FIG. 2. 4 and 5 are waveform diagrams for explaining the operation of the time signal detection device according to the present invention. 1: Radio receiver, 12: Time signal detection device,
13: Waveform shaping circuit, 14: Differential circuit, 15: Period measuring means, 16: Delay timer, 17: Pulse width measuring means, 18: Pulse interval measuring means, 19: Forecast counter, 21: Switching signal generating means, 22: Signal switching circuit, 23: OR means.

Claims (1)

[Claims] 1. A waveform shaping circuit 13 that shapes a low frequency signal output from a radio receiver into a rectangular wave, and B. Timing of rising or falling of the rectangular wave output from this waveform shaping circuit 13. It is composed of a digital differentiator circuit 14 which takes out a pulse signal synchronized with a period measuring means 15 for measuring the period of the input signal depending on whether or not the count value of the clock pulse reaches a predetermined value within the period, and detecting a forecast signal and a true report signal having a preset period; The counter starts counting clock pulses every time the forecast signal and the correct report signal rise, and checks whether the counted value reaches a predetermined value and determines whether the forecast signal or the correct report signal is set to a predetermined value. pulse width measuring means 17 for determining whether or not the period of time has continued; a pulse interval measuring means 18 that determines whether the forecast signal has arrived at a predetermined time interval by checking whether the forecast signal has arrived at a predetermined time interval; that the number of times has arrived, and
a forecast counter 19 that detects that a true news signal continues for a predetermined period of time following a forecast signal and outputs a time signal detection signal; a switching signal generating means 21 that outputs a signal for switching the state; H a switching circuit 22 that switches the frequency of the clock pulse supplied to the period measuring means when the switching signal is output from the switching signal generating means 21; I a pulse width measuring means 17 and pulse interval measuring means 18 respectively, output a termination signal when the pulse width is long and the pulse interval is longer or shorter than the regular time, and when the forecast counter 19 counts the arrival of the signal a predetermined number of times. , an OR means 23 for resetting the forecast counter 19 and the switching signal generation means 21; A time signal detection device comprising: a counter 24;