JPS6365981B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Industrial Application Field The present invention is an evaluation tool created for developing a program to be stored in a built-in ROM or examining its operation when manufacturing a one-chip microcomputer. Regarding chips.

(b) Prior art In general, a one-chip microcomputer with a built-in ROM and RAM operates by itself according to a program stored in the ROM.
Programs are stored in the ROM using a mask when the one-chip microcomputer is manufactured. That is, when one-chip microcomputers are mass-produced, the same program is written into all of the mass-produced products. Therefore, programs cannot be easily rewritten or changed, and sufficient consideration is required when creating a program. Therefore, an evaluation chip was created that had the same functions as a mass-produced one-chip microcomputer, but whose operations were performed by commands given from the outside. Program development and examination were performed using this evaluation chip. be exposed.

On the other hand, some conventional one-chip microcomputers allow the user to select the circuit type of the input/output circuit. Specifically, it is possible to select whether the input circuit type is a normal inverter or a Schmitt inverter, and the output circuit type is open drain or with a pull-up resistor. input/input so that the circuit format is as follows.
The output circuit is switched using a mask. However, in evaluation chips compatible with one-chip microcomputers in which the circuit type of the input/output circuit can be selected, the type of the input/output circuit is usually fixed to one type. This happened in February 1980.
Page 10, No. 2, 2 of “Microcomputer Data Series No. 3LM6499 Manual” published by the applicant on the 15th
It is described in the section.

When developing and evaluating programs using such an evaluation chip, connect external circuits to the input or output terminals of the evaluation chip, and connect the circuits set to the input/output circuits of the one-chip microcomputer. If you do not match the format,
Accurate evaluation of programs is not possible. Therefore, as the number of terminals increases, the connection of external circuits becomes more complicated, making the evaluation chip difficult for users to use and posing a major obstacle to program development.

(c) Purpose of the Invention The present invention has been made in view of the above-mentioned points, and has the same circuit format as that which can be set in the input/output circuit of a one-chip microcomputer, and is capable of providing a program from the outside. By giving data specifying the circuit format in the same way as
The purpose of the present invention is to provide an evaluation chip in which the circuit format of the output circuit can be set.

(d) Structure of the Invention The present invention provides a chip for program evaluation of a one-chip microcomputer in which the input or output circuit type can be selected by a mask, and the chip can be set as the input or output of the one-chip microcomputer. an input circuit or an output circuit having a circuit format capable of configuring the input circuit, a plurality of circuit format designation data storage circuits that output a plurality of control signals for selecting the circuit format of the input circuit or output circuit, and the circuit format designation data storage circuit. A preset clock generation circuit is provided which sequentially outputs a plurality of preset clock signals, each controlling the memory operation of the program counter and setting a predetermined address in the program counter, based on an externally applied reset signal. By storing data specifying a circuit type at the predetermined address of the external storage circuit addressed by the program counter, when the reset signal is applied, the data is sequentially preset in the circuit type specifying data storage circuit and input. This is a configuration in which the circuit type of the circuit or output circuit is set.

(E) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. The evaluation chip 1 indicated by the broken line has input/output common terminals PA0 to PA7, PB0 to PB7, and PC, similar to a one-chip microcomputer for mass production.
The input/output circuits 2, 3, 4, and 5 provided in 0 to PC7 and PD0 to PD7, the instruction register 6 that stores the instruction code to be executed, and the instruction code stored in the instruction register 6 an instruction decoder 7 that controls each unit to decode and execute instructions; a program counter 8 that specifies a memory address where a program is stored to sequentially execute the program;
ALU9 that performs calculations and RAM1 that stores data
0, various registers 11, and an 8-bit bus 12 for data transfer between each circuit, but it does not have a ROM for storing programs like the one installed in mass-produced one-chip microcomputers. do not have. Instead, each bit output of the program counter 8 is sent to external terminals PM0 to PM1.
1 and is taken out to the outside via the external terminal.
Instruction codes can be preset into the instruction register 6 via IM0 to IM7. Therefore, by externally connecting the EP-ROM 13 in which the program to be evaluated is written to the terminals PM0 to PM11 and the terminals IM0 to IM7, the evaluation chip 1 can be operated based on the program.

On the other hand, the evaluation chip 1 is provided with circuit type designation data storage circuits 14 and 15 and a preset clock generation circuit 16, which are not provided in the one-chip microcomputer. The circuit type designation data storage circuits 14 and 15 each consist of eight latch circuits to store 8-bit data.
The inputs are commonly connected to external terminals IM0 to IM7, and the storage operation of the data applied to the inputs is performed independently by the preset clock signals OPCL1 and OPCL2 output from the preset clock generation circuit 16. controlled by When the reset signal RST is externally applied, the preset clock generating circuit 16 first outputs the preset clock signal OPCL1 in the first period, and outputs the preset clock signal OPCL2 in the next period. Therefore, when the reset signal RST is applied, the storage operation of the circuit type designation data storage circuit 14 is first controlled, and then the storage operation of the circuit type designation data storage circuit 15 is controlled. In addition, the 8-bit output OPT0 to OPT7 of the circuit type specification data storage circuit 14
is applied to the input/output circuits 2 and 3 to control switching of their circuit formats, while the 8-bit outputs OPT8 to OPT15 of the circuit format designation data storage circuit 15
is applied to the input/output circuits 4 and 5 to control switching of their circuit formats. Therefore, each of the 8
Input/output circuits 2, 3, 4, 5 according to the contents of each bit of bit data (that is, circuit type designation data)
The circuit format can be specified.

The input circuits 2, 3, 4, and 5 have the same circuit format as the input circuit format and output circuit format that can be set in the input/output circuit of the corresponding mass-produced microcomputer. Specifically, the output circuit format can be selected between open drain and pull-up resistor, and the input circuit format can be selected between normal inverter and Schmitt inverter.Switching can be done using a mass-produced micro While the computer switches using a mask, the evaluation chip 1 is electrically switched using signals OPT0 to OPT15. Furthermore, input/output circuits 2, 3,
The circuit formats of the upper 4 bits and lower 4 bits of signals 4 and 5 can be independently selected corresponding to each bit of signals OPT0 to OPT15.

FIG. 2 shows the input/output circuit 2 shown in FIG.
The lower 4 bits of the input/output circuit 2 representing input/output circuits 3, 4, and 5 and the circuit format designation data storage circuits 14 and 15
2 is a circuit diagram of the preset clock generating circuit 16. FIG. In Figure 2, input/output common terminals PA0 to PA
3 is provided with an identical circuit type switching circuit 17, but this circuit type switching circuit 17
All input/output circuits 2, 3, 4, 5 are the same as
is also provided in the same way. The circuit type switching circuit 17 has a drain connected to a signal line 18 connected to each input/output common terminal PA0 to PA3.
- Channel output MOS transistor 19,
A pull-up resistor 20 and an N-channel MOS transistor 21 are connected in series between the power supply V _DD and the signal line 18 , a normal inverter 22 and a Schmitt inverter 23 to which the signal line 18 is applied to both inputs, and each inverter 22 , 23, and N-channel MOS transistors 24 and 25, one electrode of which is connected to the output of 23, and the other electrode of which is wired-OR connected. The MOS transistors 19 and 21 and the pull-up resistor 20 are an output circuit, and the gate of the MOS transistor 19 is connected to each output Q ₀ ~ of a data latch circuit (not shown) that latches data transferred to the bus 12 when an output command is executed. Q ₃ is applied, and the MOS transistor 19 is turned on or off depending on the content of each of its outputs Q ₀ -Q ₃ , thereby outputting data to the input/output common terminals PA 0 -PA 3 . On the other hand, the output OPT0 of the circuit format specification data storage circuit 14 is applied to the gate of the MOS transistor 21, and when the output OPT0 is "1" (that is, V _DD level), the MOS transistor 21 is turned on.
The output format is connected to the pull-up resistor 20, and when the output OPT0 is "0" (ground level), the MOS transistor 21 is turned off.
Open drain output format. In addition, a normal inverter 22, a Schmitt inverter 23
and MOS transistors 24 and 25 are input circuits, and the output OPT1 of the circuit format specification data storage circuit 14 is applied to the gate of the MOS transistor 25, and the gate of the MOS transistor 24 is
Output 1 inverted by inverter 26
is applied, and when the output OPT1 is "1", the MOS transistor 25 is turned on and the output of the Schmitts inverter 23 is selected, and when the output OPT1 is "0", the MOS transistor 24 is turned on. Therefore, the output of the normal inverter 22 is selected. Selected normal inverter 22 or Schmidt inverter 25
The output of is the input of a gate circuit (not shown) which conducts when an input instruction is executed and sends data onto bus 12.
Applied to _G0 to _G3 . In this way, the output circuit format of the lower 4 bits of the input/output circuit 2 is controlled by the output OPT0 of the circuit format designation data storage circuit 14.
The output circuit format of the upper 4 bits is controlled by output OPT1.

In addition, circuit type designation data storage circuits 14 and 15
are each composed of eight latch circuits 27 and 28, and the external terminals IM0 to IM7 of the evaluation chip 1 are commonly connected to the input L of each bit of the latch circuits 27 and 28, and the clock input φ of the latch circuit 27 is A preset clock signal OPCL1 is applied to the latch circuit 28, and a preset clock signal OPCL2 is applied to the clock input φ of the latch circuit 28. As described above, the outputs OPT0 and OPT1 of the latch circuit 27 control the lower 4 bits of the input/output circuit 2, and the outputs OPT2 and OPT3 control the upper 4 bits. Similarly, outputs OPT4 and OPT5 output the lower 4 bits of input/output circuit 3, and outputs OPT6 and OPT7 output the upper 4 bits.
Control bits. On the other hand, the output of the latch circuit 28
OPT8 and OPT9 control the lower 4 bits of the input/output circuit 4, outputs OPT10 and OPT11 control the upper 4 bits, and outputs OPT12 and OPT1
3 outputs the lower 4 bits of the input/output circuit 5.
14 and OPT15 are assigned to control the upper 4 bits.

Preset clock signals OPCL1 and OPCL2
The preset clock generating circuit 16 that outputs
D-FF29, 3 with reset signal RST input to the first stage and clock CP applied to clock terminal φ
0, the OR gate 31 to which the reset signal RST and the output Q of the D-FF 29 are applied, and the OR gate 3
The output obtained by inverting the output of 1 by the inverter 32 and the output of D-
The output of the OR gate 31 is output as the preset clock signal OPCL1, and the output of the AND gate 33 is the preset clock signal OPCL2.
is output as The operation of this preset clock generating circuit 16 is shown in FIG.

In FIG. 3, when the reset signal RST becomes "1" for a time longer than the period of the clock CP, the output of the OR gate 31, that is, the preset clock signal
OPCL1 becomes "1" in synchronization with the rise of the reset signal RST, and D-FF29 outputs "1" for a period corresponding to the "1" period of the reset signal RST by the clock CP, and further ,D-
FF30 outputs "1" with a delay of one cycle of clock CP. Therefore, the preset clock signal
OPCL1 is D from the rising edge of the reset signal RST.
- The pulse becomes “1” until the fall of the output of FF29, while the preset clock signal
OPCL2 becomes a pulse that becomes "1" from the fall of the preset clock OPCL1 to the fall of the output of D-FF30. In addition, the clock pulse
Assuming that the period of CP is equal to one machine cycle of evaluation chip 1, the preset clock signal OPCL
It is convenient to control the storage operation of the circuit type designation data storage circuits 14 and 15 by using OPCL1 and OPCL2.

On the other hand, preset clock signals OPCL1 and
OPCL2 is also applied to the instruction decoder 7 and program counter 8, as shown in FIG.
When OPCL1 or OPCL2 becomes "1", the operation of the instruction decoder 7 is stopped, and the program counter 8 has a function of presetting different addresses. Therefore, the EP in which the program to be evaluated was written -
When operating the ROM13 by connecting it to the evaluation chip 1, the preset clock signals OPCL1 and
EP-ROM1 specified by the address value preset in program counter 8 by OPCL2
By storing 8-bit data specifying the circuit format at address 3, the circuit formats of input/output circuits 2, 3, 4, and 5 can be set. For example, if the EP-ROM 13 is provided with 8-bit data from address 0 to address 4095, the address to be preset in the program counter 8 is set to address 4094 when the preset clock signal OPCL1 is set, Tsuku signal OPCL2
It is set to address 4095 when the preset clock signal OPCL2 disappears, and is reset to address 0000 when the preset clock signal OPCL2 disappears. On the other hand, EP-ROM13
8-bit data A specifying the circuit type of input/output circuits 2 and 3 is stored at address 4094, and 8-bit data B specifying the circuit type of input/output circuits 4 and 5 is stored at address 4095. As shown in FIG. 3, when the reset signal RST is applied when evaluating the program, the preset clock signal OPCL1 becomes "1", so the program counter 8 is set to address 40 of the EP-ROM 13.
94, and EP-ROM13 is at address 409.
4 is applied to terminals IM0 to IM7. At this time, the preset clock signal
Circuit format specified data storage circuit 1 by OPCL1
4 stores data A applied to terminals IM0 to IM7. Then the preset clock signal OPCL
2 becomes “1”, the program counter 8
In order to specify address 4095 of EP-ROM 13, EP-ROM 13 applies data B stored at address 4095 to terminals IM0 to IM7. At this time, the circuit type designation data storage circuit 15 is set to the data B by the preset clock signal OPCL2.
remember. Therefore, data A and data B stored in the circuit type designation data storage circuits 14 and 15
The circuit formats of the input/output circuits 2, 3, 4, and 5 are switched by. When the preset clock signal OPCL2 becomes "0", the program counter 8 is reset, address 0000 of the EP-ROM 13 is designated, and the programs stored at address 0000 are sequentially executed. Furthermore, when the preset clock signal OPCL1 or OPCL2 is output,
The data sent from the EP-ROM 13 is also preset to the instruction register 6, but
Since the operation of the instruction decoder 7 is prohibited by the preset clock signal OPCL1 or OPCL2, the evaluation chip 1 will not malfunction. Further, in this embodiment, an input/output circuit that serves both input and output has been described as an example, but the same applies to setting the circuit format of an input-only circuit or an output-only circuit.

(F) Effects of the Invention As described above, according to the present invention, the same circuit format as that which can be set for the input circuit or output circuit of a mass-produced microcomputer can be specified by multiple bits of data, and Since the data is preset by applying a reset signal, there is no need for an external circuit to connect to the external terminal of the evaluation chip, which has the advantage of making program development and evaluation accurate and easy. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a partial circuit diagram of the block shown in FIG.
FIG. 3 is a timing diagram showing the operation. Explanation of main drawing numbers, 1...Evaluation chip, 2, 3,
4, 5...input/output circuit, 6...instruction register, 7...instruction decoder, 8...
Program counter, 9...ALU, 10...RAM,
11...Register, 12...Bus, 13...EP-
ROM, 14, 15...Circuit type specification data storage circuit, 16...Preset clock generation circuit, 17...
Circuit type switching circuit.

Claims (1)

[Claims] 1. In a chip for program evaluation of a one-chip microcomputer whose input or output circuit format can be selected by a mask, an input circuit having a circuit format that can be set as the input or output of the one-chip microcomputer. Alternatively, an output circuit, a plurality of circuit format designation data storage circuits that output a plurality of control signals for selecting the circuit format of the input circuit or the output circuit, and a program that controls the storage operation of the circuit format designation data storage circuit, respectively. A preset clock generating circuit is provided which sequentially outputs a plurality of preset clock signals for setting predetermined addresses in each counter based on a reset signal applied from the outside, and an external memory addressed by the program counter is provided. By storing data specifying the circuit type at the predetermined address of the circuit, when the reset signal is applied, the data is sequentially preset in the circuit type specifying data storage circuit, and the circuit type of the input circuit or output circuit is set. A microcomputer evaluation chip characterized by: