JPS6366060B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to a multilayer wiring structure in which two or more wiring layers are provided as wiring on the surface of the semiconductor integrated circuit device.

Wiring in semiconductor integrated circuit devices is widely known as wiring formed by doping impurities into the silicon substrate, wiring made of polycrystalline silicon doped with impurities, and wiring made of metal. Formed on the surface of the device. but,
It is not true that two-layer wiring on the surface of a device made of polycrystalline silicon and metal achieves twice the wiring density as compared to a single-layer wiring made only of metal. This is because in conventional two-layer wiring, the unevenness of the device surface caused by the formation of polycrystalline silicon wiring becomes an obstacle, and metal wiring is formed at high density on top of this polycrystalline silicon wiring. This is because it could not be realized with good yield.

An object of the present invention is to provide a semiconductor integrated circuit device with improved yield and interconnect density.

According to the present invention, one end of one wiring layer in an upper layer is located on one wiring layer in a lower layer, and the other end is located between one wiring layer in a lower layer and another wiring layer in an adjacent lower layer. To obtain a semiconductor device circuit device, wherein one wiring layer in the upper layer and one wiring layer in the lower layer are electrically connected through an opening provided in an insulating layer interposed between them. .

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIGS. 1a and 1b are a plan view and a sectional view taken along the line AA' of a conventional multilayer structure. 1st
In the figure, a polycrystalline silicon wiring group 1 is shown on the device surface.
is formed, and a metal wiring group 3 is formed thereon with an insulating film 2 interposed therebetween. In order to form the metal wiring group 3, unnecessary portions of metal, that is, portions for insulating the metal wirings 3, must be removed by photolithography or the like. However, at this time, due to the surface level difference at the end of the polycrystalline silicon wiring 1, the yield of the photolithography method, that is, the resolution of the mask end for selective etching deteriorates, and as a result,
Adjacent metal wiring 3 with unnecessary metal parts 4 remaining
There are many accidents where the two come into contact with each other.

As a method of avoiding this and forming polycrystalline silicon wiring group 1 and metal wiring group 3 that are parallel to each other, as shown in the plan view and cross-sectional view of FIG. A method has been adopted in which metal wiring 5 is formed in between. However,
In this method, when making electrical contact between the polycrystalline silicon wiring 1 and the metal wiring 5, it is necessary to form a portion 6 on the polycrystalline silicon wiring 1 in which a part of the metal wiring 5 extends. Then, the metal wiring 5' adjacent to the overhanging side must be bent near the overhang portion 6 in the direction of the overhang. Therefore, there is a limit to the improvement in the density of the metal wiring 5. This becomes more noticeable as the number of electrical connection points between the two increases.

That is, as shown in FIG. 3, each time the metal wiring group 8 makes electrical contact with the polycrystalline silicon wiring group 7, the adjacent metal wiring 8 bends nearby.
Note that FIG. 3 is a schematic diagram, and each wiring 7,
The width of 8 is not shown. As the number of wires running in parallel increases, the number of bends increases dramatically. As a result, the time required to design a mask used in manufacturing a semiconductor integrated circuit device increases, and furthermore, this becomes a factor causing design errors.
On the other hand, if metal wiring is not run in the row next to the metal wiring that is in electrical contact with the polycrystalline silicon wiring, complexity in mask design can be solved, but at the cost of the accumulation of metal wiring. Density is significantly reduced.

On the other hand, even if the polycrystalline silicon wiring 7 were to protrude below the straight metal wiring group 8 to make electrical contact, the same design complexity would occur, and If you try to resolve this,
This time, the integration density of polycrystalline silicon wiring is significantly reduced. Therefore, in an embodiment of the present invention, as shown in FIG. 4, when forming the metal wiring 9 on the polycrystalline silicon wiring 11, the metal wiring 9 is not formed directly above the polycrystalline silicon wiring 11. The metal wiring 9 is formed in such a position that its end line is shifted from the end line of the polycrystalline silicon wiring 1, and more than half of the width of the metal wiring 9 is above the polycrystalline silicon wiring 11. The distance l and m between the end line of the metal wiring 9 and the end line of the polycrystalline silicon oxide wire 11 is 0.5 μm.
If there is more than that, the effect will be great. Therefore, because of the shift distances l and m, the top of the stepped portion of the line at the end of the polycrystalline silicon wiring 11 is covered by the metal wiring 9, so that it is not like the conventional wiring as shown in FIG. Contact accidents between adjacent metal wiring due to residual metal do not occur. Of course, it is not necessary that l=m.

Further, since more than half of the width of the metal wiring 9 overlaps with the polycrystalline silicon wiring 11, the metal wiring 9
Mutual electrical contact between the wire and the polycrystalline silicon wiring 11 is made through a contact hole 1 provided in the overlapping portion thereof.
Since this can be done with zero, there is no effect on the metal wiring 9 adjacent to that metal wiring 9. Therefore, there is no need for the complexity of mask design associated with the conventional wiring structure as shown in FIG. 2, and there is no problem of a significant decrease in wiring density.

In this manner, such an integrated circuit device has improved yield and wiring density.

Note that the present invention is not limited to the above embodiments; for example, the size of the upper layer wiring that overlaps with the lower layer wiring is set to more than half, but it may be made smaller as long as it is within the range where the contact hole 10 can be formed. be able to. Alternatively, both layers may be made of the same material.

As explained above, according to the present invention, it is possible to realize two-layer wiring on the device surface, in which polycrystalline silicon wiring groups and metal wiring groups running parallel to each other are stacked, with high integration density and high yield. .

[Brief explanation of drawings]

Figures 1a and 1b are a plan view and a sectional view taken along line A-A' of the conventional multilayer wiring structure, respectively;
FIGS. 2a and 2b are a plan view and a sectional view taken along the line A-A' of another conventional multilayer wiring structure, respectively. FIG. 3 is a plan view showing another conventional example, and FIG. 4 a.
and b are a plan view and a sectional view taken along line AA' of a multilayer wiring structure according to an embodiment of the present invention, respectively. In FIG. 1, 1 is a polycrystalline silicon wiring, 2 is an insulating film, 3 is a metal wiring, and 4 is a remaining unnecessary metal portion. In Figure 2, 5,5'
is a metal wiring, and 6 is a protruding portion of the metal wiring. In Fig. 3, 7... polycrystalline silicon wiring, 8... metal wiring, and in Fig. 4, 9... metal wiring, 10... electrical contact hole between polycrystalline silicon wiring and metal wiring. .

Claims (1)

[Claims] 1. A first wiring layer formed in parallel on a semiconductor substrate, and a weight on the first wiring layer with an insulating layer interposed therebetween,
The first wiring layer has a second wiring layer having a parallel portion, and the parallel portion of the second wiring layer has a line at one end thereof in a predetermined line of the first wiring layer. and the line at the other end is located between the predetermined wire of the first wiring layer and another adjacent wire, and the predetermined wire of the first wiring layer is A semiconductor integrated circuit device, wherein an upper portion thereof is connected to the parallel portion of the second wiring layer.