JPS6366452B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tuning display circuit for, for example, a tervision receiver.

Generally, in electrical equipment such as television receivers, it is difficult to accurately tune the local oscillation frequency of a tuner to the frequency of a channel that a viewer desires to receive. In particular, in the case of a dial-type electronic tuner, the user must always operate the tuning dial to the desired reception frequency so that the tuner's local oscillation frequency matches the desired reception channel. However, in the case of such tuners, it is generally difficult to accurately tune them, and although slight tuning deviations have been corrected using electric circuits, there are limits to this, and it is still difficult to accurately tune them. It is necessary to synchronize. If such accurate synchronization was not performed, there was a risk that the resolution of the received image would deteriorate or the colors would not appear.

The present invention has been made in view of the above points, and includes a first display device, a second display device, and a control circuit for controlling these display devices as desired. The first display device is made to blink when there is no received signal of the channel, and when a signal is detected, it stops blinking and turns on, and when the optimum synchronization state is reached, the first display device blinks. To provide a tuning display circuit in which a second display device is turned on when a second display device is turned off, and which enables accurate and reliable optimal tuning.

EMBODIMENT OF THE INVENTION Hereinafter, one Example based on this invention is described based on drawing.

FIG. 1 shows a block diagram showing one embodiment of the present invention. In this figure, numeral 1 is a terminal for inputting signal pulses supplied from a flyback transformer (not shown), 2 is a terminal for inputting synchronous pulses supplied from a synchronous circuit (not shown), and 3 and 4 are AFT (automatic microcontrollers). 5 is an AND gate, 6 is an OR gate, and 7 is an inverter. Also, code 8
9 is an oscillation circuit, 9 is a detection circuit, 10 and 11 are light emitting diodes, 12 and 13 are AND gates, 14 and 15 are driving transistors, and 16 and 17 are resistors.

By the way, the signal pulse obtained from the flyback transformer is applied to terminal 1, and the synchronizing pulse is applied to terminal 2 and supplied to AND gate 5. The output signal of the AND gate 5 and the output signal of the oscillation circuit 8 are configured to be supplied to one input terminal of the AND gate 13 via the OR gate 6. The output signal of the AND gate 13 is applied to the base of a transistor 14 to drive the light emitting diode 10 connected to the collector of the transistor 14 whose emitter is grounded. On the other hand, the output signal of the AFT circuit is supplied from terminals 3 and 4 to one input terminal of an AND gate 12 via a detection circuit 9. 5 output signals are supplied. The output signal of the AND gate 5 is supplied to the base of a transistor 15 whose emitter is grounded, and is also supplied to the other input terminal of the AND gate 13 via an inverter 7.

The operation of the present invention configured as above will be explained with reference to FIG. FIG. 2 shows a waveform diagram of signals of various parts according to the present invention. In this figure, the symbols A ₁ , A ₂ , B to E are each point in Figure 1.
Signal waveforms at A ₁ , A ₂ , B to E are shown.

A1 and A2 shown in FIG. 2 show AFT characteristics, where the vertical axis shows the voltage V and the horizontal axis shows the frequency f. The AFT voltage of a typical television receiver is
It shows an S-shaped characteristic as shown in FIG. 2, and the characteristics A1 and A2 exhibit opposite characteristics. AFT like this
When voltages A1 and A2 are input to the detection circuit 9, the second
As shown in Figure C, a signal indicating an "H" (high) level is obtained only near the intersection of the AFT voltages.

Also, flyback transformer signal 1 and synchronization signal 2
When the signal is passed through the AND gate 5, as shown in FIG. 2B, when the received channel signal has a signal above a predetermined level, it becomes an "H" level, and when there is no signal below a predetermined level, it becomes an "L" (low) level. A discrimination signal is obtained. When controlling the lighting of the light emitting diode 10 using this signal, the receiving channel is at "L" (low) level when there is no signal, and "H" when there is a signal.
Therefore, the output of the OR gate 6 is the output pulse of the oscillation circuit 8 when there is no signal (see g in Fig. 2E: its frequency is about several Hz to several + Hz), and when there is a signal, it outputs the output pulse of the oscillation circuit 8 as it is, and when there is a signal, it outputs the output pulse of the oscillation circuit 8 as it is, and when there is a signal, ”Output the level.
Furthermore, when the output signal of the detection circuit 9 (FIG. 2C) and the output signal of the AND gate 5 (FIG. 2B) are ANDed by the AND gate 12, a signal as shown in FIG. The signal inverted by the inverter 7 and the output signal of the OR gate 6 are connected to the AND gate 13.
When the AND is performed, a signal as shown in FIG. 2E is obtained.
As a result, the first light emitting diode 10 is dimmed by the output pulse of the oscillation circuit 8 when there is no signal, continues to light up when there is a signal, and turns off at the time of optimum tuning, and at the same time is turned off by the signal shown in FIG. 2D. The second light emitting diode 11 lights up.

Therefore, optimal tuning can be achieved while monitoring the display states of these display devices 10 and 11.

Next, the AFT detection circuit 9 will be explained.

FIG. 3 shows a circuit diagram of an embodiment of the detection circuit. Terminal 3 is connected to the base of the first transistor Tr 1 via a resistor R ₁ , and terminal 4 is connected to the base of the first transistor Tr ₁ .
It is connected to the base of the second transistor Tr ₂ via a resistor R ₂ . This first transistor Tr ₁
The base of is grounded through resistor R ₃ and
It is connected to the emitter of transistor Tr ₁ via diode D ₁ . Also, the second transistor
The base of Tr ₂ is connected to ground through resistor R ₄ and to the second transistor through diode D ₂ .
Connected to the emitter of Tr ₂ . The emitters of the first and second transistors Tr ₁ and Tr ₂ are connected to each other.

Furthermore, the collector of the first transistor Tr ₁ is
It is connected to the power supply Vcc via a resistor R ₅ and also to one input terminal of the AND gate 18 . Moreover, the collector of the second transistor Tr ₂ is
It is connected to the power supply Vcc via a resistor R ₆ and also to the other input terminal of the AND gate 18 . The output signal of the AND gate 18 can be outputted as the output signal of the detection circuit 9.

The operation of the detection circuit 9 having the above configuration will be explained.

The difference in voltage at AFT terminals 3 and 4 is |V ₃ −
When V ₄ |≧2V _BE , the output signal of this detection circuit 9 becomes "H" level. That is, if the voltage supplied to input terminal 3 is V ₃ , the voltage supplied to input terminal 4 is V ₄ , and the base-emitter voltage of transistor Tr ₁ or Tr ₂ is V _BE , then V ₃ and When the difference in V ₄ becomes 2V _BE or more, transistor Tr ₁ or Tr ₂ is turned on.

For example, when V ₃ −V ₄ ≧2V _BE , the first transistor Tr ₁ is turned on, and V ₄ −V ₃ ≧2V _BE
When , the second transistor Tr ₂ turns on, and only when |V ₃ −V ₄ |<2V _BE , both transistors turn on.
Tr ₁ and Tr ₂ are turned off. Therefore, both inputs of the AND gate 18 become logic "1" when the transistors Tr ₁ and Tr ₂ are off, and the output terminal has the second
A signal having a waveform as shown in FIG. C is output.

In this way, when there is no signal in the reception channel, the first light emitting diode 10 flashes to indicate the no signal state, and when there is a signal, the first light emitting diode 10 lights up. Furthermore, when the tuning is adjusted and the optimum tuning is obtained, the first light emitting diode 1
At the same time as 0 turns off, the second light emitting diode 1
1 lights up to indicate optimal tuning.

As described above, the present invention includes first and second display devices and their control circuits, and causes the first display device to blink when there is no signal and to turn on when there is a signal, When optimal synchronization is achieved, the light is turned off and the second display device is turned on at the same time.
This has the effect that a reliable and accurate state of synchronization can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a signal waveform diagram according to the embodiment of FIG. 1, and FIG. 3 shows a specific configuration of the detection circuit of FIG. 1. It is a circuit diagram. 5, 12, 13, 18...and gate, 6...
...OR gate, 7 ... Inverter, 8 ... Oscillator circuit, 9 ... Detection circuit, 10, 11 ... Light emitting diode, 14, 15 ... Transistor, 16, 17
...Resistor, _R1 to _R6 ...Resistor, _D1 and _D2 ...Diode, _Tr1 and _Tr2 ...Transistor.

Claims (1)

[Claims] 1. An electronic tuning tuner for receiving broadcast signals,
A tuning display circuit that controls the lighting/extinguishing states of the first and second display devices according to the tuning state, which determines the presence or absence of a received signal of a selected channel, and determines whether or not there is a received signal of a selected channel, and which detects a signal whose received signal is at a predetermined level or higher. signal discrimination means for generating a discrimination signal that sometimes exhibits a first level and exhibits a second level when there is no signal below a predetermined level;
a signal detection circuit that is supplied with the AFT voltage that changes in a linear characteristic and the discrimination signal as input, and generates a first signal near the tuning frequency when a signal is present; and a signal detection circuit that generates a second signal having a predetermined frequency. oscillating means, taking a logical sum of the second signal and the discrimination signal from the signal discrimination means, outputting the second signal when there is no signal, and outputting the first level discrimination signal when there is a signal; and a first logic means for driving the first display device by performing a logical product of the output of the signal detection means and the output of the first logic means, and driving the first display device when there is no signal. A first lamp that is turned on and off by a second signal, turned on when a signal is present, turned on by the first level discrimination signal, and turned off using the first signal near the tuning frequency. It is characterized by comprising a driving means, and a second driving means for driving the second display device by the first signal and lighting the second display device at a frequency near the tuning frequency. tuning display circuit.