JPS6367159B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a low power electronic timepiece with particular temperature compensation.

Conventionally, the size of electronic watches was determined by
One of the crystal oscillators, pulse motors, electronic display elements, and batteries has reached its limit, and as technology has developed, it has alternately given up its position as the limit, and has followed the path of shrinking its volume.

There are frequency division power, pulse motor power, and crystal oscillator power that determine the operating life of a watch.
There is a leakage current loss of the battery used in combination with these, and the operating life of the electronic watch is determined by the relationship between these and the current capacity of the battery used. In the marketability of battery-powered watches, not only performance, but also the above-mentioned external dimensions and operating life account for a large proportion, and only recently have they reached the level of self-winding mechanical watches. Furthermore, according to recent technology, the power required to drive a watch is about to drop from 10 μW a few years ago to less than 1 μW due to improved motor characteristics and rationalized design of the wheel train mechanism. In addition, the power required to display the time on an electronic clock has become less than 0.5 μW, using a liquid crystal display as an example. If we consider only the power required to display the time, the battery capacity can be reduced to 1/10, or it has become possible to design a clock with an operating life of 10 years. Currently, the power consumption of battery-powered watches other than the time display is 3μW.
~1.5μW exists, which is 2/3 of the oscillation circuit and 1/3
Frequency division and other non-oscillating clock circuit systems are becoming increasingly consumed. Therefore, it can be said that two-thirds of the current difficulties in making watches thinner and extending their life span are the electric circuits.

The present invention relates to a system configuration that can reduce the power consumption of an electric circuit, which is the problem mentioned above, and can also be expected to improve performance. The key point of the invention is to connect a capacitor in series with the power supply voltage to store energy, then connect them in parallel to average the potential difference across the capacitor, and use these switching operations to create a highly efficient low voltage source. By using this low voltage to perform crystal oscillation and information processing for clocks, the information processing performed by conventional electronic circuits is reduced to 1/2 of the original voltage.
The total power consumption is 1/4 to 1/25, and the total power consumption is 1/10 that of conventional electronic watches, providing a thinner electronic watch with a long operating life. Furthermore, according to this configuration, electronic components can be used with low impedance, which is highly effective in terms of accuracy, stability, and ease of maintaining accuracy of the crystal oscillator. In addition, this configuration can be used for multi-functional watches that feature increased functionality through electronic circuits, such as multiple alarm watches, clocks with calculators, etc.
Alternatively, it is highly effective when used in pure pocketable devices such as notebook-type calculators, or systems that use high voltage or low voltage depending on the situation, such as systems that always measure time with a low voltage source and display elements. If you want to increase the contrast of the calculator, operate at a low speed when displaying numeric values or displaying calculation results, and increase the speed of calculations only during calculation commands, switch the calculation unit power supply and use a high voltage unit to increase the upper limit of the operating frequency of the calculator. This is highly effective, as it can be used to increase the frequency of clock pulses to improve calculation speed, thereby achieving both lower power consumption and higher performance.

Next, one embodiment of the present invention will be described based on the drawings. In FIG. 1, thick black lines indicate energy flow paths, and thin black lines indicate signal paths. In FIG. 1, 111 is an extremely low power sub-oscillator for the voltage conversion circuit of the present invention, which is an integrated circuit made by connecting three to five stages of low mutual conductance C/MOS inverters in a ring. It is a ring oscillator. A switching circuit 112 is switched in synchronization with a signal obtained from the sub-oscillator 111. Reference numeral 113 denotes a time reference signal source for the clock, which is realized by, for example, a crystal oscillation circuit. Reference numeral 114 is a timekeeping unit signal synthesis mechanism that synthesizes the output of the time reference signal source 113, for example, 32768 Hz, into a signal that is the unit of ticking of a clock. For graphs, 100Hz is synthesized so that it can be measured to the nearest 1/100. Reference numeral 115 denotes a timekeeping mechanism, which is composed of a counter capable of setting an initial value, and counts the signal from the timekeeping unit signal synthesis mechanism 114 to hold the time starting from the initial value time. 116 is a level converter and a crystal oscillator 113;
The counting signal synthesis mechanism 114 and the clocking mechanism 115 are
V _SS 'For example, if the operating voltage level is different, such as operating at 0.3 V and the system after the display device 117 operates at V _SS1 , for example 1.55 Volt, convert only the voltage level without changing the information to be transmitted by the signal. do. The level converter 116 is inserted between the count signal synthesis mechanism 114 and the clock mechanism 115, and the clock mechanism 115 is set to V _SS 1.
For example, the counting signal synthesis mechanism 11
The first stage is operated at V _SS ' and the second stage is operated at V _SS i.
A level converter 116 is operated between the front stage and the rear stage.
It is also conceivable to enter it in that way. The number of signal paths to be level-converted and the frequencies handled differ depending on the position of the input. In general, it is better to install the level converter 116 on the higher frequency side than the clock mechanism because the number of level converters is smaller, but power consumption increases, and it is better to install the level converter 116 on the lower frequency side than the clock mechanism because the number of level converters is smaller. This increases the load on the chip side, but reduces power consumption. The display device 117 is a block that displays time information or other instruction information held by the clock mechanism 115, and includes a decoder, a display drive circuit, and a display element. Reference numeral 118 denotes an electrical energy source, such as a silver peroxide battery or a system combining a solar battery and a secondary battery. The switching pulse that controls the switching element can be easily extracted from the middle of the frequency division stage in the case of a quartz clock, but there is also a method to use an extremely low power ring oscillator independently of this, which uses a crystal oscillator with a high Q value. Compared to the slow start-up characteristics of the low-power crystal oscillators, a ring oscillator with fast oscillation start-up characteristics is prepared as an auxiliary oscillator, making it possible to perform temperature detection and voltage conversion switching.

FIG. 2 shows a specific example of the sub-oscillator A, waveform shaping circuit B, and switching circuit C for voltage conversion in the present application. 201 is a 1.6 Volt battery, 21
1 is low Gmi P channel enhancement F.
ET, 212 is N-channel enhancement FET
It is. In FIG. 2, a pair of P-channel enhancement FET 211 and N-channel enhancement FET 212 form an inverter circuit, and if the gain is sufficient, it oscillates at a frequency whose half cycle is three times the response time of the circuit. .

Using such a ring oscillator as a sub-oscillator is effective because an external capacitor is not required when integrating the circuit.

The frequency is, for example, 1000Hz to 100Hz, and the current consumed by this oscillation is 0.1 μA to 0.01 μA. 21
The low Gm (mutual conductance) FET of 1 passes through FETs 211 and 212 during oscillation, shorting the power supply and reducing the flowing current component. The reduction in the through current can also be achieved by connecting the through current.

The signal φ _D 213 is also connected to the low Gm inverter 2.
21, and the switching circuit C
is supplied as a complementary signal pair with φ.
The signals supplied to the switching circuit C do not necessarily have to be phase-inverted complementary signals.

If it is necessary to supply m-phase (m is a natural number) signals to the switching section, the output signals of an odd number of inverters, for example 2n+1 ((2n+1)>m, m is a natural number) of the oscillation section A, are the same. Utilizing the fact that the phases differ with each other, it is possible to obtain a number of signals equal to or less than (2n+1) and their inverted signals by a decoder circuit such as an exclusive OR of the outputs of adjacent inverters.

The embodiment of the switching circuit C shown in FIG. 2 only needs to have two single-phase complementary signals.

231, 233, 232, and 234 in Fig. 2 are all switching circuits.Functionally, when φ=H, the even numbered switches 232, 234 are turned on, and the odd numbered switches 231, 233 are turned on.
It becomes OFF.

In this state of φ=H, capacitor C ₁ 241 and
C ₂ 242 is connected in series and charged with its ends connected to V _DD and V _SS .

If a load is connected between the output terminal 251 of V _SS 1/2 and V _DD or V _SS of the power supply, and if the capacitance ratio of C ₁ and C ₂ is equal, each of C ₁ and C ₂ The voltages V ₁ and V ₂ across are not equal. Next, when φ=L, the odd numbered switches 231 and 233 turn on, and the even numbered switches 232 and 234 turn on.
When it is turned OFF, the capacitors C ₁ 241 and C ₂ 242 are connected in parallel, and V ₁ =V ₂ (≠0). H of φ,
By alternately switching L, a voltage of 1/2 of V _SS 1, measured between V _DD and V _SS 1/2, is obtained from the V _SS 1/2 output terminal of the 251. Capacitors with widely different values such as C ₁ = 2.5 μF and C ₂ = 0.1 μF may be used, but
The closer the capacitance values of C ₁ and C ₂ are, the higher the utilization efficiency is.

This is because when the switching operation of the switching circuit causes charge transfer between capacitors, accompanied by a joule loss, the power efficiency decreases. If the values of the capacitors 241 and 242 are completely equal, the charging voltages of the capacitors immediately before they are connected in parallel phase are equal, and no charge transfer occurs between the capacitors when they are connected in parallel.

231 is a switch using P channel FET.
In the ON state, it is necessary to connect to V _DD ,
In the OFF state, the drain potential is between V _DD and V _SS 1, the impedance between the source and drain must be large, and the leakage current must be negligibly small.

FET234 and FET231 are complementary ON and
OFF, and when φ=H, N channel FET234
ON, P channel FET 231 turns OFF.

Reference numerals 232 and 233 are transmission gates, and since the potential at the point of switching is between V _DD and V _SS , P channel and N channel FETs are paired to ensure that they are turned on. . In Figure 2, P channel (hereinafter abbreviated as P-CH)
All FET substrates are connected to V _DD , and all N-channel (hereinafter abbreviated as N-CH) FET substrates are connected to V _SS 1.

Instead of using the oscillator shown in Figure 2A, a crystal oscillator, which is a clock time reference signal source, is directly driven by the battery voltage, and the voltage conversion circuit is driven using the oscillation force signal or its frequency-divided signal. You can also use a system that does this. The purpose of creating a low voltage source in this case is
For example, it can be used to supply a low voltage for a liquid crystal matrix drive, to lower the bias voltage of a crystal oscillator that is already oscillating at a low threshold voltage, or to reduce the bias voltage applied to a resistor using a field effect transistor. used for supplying

Since the oscillator section in FIG. 2A is a sub-oscillator for reducing current consumption, care must be taken to reduce the current consumption here. The output waveform of the oscillation output signal 213 is a blunt waveform, and when the blunt waveform is directly applied to the inverter 221, a through current component (P-
Since the power supply short-circuit current component that flows through both CHFET and N-CHFET becomes large, two inverter outputs adjacent to each other in the oscillation section are used to shape the waveform without the through-current component as shown in Figure 5. I can do it.

Figure 3A is an example of obtaining 1/3 of the voltage.
301 is a battery, 313 is an oscillator, 321 is a waveform shaping device, and 324 is an inverter for obtaining an inverted waveform. At φ=H, N-CH FET332,
Transmission gates (hereinafter referred to as TG) 342 and 344
Turn on, three capacitors 351, 35
2,353 are connected in series to the power supply,
It will be charged. Next, when φ=L, FET332,
T.G342 and 344 are turned OFF, and P-CHFET
331, 341 and TG343, 345 are turned on, and three capacitors 351, 352, 353
are connected in parallel to average the voltage. This averaging operation corrects variations in voltage during charging of the three capacitors due to variations in capacitance of the capacitors, and creates a voltage that is exactly 1/3 of the power supply voltage. As already mentioned, in order to achieve high efficiency, the ratio of the values of the three capacitors must be 1.
It is desirable that the capacitor capacity is large in order to reduce the output impedance of the low voltage source, and from the standpoint of realizing a low voltage circuit in a small volume and at low cost,
The smaller the capacitance, the better. FIG. 3B is a system that satisfies these conflicting demands. Here, the system of FIG. 3A using a small capacitance capacitor is used as is for voltage conversion, and the output of the voltage converter is connected to a large capacitance capacitor 399 using a switch circuit 389.

A possible method is to transfer charges in a state where a low voltage output is obtained. Since charge transfer is performed in the low voltage output phase, in steady state, the voltage of the large capacity capacitor and the output voltage of the low voltage circuit almost match, and the Joule loss component due to parallel connection of capacitors with different voltages is Almost never occurs. Also, the differential output impedance seen from the output load has a low value due to the large capacitance capacitor at the output end.

Figure 4 generally shows n/m of the given power supply voltage.
(m, n are natural numbers) It is assumed that the capacitances of the capacitors of 411 to 4 nm are all Co and that the power supply voltage (potential difference between V _DD and V _SS i) is Vo. For the sake of simplicity, let's assume that the capacitors 411 to 4mn are not charged with any electric charge, and if they are connected as shown in Figure 4A, each capacitor will have an equal charge of Qo = CoVo/n stored, A voltage of Vo/n appears across the capacitor.
Next, if we change the wiring so that m capacitors are connected in series while keeping the orientation of the capacitors aligned, if we do not change the total number of capacitors, we will have n columns with m capacitors in series. If we connect these n columns in parallel, we get
When connected in parallel, the voltage across the column is (m/
n) Becomes Vo. Also, it is clear that in the above operation process, no current is generated due to the connection of the capacitor, so theoretically the voltage is converted with 100% efficiency. Since each capacitor has the same capacity, 100% efficiency can be expected.
The above is an example for explaining the operating principle in an easy-to-understand manner, and in reality, the number of capacitors can be reduced.

In the case of partial pressure ratio>1/2, 1-partial pressure ratio<1/2. Therefore, the number of capacitors can be saved by creating the remaining voltage and using the voltage difference from Vo.

Replacing series/parallel capacitors When reconnecting a column of m capacitors connected in series to a column of n capacitors connected in series, replace the capacitors that are constantly connected in series with one small-capacity capacitor column. It can be replaced with a capacitor of at least m series n capacitor columns;
In other words, m ² capacitors can be replaced with one Co capacitor.

FIG. 5 shows an example of an integrated circuit configuration in which the voltage conversion circuit according to the present invention is further combined with a voltage control circuit based on the threshold value of the circuit element. The configuration shown in Figure 5 shows that a battery such as a lithium battery, which has a large power capacity and a very good shelf life, has a high voltage (approximately 2.6 to 3.2 Volt) for use in watches, and has a higher voltage than a silver battery. This is a very convenient circuit for effectively utilizing batteries that have a large voltage fluctuation rate. 500 is a battery, and 501, 502, and 503 are low-current inverters, three of which are connected in a ring to generate oscillation.
The output of each inverter is an unshaped oscillation waveform whose phase is shifted by 2π/3, so it is 504
Waveform shaping gate allows waveform shaping with small through-current. When the outputs of 502 and 503 are both "H", the output of 504 is set to "L", and when the outputs of 502 and 503 are both "L", the output of 504 is set to "H". The output of 504 is further waveform-shaped by two stages of inverter circuits, and is converted to 508, 509 by the already explained capacitor connection switching circuit.
Switch the two capacitors in series and parallel to 1/2
Obtain the voltage of V _SS1 . Furthermore, 510 is a combination of input and output of a C/MOS inverter, and P-ch-
For voltages that exceed the sum of the absolute values of the FET and N-ch-FET thresholds, they exhibit voltage (source-to-source) current characteristics similar to those of a Zener diode, so a voltage control circuit based on the sum of these thresholds is It consists of
The power supply voltage of the C/MOS inverter 510 is {|V _TP
In addition to |+V _TN }, the voltage component |V _TP | due to the source follower of P-ch-FET513 is added, and 2
|V _TP |+V _TN . FET511 is N-ch-
High resistance using FET. 512 is a large current capacity P-ch-FET, and since it is a source follower, the source output voltage is lower than the gate voltage.
There is a voltage difference only for V _TP , and P-ch-FET513
The voltage that has been raised is P-ch-FET5
It is used to compensate for the differential voltage at 12. The output voltage of the control output 519 is approximately |V _TP |+V _TN , and due to variations in the threshold value during IC manufacturing,
In this circuit, matching is achieved by controlling the power supply voltage, and after wide voltage conversion is performed using an efficient voltage conversion circuit, finer voltage adjustment is performed using FET.
By using the threshold value as a reference, a system with extremely high energy efficiency can be realized.

520 is a crystal oscillation circuit, 521 is a waveform shaping circuit that generates a time reference signal, 523 is a frequency dividing circuit,
A clock unit signal is synthesized from the output of the waveform shaping circuit 521. 524 is a clock circuit that handles low frequencies.
Since the current consumption is small, the power source of the crystal oscillator 520, which has a lower impedance than the frequency divider 523, is used. 525 is a level shifter that converts the logic output signal of the clock circuit 524 into a high voltage, and outputs it to the display device 526.
Supplies the signal that drives the.

FIG. 6A is a block diagram of a system combining a temperature correction circuit and a voltage conversion circuit according to the configuration of the present invention. 600 is a silver battery, 601, 602, 60
3 is a low transconductance inverter, 604
is a resistance, 605 is a capacitance, and 604 and 60
5 can also be incorporated into an integrated circuit. If the conductance and stray capacitance of 601, 602, and 603 in the integrated circuit are not created with good reproducibility, 60
The oscillation frequency can be adjusted or the temperature-oscillation frequency characteristic can be corrected by attaching the resistor 4 externally. To adjust the oscillation frequency, 605 may be used as an external adjustment capacitor of the integrated circuit, or the inverter 605 may be used as an external adjustment capacitor of the integrated circuit.
It may be adjusted by adjusting the power supply voltage supplied to 01, 602, and 603 to change the mutual conductance. 610 is the voltage conversion circuit according to the present invention, which has already been explained. The oscillation circuit using inverters 601, 602, and 603 is a sub-oscillator corresponding to 111 in FIG. 602 and 603, but if you do not use an external temperature-sensitive element such as a thermistor resistor for 604 or a temperature-sensitive capacitor for 605, or if you use a household clock that uses manganese batteries, an oscillation inverter is required. It is better to supply power from a simple regulator circuit based on the threshold value of the control terminal of the transistor, which is an active element used in the components 601, 602, and 603, to absorb deviations in characteristics of transistor constants during integrated circuit manufacturing. Good to be able to do it. 611 is a time reference signal source, which is a crystal oscillation circuit.

612 is a frequency divider, and 613 is a data type flip-flop, which is an embodiment of a circuit for obtaining a frequency difference. When the frequency difference is very large,
The output of the data type flip-flop 613 gives an integer multiple of the difference frequency, so for example, the data input D is 16384 Hz and the clock input φ is 1023 Hz.
Hz, a difference frequency signal of 16×(1024−1023) Hz is obtained. 614 is a square multiplication circuit,
It is provided to synthesize a signal for correcting the second-order temperature coefficient of the crystal resonator, that is, a temperature compensation function. 6
16 is an example of a frequency adder circuit, which is an exclusive logic circuit or a coincidence circuit (iden-) which is its logical negation.
tity gate) is the simplest. 623 is a second signal generation circuit 601 for temperature-sensitive oscillator and voltage conversion circuit;
This is a circuit for synchronizing the output 606 of 602 and 603 with the phase of the signal of 611.The frequencies of the data input and output of 623 are almost equal, and only the phase is synchronized to 606 to the output of the frequency addition circuit 616. It has changed into something. 624 is a frequency divider that generates a low frequency signal for compensation.

The phase of the output signal of the frequency divider 624 is determined by the frequency divider 612.
The waveform is shifted by a half period of the crystal oscillation circuit 611 by utilizing the phase of the output signal of the inverter 622 and the signal inversion effect of the inverter 622. 626 is a gate for frequency addition. In the above mentioned place,
The output of the multiplier circuit 614 for correcting the secondary characteristic of the temperature characteristic and the output of the frequency divider 624 of the signal generating circuit for correcting the primary characteristic are transmitted to the crystal oscillation circuit 611 which is a signal source for the time reference. However, it is not necessary to use it originally, it is only used because it is nearby as a frequency source, and it is possible to synthesize it using another oscillator or the voltage conversion signal 606. It can also be synthesized from An outline of the operation of FIG. 6A will be explained. A relatively accurate frequency signal from the time reference crystal oscillator 611 is divided by a frequency divider 612, and a difference frequency signal x from the output 606 of the ring oscillator is obtained by a gate 613, which is squared by a squaring circuit 614. It becomes a temperature compensation function signal containing the term x ² and passes through the frequency divider 615,
At gate 616, the frequency is added to the signal that bypassed the squaring circuit. This output is further added to the output signal 606 of the ring oscillation circuit at the gate 626 to become a signal with a frequency sufficiently stable against temperature changes, and the frequency is divided by the frequency divider 617 to become the time-keeping signal. and is transmitted to the time keeping circuit 618. That is, temperature information is collected by the sampling operation of the flip-flop 613,
It is included in the output x to become a temperature difference signal, which is processed by the arithmetic circuit as described above and combined with other frequency components to produce a temperature-corrected time-keeping signal, which includes elements 613, 614, 615, 61
6, 624, 626, etc. constitute an arithmetic circuit for temperature correction of the oscillation frequency. FIG. 6B is a squaring circuit, and the squaring circuit 614 for correcting secondary characteristics in FIG. 6A
This is an example corresponding to. x is the squared input signal, REF is the time signal for frequency measurement, and the sixth
Synthesis is performed based on stable frequency signals such as those from the holding mechanism 618, frequency divider 617, frequency divider 615, frequency divider 612, or crystal oscillation circuit 611 in FIG. As an example of frequency measurement, FIG. 6B counts the number of pulses on the x input during a given period of REF. This method calculates the average frequency over a relatively long period of frequency measurement, reducing the effects of jitter and noise, and making effective use of the constant frequency property of time reference signals for clocks. . In Figure 6B
REF↑ is a reset signal that falls for a short time in synchronization with the rise of the REF signal, and is synthesized from the REF signal and the clock pulse φCl by a delay by a logic circuit 631 and a gate 632. Reference numeral 633 denotes a counter which is reset by the ↑ signal to a count value of "0", after which it counts squared signal pulses of x and increases the count value in a stepwise waveform with a constant slope as a function of time. The pulse width of REF is short during the high level period and long during the low level period. this
Count the unknown frequency signal x during the high level period of the REF signal, hold this count value during the remaining low level period, and create the REF rising differential signal REF↑ at the rising edge of the next REF signal. The count value is repeatedly reset to 0. For example, if the high level period of REF is 1 second,
It is best to choose a low level period of REF between 15 seconds and 300 seconds. The time constant of heat conduction in response to step-like temperature changes in a watch housed in a metal case is approximately 8 seconds.
15 seconds, and the minimum time for temperature change when a person is carrying the watch is several minutes, and it takes several hours or even tens of hours for a change to actually appear as a visible change in the time the watch is kept on. It takes time, so if you don't care about the time indication error of 0.5 seconds or less, use the above method.
The low level period of the REF signal may be as long as about one hour. Therefore, in FIG. 6B, the counter 633 always holds the frequency of the x input. For example, if a counter configured with seven flip-flops connected in cascade is used, the counter 633 maintains the _frequency of the x _input . An example for performing a square calculation of temperature difference information using 7 bits will be shown. Assuming that the above temperature difference information is Θ and expressed as Θ=q ₀ 2 ⁰ + q ₁ 2 ¹ +...+q ₆ 2 ⁶ , Q ₁ i=H (high level) corresponds to qi=1,
Q ₁ i=L (low level) can be set to correspond to qi=0. To realize Θ ² , first create a signal proportional to Θ ¹ . Sequentially divide the constant frequency _c signal C by 1/2 using a binary counter, 2 ^-i・_c
When the logical product of the signal Ci with the frequency of and Q ₁ i is added using the OR gate, the signal with the frequency 〓 ₁ proportional to Θ is obtained.
Cθ ₁ is obtained. Next, in exactly the same operation, using Cθ ₁ instead of C, the signals Cθ ₁ i and Q ₁ i with frequencies of 2 ^-i・〓 ₁
A signal 〓 ₂ proportional to Θ ² is obtained from the logical product sum.
By continuing similar operations, it is easy to obtain a signal proportional to the third power or higher power of Θ. By multiplying the signals obtained in this way from the 0th power to the 3rd power of Θ or higher-order powers by an appropriate coefficient, the X-cut crystal oscillator that is actually used can be
1 of each of the DT cut and AT cut crystal oscillators
It is possible to compensate for second-order, second-order, and third-order temperature coefficients. Naturally, it is also possible to compensate for temperature coefficients of orders lower than the highest order. Here, the above principle can be modified to simplify the system. In the above explanation, we purposely created 〓 ₁ proportional to Θ ¹ from the constant frequency signal _c , but there are cases where it is possible to use the x input as a signal corresponding to 〓 ₁ . The temperature sensor is operated intermittently, e.g.
In a system in which the temperature detector is operated only at the high level of the REF signal, the data measured during this period is held in a counter, and a temperature correction signal is generated based on this held data.
The temperature signal corresponding to the x input is input only intermittently, and a function generation mechanism is prepared to generate 〓 ₁ from _c . If the sub-oscillator for voltage conversion is always operated as in the embodiment of the present application, and the difference signal between this signal and a signal with a constant frequency is a temperature difference signal and can be obtained continuously, instead of 〓 ₁ . The x signal can be used to simplify the system configuration. 6th
Figure B is an example of a simplified system as described above.

In FIG. 6B, REF is a constant frequency signal that serves as a reference for period measurement, and is a relatively low frequency signal obtained by dividing the crystal oscillator output signal. 114) or a holding mechanism (FIG. 1 115).
x is a temperature difference signal, created by data type flip-flop 613 in FIG. 6A. C is a clock signal, and any signal with a higher frequency than x may be used, but the output signal of DIV612 and DIV61
Since it is necessary to shift the phase of the output signal of No. 5, it is necessary to select different phase signals for that purpose.

In the explanation of FIGS. 6A, B, and C, all toggle type flip-flops (hereinafter abbreviated as T-FF) have a falling trigger, and all latches (hereinafter abbreviated as L-FF) have a falling trigger.
(abbreviated as FF) reads data when the clock signal is at high level and holds the data when it is at low level. It is also assumed that a data type flip-flop (hereinafter abbreviated as D-FF) holds the data value at the moment of falling of the clock signal.

In Fig. 6B, 631 is a digital delay circuit whose output changes in synchronization with the rise of C, and the signal ↑ synchronized with the rise of REF with the delay time width.
is created using gate 632. 633 is a counter (N(Q ₁ i)) that counts and holds the frequency of x input.
Here, Q ₁₀ to Q ₁₆ represent weights of 2 ⁰ to 2 ⁶ . 634 is a D-FF circuit for synchronizing the x input signal into a signal synchronized with the rise of C, and 635 is a D-FF for creating a delayed waveform for differentiation. Frequency measurement/
The holding counter 633 includes a flip-flop 6
A counting signal Cp=x ^* Q _REF located at the high level of the REF signal is created from the signal ^* synchronized in 34 and the output of the digital delay circuit 631,
A counter 633 counts. Gate 637 receives the output signals x ^* , x ^** of flip-flops 634 and 635.
signal synchronized to the rising edge of x ^* using the delay of
Create x ^* ↑. The high level pulse width of x ^* ↑ is equal to the synchronization of the C input signal and is synchronized with the fall of the C input, that is, the rise of the output of the oscillator 611 in FIG. 6A. 638 is a cascaded T-FF to divide x ^* ↑ to obtain a low frequency signal
The change in the output of each Q ₁₀ to _{Q 16} is synchronized with the falling edge of x ^* ↑.

639 is a special notation to make it easier to see the logical product sum, and if the output of the 640 gate is y, then y=Q ₁₆・Q ₀₁・x ^* ↑ +Q ₁₅・₀₁・Q ₀₂・x ^* ↑ +Q ₁₄・₀₁・₀₂・Q ₀₃・x ^* ↑ ＋Q ₁₃・₀₁・₀₂・₀₃・Q ₀₄・x ^* ↑ ＋Q ₁₂・₀₁・₀₂・₀₃・₀₄・Q ₀₅・x ^* ↑ ＋Q ₁₁・₀₁・₀₂・₀₃・₀₄・₀₅・Q ₀₆・x ^*
↑ +Q ₁₀・₀₁・₀₂・₀₃・₀₄・₀₅・₀₆・
x ^* ↑. If we re-express this using the signal Ci mentioned above, the right side of the above becomes: Right side = Q ₁₆・C ₁ +Q ₁₅・C ₂ +Q ₁₄・C ₃ +Q ₁₃・C ₄ +Q ₁₂・C ₅ +Q ₁₁・C ₆ +Q ₁₀・C ₇ . Set the symbol ( ) that gives the frequency,
Assuming that (A) represents the frequency of A, (C ₁ ) = 2 ⁶ · (x ^* ) · 2 ^-7 (C ₂ ) = 2 ⁵ · (x ^* ) · 2 ^-7 (C ₃ ) = 2 ⁴・(x ^* )・2 ^-7 (C ₄ )=2 ³・(x ^* )・2 ^-7 (C ₅ )=2 ²・(x ^* )・2 ^-7 (C ₆ )=2 ¹・(x ^* )・2 ^-7 , and (y)=2 ^-7・(x ² ) holds true. In FIG. 6B, special notation is used to make it easier to see the logical product sum. For example, it is represented using a matrix 639 and a gate 640.

The reason for using the AND-OR gate is to add the frequencies of the weighted signals of 2 ^-7 (C) to ^{2 -1} (C) corresponding to Q ₁₀ to Q ₁₆ using a logic gate such as OR gate 640. This is because, in order to make this possible, the sum of all the logical products of the arbitrary combinations of the weighted signals must always be at a low level. When using an AND gate, you can use negative logic and consider exactly the same thing. EXCLUSIVE-OR
When the gate is used for frequency addition, it is only necessary that the weight signals have different waveform changes. FIG. 6C is a timing chart showing the timing of measuring and holding temperature data in FIG. 6B. The horizontal axis represents time, and the vertical axis represents a high level upward. The REF input signal is delayed and inverted to become the Q _REF signal, and a reset signal consisting of the REF signal and the _REF signal is created. is the rising edge signal of the REF signal, which is the inverted signal of REF↑ itself.
P is _{the REF} signal itself, and counts at the low level of P, and holds data at the high level of P. Cp is a signal for counting temperature data. In the state from t ₂ to _{t 3} when data is stored in Q ₁₀ to _{Q 16} , a signal proportional to x ² is obtained by the mechanism already described, and the system shown in FIG. 6 operates.

FIG. 7 shows an embodiment of the level conversion circuit. Input signal A700 of inverter 701 is level-converted and becomes output signal A'720. Inverter 7
01 is low voltage operation, and input signal 700 and output signal 702 are complementary signals such that both logic levels are V _DD and V _SS1 .

FET711, 712, 714, 715 and
FET721, 722, 724, 725 are V _DD and
It constitutes a NAND gate that uses V _SS2 as the output level of the logic circuit, and two sets of NAND gates cross each other to form a positive feedback loop, making it a bistable flip-flop. 702 signal A
The complementary signals of the signals 700 and 700 are input signals for setting the state of the bistable flip-flop circuit. If A=L, P-CH-FET7
11 is ON, N-CH-FET721 is OFF
or enter a high impedance state. Since =H at the same time, P-CH-FET715 is
It becomes OFF, and N-CH-FET725 becomes ON.
In this state, the output signal 720 rapidly approaches the high level V _DD due to the action of the positive feedback loop, and P-
CH-FET712 is ON, 714 is OFF,
N-CH-FET 722 turns OFF, 724 turns ON and becomes stable. In a stable state, A and A' are in an inverted relationship, but if the output signals are taken out from the drains of FETs 714 and 715, it is clear that a signal that is not in an inverted relationship and differs only in logic level can be obtained. When configuring the level conversion circuit shown in FIG. 7, the mutual conductance of the N-CH-FET is set to a small value, the mutual conductance of the P-CH-FET is set to a large value, and the N-CH-FET shown in 721 or 726 is configured. At the gate of FET (V _SS1 −V _SS2 )
The impedance when a voltage of 7 is applied is 7.
_{FET7 _}
Care must be taken that the value of the flip-flop can be set by 11 or 715. When integrating the circuit, the channel widths of FETs 711 and 715 may be increased, and the channel lengths of FETs 721 and 725 may be increased.

FIG. 8 shows an example of an electronic timepiece equipped with two types of mechanisms: voltage reduction by a voltage conversion circuit and voltage boosting by a booster circuit according to the present invention. 800 is a sub-oscillator for voltage conversion, which can be thought of as a ring oscillator as already shown in FIGS. 2 and 3, or if the purpose is simply to convert voltage for display driving,
A signal obtained from a time reference signal source or a frequency-divided signal of the signal may be used, or a completely separate crystal resonator may be prepared and oscillated. Inverters 801 and 802 are used for waveform shaping.
At the same time, it is also an inverter for power supply that drives the boost mechanism. 803 and 804 are voltage dividing capacitors, and it is preferable that their capacitance values are equal. 805 is a capacitor for holding the boosted voltage. 811 is a diode for clamping, 8
21 is a capacitor for clamping. When =H, the diode 811 is forward biased, the output terminal of the inverter 802 of the capacitor 821 is charged positively, and the opposite electrode is charged negatively, and when =L, the diode 811 is reverse biased.
OFF state, and the positively charged side electrode of the capacitor 811, that is, the side electrode connected to the output terminal of the inverter 802, is set to the low level and the potential of V _SS1 , so the negative potential side electrode of the capacitor 821 In other words, the potential at point 821 is V _SS1
The potential will be lower by (V _DD − V _SS1 ) than that. In the end, the high level of the output signal of the inverter 802 is V _SS1 due to the diode 811 and the capacitor 821.
It is clamped to the potential of Transistor 816 is an N-CH-FET whose substrate and source are connected and connected to V _DD by capacitor 805.
is connected to transistor 816.
The transistor 816 can be replaced with a diode in which the current flows in the forward direction from the source side to the drain side in the OFF state.
In this case, diode 811 and capacitor 8
It can be thought of as a circuit that further rectifies a signal that is clamped by setting the potential of V _SS1 to a high level by a diode 816 and stores an electric charge in a capacitor 805. Here, if the output impedance of the inverter 802 is a sufficiently low value,
Assuming that the impedance is much lower than the impedance in the ON state of FETs 812 and 816, the above-mentioned clamping effect is reliably performed, and the high level of the clamp output terminal 823 is approximately the level of V _SS , and the low level is approximately 2. We can guarantee that it will be at the level of V _SS1 . The reason I use the expression "approximately" here is because if the diode causes a forward voltage drop, the clamp level will be closer to _VDD than _VSS1 . The potential of the rectified output terminal 825 is approximately 2.
When the value of V _SS1 is, the inverter consisting of FETs 814 and 818 performs an inverter operation with the potential of V _SS1 and V _SS1 × 2 as the power supply level, and when the level of 823 is V _SS1 , the level of 824 is 2・V _SS1 Then, by turning FET812 ON and FET816 OFF, the forward voltage drop of diode 811 is equivalently eliminated, and when the level of 823 becomes 2.V _SS1 , the level of 824 becomes V _SS1 , and FET 816 is turned off.
Turn ON to eliminate the forward voltage drop of 816 as a diode. After all, according to this embodiment, the forward voltage drop component in the diode clamp circuit can be effectively removed, and a highly efficient boosting mechanism can be realized. For example capacitors 821 and 805
is 0.5μF, and the frequency of the signal φ is 256Hz,
FET812 is HD1G1030, diode 811 and 816 (this also works as FET)
When configured with 3N169, it showed a power conversion efficiency of 98% at a power supply voltage of 1.6 volts with a load of 1 MΩ. When the diode 811 is made of 3N169, the gate, substrate, and source are coupled, and the diode is used between the drain and the substrate. This configuration can be used as a C/MOS-IC.
Capacitor 822 and diode 813 are used when this configuration is operated in push-pull mode. As a modification of this configuration, a system in which capacitor 805 is removed and a capacitor 822 and diode 813 are used, and a system in which diode 813 and capacitor 822 are removed are used. The boost system 831 has exactly the same principle as above, except that the clamp level V _SS1 explained above is changed to the voltage converter circuit.
The only change was to clamp it to the level of V _SS1/2 output (1/2)/V _SS1 . In this case, (1/
2) → Since the potential shifted by V _SS1 from V _SS1 (3/2)·V _SS1 is obtained, this is expressed as V _SS3/2 . By combining the above circuits, V _DD (=
0volt) and V _SS1 potential, 1/2, 3/2, 2 times V _SS1
Three types of voltages are obtained, and when considering V _SS1 as a reference, a potential that is shifted by 1/2 V _SS1 in the positive and negative directions from V _SS1 and a potential that is shifted by exactly V _SS1 in the positive and negative directions are obtained, and the liquid crystal display panel is 1/3 Dynamic matrix can be driven using voltage application method. The meaning of the 1/3 voltage application method is that the ratio of the voltage applied to a matrix point selected to be turned on and the applied voltage to a point on the matrix selected not to be turned on is 3:1. 841 is a crystal oscillator that serves as a time reference source for watches, and has a frequency of ²¹⁵ Hz to ²²² Hz. Reference numeral 842 designates a clock unit signal synthesis mechanism consisting of a frequency divider, 843 a level conversion circuit, 844 a clock mechanism, 845 a display drive circuit, and 846 a display mechanism.

The feature of this configuration is that information is processed using the low voltage obtained by the voltage reduction circuit, and sufficient energy is supplied only to the components that essentially require energy at the most suitable voltage. In particular, matrix drive uses threshold values to reliably address and drive low-voltage liquid crystal display elements, drive low-voltage electromism display elements, and apply high voltage to FETs in pulse motor drive circuits that require large currents. It is possible to reduce the size of the drive FET, which accounts for a large proportion of the IC chip size, by applying voltage, and in particular, the divided voltage conversion that can be expressed as an arbitrary fraction in this application is effective in matching the battery voltage and the element. . Furthermore, as shown in the embodiments of this application, a low-current ring oscillator built inside an IC, an oscillation and waveform shaping circuit with low through-current, etc. play an important role in integrating the entire system.

Figure 9A shows m rows and n columns of liquid crystal (m and n are natural numbers)
This is a schematic diagram for driving a matrix, in which, for example, m rows of upper electrodes and n columns of lower electrodes are formed on the surfaces of the upper electrode glass and the lower electrode glass, respectively, and the electrode lines are opposed to form a narrow It is sufficient to consider a structure in which the electrodes are stacked with insulating spacers in between, and a field-effect liquid crystal is sealed between the opposing electrodes. The explanation will be made regarding lighting and non-lighting of the specified segment Sij in the i-th row and j-th column (i and j are arbitrary natural numbers) in FIG. 9A. When the Sij is not lit, a voltage below the threshold is applied to the Sij portion 901, and when the Sij is lit, a voltage above the threshold is applied for a short period of time, thereby allowing accurate addressing of the display segment. . In addition to this, to achieve matrix driving, a liquid crystal with fast rise characteristics that lights up with a short drive pulse, and a liquid crystal with a long frame memory time that memorizes the lighting state during the period of the drive pulse, or a liquid crystal with slow fall characteristics. However, it is assumed here that the above requirements are satisfied by the selection of the liquid crystal cell structure and liquid crystal material.

φd ₁ to φd _n in FIG. 9B are for applying potentials to electrode lines specifying rows. The potential φs _j specifying the column is obtained by selecting φs and s in FIG. 9B. FIG. 9C shows a specific circuit configuration. φs in FIG. 9 specifies the off state. To light only the segment of Si _j , φs is specified only at the high level of φd _i , and when φd _i is at the low level, φs
It is sufficient to set φs _j so that φs j+ is specified so that s is specified only at the high level of φd _i , and φs is specified only at the low level of φd _i , so that only the Si j _{+ 1} segment is lit. It is sufficient to set ₁ . E in Figure 9B
This signal is used to form a short circuit that does not go through the power supply circuit when applying an alternating voltage to the liquid crystal segment, and has the effect of reducing power consumption when driving capacitive display elements in general. The voltage applied to the liquid crystal element when it is not lit is expressed as (φd _i -φs), and the voltage applied to the liquid crystal element that becomes a lighting segment is expressed as (φd _i -s), as shown in FIG. 9B. is shown. As is clear from the waveform (φd _i -φs), when the lamp is lit, a voltage three times as high as when the lamp is not lit is applied for a short time.

In Figure 9C, φs _j is a signal that sets V _SS1/2 to a high level, V _SS1 to a midpoint level, and V _SS3/2 to a low level, and is set to the midpoint level at the high level of E. In the other low level state of E, the voltage level changes between V _SS1/2 and V _SS3/2 with a phase equal to φ at the high level of Sj, and this becomes a low level state of Sj. Changes to signals of equal phase. φd _i is a signal that sets V _DD to a high level and V _SS2 to a low level; when E or i is at a high level, it is set to the midpoint level V _SS1 , and when i is at a low level, it becomes a signal that matches φ. In Figure 9C,
Signal E931, 933, Di932, i93
4, φ935 and 936 can be considered to be signals whose high logic levels are V _DD and V _SS2 .
When the circuit shown in Figure 9C is effective, the relationship between the threshold voltage V _TLC of the liquid crystal element and the power supply voltage is {(1/2)・(V _DD −V _SS1 )<V _TLC (3/2)・(V _DD −V _SS1 ) > V _TLC }, and depending on the value of V _TLC , V _SS1/2 ,
The voltage ratio of V _SS1 , V _SS3/2 , and V _SS2 remains constant, and the coefficients of the voltage conversion circuit are changed so as to satisfy the above relation, for example, 1/3, 2/3, 3/3, 4 of the power supply voltage. Try to create a voltage of /3. There is no need to actually create 3/3 voltage, and the battery voltage can be used as is. Since some currently available liquid crystals have a Vnc of about 1.1 volts, the circuit shown in FIG. In this case, it is reasonable to use a system in which information is processed at a low voltage, and the display drive signal, for example, φ is a level-converted high voltage.

FIGS. 10A and 10B show the relationship between the applied voltage and the internal state of a PLZT (lanthanum lead zirconate titanate) or electrochromic display element. In Fig. 10A, the driving method differs depending on whether the lighting state is set to point B' and the non-lighting state is set to point O or Q = 0, or whether the lighting state is set to B' and the non-lighting state is set to E'. It's coming. When Q is the amount of polarization, PLZT can be used to turn on point B' and turn off points H' to D', and to turn it on by applying a voltage of OA' or higher, to turn on H' and D'. It can be used to turn off the light by applying a reverse voltage between the two. A similar driving method can be used in an electrochromic element, where Q is the amount of electrochemically deposited substance (deposited on the top surface is defined as positive, and deposition on the back surface is defined as negative).
In the case of a PLZT, electrochromism, or elastomer display element that exhibits properties as shown in Figure 10B, it is necessary to control the charge integral value so that it stops at position A (depending on how it is used) even when the light is not lit, or to create a minor loop. It is necessary to use a method that allows you to draw and stop at the 0 point. If it can be clearly identified as a display element at points B and E, apply a sufficient positive voltage and set it to point B to turn it on, and apply a sufficient reverse voltage and set it to point E to turn it off. I can use it.
FIGS. 10C and 10E show examples of driving circuits for a PLZT or electrochromic element as a display element having the properties shown in FIG. 10A. The drive circuit can often be used for display elements having properties as shown in FIG. 10B. FIG. 10C shows the display signal Sk
On the other hand, when Sk rises, Sk rises in accordance with the high level of φ and falls at the low level of φ.
This is an embodiment of a circuit that creates a rising differential signal S ^ON _k and a Sk falling signal S ^OFF _k that rises in synchronization with the falling of φ when Sk falls and falls at the high level of φ. S ^ON _k is a signal for turning on the display element, and S ^OFF _k is a signal for turning off the display element, the waveforms of which are shown in FIG. 10E.
FIG. 10D is an example of a driving circuit, in which the block 1002 is equivalent to the block 1001 in FIG. 10C. 1003 and 1005 are P-CH-FETs, and when the transistor 1003 is turned on at the high level of S ^ON _k , the output potential of φsk is V _DD
When S ^OFF _k is at a high level, transistor 1005 is turned on and the potential of φsk becomes equal to V _SS1/4 . S ^ON _k and S ^OFF _k will never be at high level at the same time. When both S ^ON _k and S ^OFF _k are at low level, transistors 1003 and 1005 are both
OFF, the voltage applied to the display element 1006 attenuates to 0 with a time constant determined by the leakage resistance and capacitance of the element, or maintains the previously applied voltage. A signal φ _COM having a phase and waveform synchronized with φ and differing only in voltage level is obtained from the inverter 1004, and is connected to the display element 1006 as a common electrode potential. In the end, the display element 1006
Voltage applied to a certain segment of V _EC-k
As shown in Figure 10E, if a positive voltage for lighting is applied at the rising edge of Sk, a reverse voltage for turning off at 1/1/2 of the lighting voltage is applied at the falling edge of _Sk .
2 voltages will be applied.

FIG. 11A shows in detail the drive circuit portion of the pulse motor type quartz watch. 1101 is a timekeeping mechanism that operates at low voltage and has functions including crystal oscillation, frequency division, and waveform shaping. Reference numeral 1102 denotes a level conversion circuit, and in this embodiment, V _SS2 is prepared in which the voltage level on the negative potential side is expanded to a lower potential. V _SS1 is the negative potential side level of the battery, and V _SS2 is 2
The boosted output is doubled, and V _SS2 =2·V _SS1 . or
V _SS1/4 is V _SS1/4 = 1/4 V _SS1 . 1103 and 1104 have large current capacity for driving pulse motors.
It is a FET inverter. P-CH-FET1111
and 1113 has V _SS1 when the input signal is low level.
Since it turns on by applying twice the gate voltage, compared to a normal system without a booster circuit.
The ON impedance can be reduced to 1/4, or the area ratio of the chip size used inside the IC for the drive inverter can be reduced. N-CH-FET111
There is no effect of reducing ON impedance for 2 and 1114, but gate input 11 in OFF state
A complete OFF state is realized because the low level of 06 and 1108 is lower than the source potential.
Leakage current in the circuit is reduced. The low voltage operation of the timekeeping mechanism 1101 and the reduction in output impedance or leakage from the driving inverter, which accounts for the largest amount of leakage current, have a great effect. In order to reduce the impedance of the N-CH-FET, input signals 1105 and 1106 are cut off using capacitors, and 110
Clamp the low level of 6 to the level of V _SS1 ,
105 may be directly connected to the level converter circuit 1102, and the input 1106 may be connected to the level converter 1102 via the above-mentioned capacitor. The same goes for inputs 1107 and 1108.
P-CH-FET input 1107 is directly driven, N-
CH-FET input 1107 is directly driven, N-CH-
FET input 1108 may be diode clamped and coupled to input 1104 through a capacitor. A power supply V _DD2 twice as high as V _DD is added on the positive potential side, and the signal is expanded to logic levels V _DD2 and V _SS2 by a level converter, and the inverters 1103 and 1104 are
may be driven.

FIG. 11B is a waveform diagram of the signal in FIG. 11A, and FIG. 11C is a waveform diagram of the signal in FIG. 6B. φ ₆₃₇ is the output signal of the gate 637, Q ₀₁ ...Q ₀₆ is the output signal of the counter 638,
φ ₆₃₇ C ₁ ... φ ₆₃₇ C ₄ is the counter 638 and gate 63
It is determined from the output of 7.

Here, C ₁ = Q ₀₁ , C ₂ = ₀₁・Q ₀₂ C ₃ = ₀₁・₀₂・Q ₀₃ C ₄ = ₀₁・₀₂・₀₃・Q ₀₄ .

[Brief explanation of drawings]

FIG. 1 is a block diagram of a timepiece system of the present invention using a voltage conversion circuit, FIG. 2 is an embodiment of the voltage conversion circuit, and FIGS. 3A and B are another embodiment of the voltage conversion circuit of the present invention. 4A and 4B are explanatory diagrams of the operation of the voltage conversion circuit of the present invention, FIG. 5 is another embodiment of the voltage conversion circuit of the present invention, and FIG. 6A is a combination system of the voltage conversion circuit and temperature compensation circuit of the present invention. The block diagram, FIG. 6B, is an embodiment of the squaring multiplier circuit in FIG. 6A.
Figure C is an explanatory diagram of the system operation of Figure 6A, Figure 7 is an example of a level conversion circuit, Figure 8 is an example of a combination of voltage reduction and boosting, and Figure 9A is the voltage conversion of Figure 8. FIG. 9B is a matrix drive waveform diagram, FIG. 9C is an example of a matrix drive circuit, the first
Figures 0A and B are characteristic diagrams of storage type display elements, Figures 10C and D are examples of storage type display element drive circuits, and Figure 11.
Figure A is an example of a pulse motor crystal clock system circuit using the voltage conversion shown in Figure 8, Figure 10E is a storage type display element drive waveform diagram, Figure 11B is a drive waveform diagram of a motor drive circuit, and Figure 11B is a drive waveform diagram of a motor drive circuit. Figure C is a signal waveform diagram of Figure 6B. 111: Oscillator as second signal generating means, 1
12: Switching circuit for switching the connection of the capacitor, 116: Level converter, 117: Display mechanism,
118: Electrical energy source.

Claims (1)

[Claims] 1. An electronic timepiece comprising a time reference signal source, a timekeeping unit signal synthesis mechanism, a timekeeping mechanism, a time display mechanism, an external operating member, and an electrical energy supply source, wherein the time reference signal source is a crystal oscillator, A temperature-sensitive sub-oscillator integrated into an integrated circuit is provided, the frequency difference between the crystal oscillator frequency and the oscillation frequency of the sub-oscillator is counted as a temperature-dependent temperature difference signal, and a temperature compensation function is calculated from the temperature difference signal. An electronic timepiece comprising an arithmetic circuit that compensates for temperature fluctuations in the oscillation frequency of the time reference signal source crystal oscillator. 2. The electronic timepiece according to claim 1, wherein the arithmetic circuit intermittently counts and stores the temperature difference signal and continuously generates a temperature compensation function based on the stored temperature difference signal. .