JPS6367202B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital servo device that controls the rotation system of a magnetic recording and reproducing device.

Generally, magnetic recording and reproducing devices such as VTRs are provided with automatic frequency control means, automatic phase control means, etc. in order to smoothly and stably rotate a rotating system such as an electric motor. Servo devices that control the rotation system of magnetic recording and reproducing devices, including these means, are increasingly becoming digital, and digital quantities such as pulse width modulation signals are used for control output.

The present inventors previously filed an application for a digital servo device as shown in FIG. 1 in Japanese Patent Application No. 155898/1982. In FIG. 1, 1 is a controlled object such as a rotating body, 2 is a waveform shaping circuit, 3 is a gate signal generator, 4 is an AND gate, 5 is a detection counter, 6 is a latch circuit, 7 is a pulse width modulation circuit, 8 11 is a reference counter, 11 is a low-pass filter, and 12 is a drive circuit.

Next, the operation of the conventional device having the above configuration will be described in the first section.
This will be explained with reference to FIG. 2, which shows the waveforms of the main parts of the figure. First, the controlled signal a obtained from the controlled object 1
passes through the waveform shaping circuit 2 and is input to the gate signal generator 3 as a comparison signal b. The gate signal generator 3 detects the phase difference between the reference phase signal c as shown in FIG. 2 and the comparison signal b as shown in FIG. 3) is output.

This clock gate signal d is applied to the AND gate 4.
The clock signal e input to the detection counter 5 is gated. As a result, the detection counter 5 detects the clock signal e corresponding to the pulse width of the clock gate signal d, as shown in FIG.
Count. Immediately after the clock gate signal d becomes low level and the AND gate 4 closes, the count information of the detection counter 5 is transferred to the latch circuit 6 and held by the latch pulse f shown in FIG. 5. Here, the information held in the latch circuit 6 is input to the pulse width modulation circuit 7 together with the information of the reference counter 8. Pulse width modulation circuit 7
Now, as shown in FIG. 6, a pulse width modulation signal (hereinafter abbreviated as PWM signal) which has a pulse width corresponding to the information of the latch circuit 6 and is a periodic signal of bit Q _o of the reference counter 8 is generated. Output g. This PWM signal g is input to the drive circuit 12 via the next-stage low-pass filter 11, and controls and drives the controlled object 1.

Here, the operation when the phase of the controlled object 1 is different from a predetermined phase will be explained. As shown in A in Figure 2, when comparison signal b is at a predetermined phase with respect to reference phase signal c, the duty of PWM signal g is
It is set to 50%. For example, suppose that the load suddenly increases and the phase of the controlled object 1, that is, the phase of the comparison signal b, advances as shown in FIG. At this time, the gate width of the clock gate signal d becomes small as shown in FIG.
The number of clocks input to the circuit will be smaller. Therefore, the count of the detection counter 5 becomes less than the predetermined value, and the information held in the latch circuit 6 also becomes smaller than the predetermined count value. Therefore, the PWM signal g which is the output of the pulse width modulation circuit 7 becomes a signal with a small duty, like the signal g in state B in FIG.

Therefore, the DC voltage output from the low-pass filter 11 becomes lower than a predetermined value, and the phase of the controlled object 1 is delayed.

Similarly, if the phase of the controlled object 1 lags behind the predetermined phase, the operations of the above-mentioned parts will be in the opposite direction. As a result, the duty of the PWM signal g increases, and the phase of the controlled object 1 is advanced.

Here, the configuration and operation of the pulse width modulation circuit 7 will be explained. Figure 3 shows the main waveforms. The information of the latch circuit 6 that latches the count value of the detection counter ₅ and the information of the reference counter 8 as shown in FIG _. A group of exclusive OR gates (hereinafter referred to as Ex-OR group) 9 or a similar detection circuit is used for comparison. These Ex-OR group 9
All outputs are input to a NOR gate 10, and the output thereof is further input to a reset terminal R of a T-type flip-flop (hereinafter abbreviated as T-FF) 13 as a coincidence signal h shown in FIG. on the other hand,
The signal of bit Q _o of the reference counter 8 is input to the T input signal i of the T-FF 13 . Therefore, the T input signal i has a constant period determined by the reference counter 8.

In the above configuration, the output of the T-FF 13, that is, the PWM signal g, is the output of the reference counter 8.
Qo, that _is , inverted to "H" at the falling edge of signal i, and becomes "L" at match signal h from NOR gate 10.
become.

As described above, the pulse width modulation circuit 7 compares the information of the latch circuit 6 with each bit output of the reference counter 8, and outputs a pulse with a pulse width according to the latch information and with a period determined by the bit Q _o of the reference counter 8. PWM signal g is output.

In the digital servo device having the pulse width modulation circuit 7 as described above, T-FF is
The phase relationship between the coincidence signal h input to 13 and the T input signal i is as shown in FIGS. 2 and 3. In other words,
The matching signal h and the falling edge of the T input signal i do not overlap.

However, if the load becomes large during start-up or transient situations of the digital servo device, PWM
As shown in FIG. 4, the signal g is an output with a large number of "H" portions and a small amount of "L" portions. At this time, if the delay amount of the Ex-OR group 9 or the NOR gate 10 is large, the coincidence signal h' may be delayed and overlap with the falling edge of the T input signal i, as shown in FIG. .

When this happens, the T-FF13 outputs the signal i.
The output signal g' is always "L" without being inverted. In other words, the signal g', which should be "H", becomes "L" and malfunctions.

If such a malfunction occurs, not only will the pull-in characteristics of the digital servo device deteriorate;
The drawback was that the control characteristics during transient conditions were significantly affected.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above and provide a digital servo device that operates stably without malfunctions.

In the present invention, a pulse width modulation circuit, which is one component of a digital servo circuit, is constituted by means for generating a coincidence output signal, a flip-flop, and a latch circuit consisting of several gates. The feature is that the inversion of the signal is reliably performed to prevent malfunctions due to delays in the coincidence output signal.

An embodiment of the present invention will be described below with reference to FIG. Note that the main waveforms of FIG. 5 are shown in FIG. 6.

In FIG. 5, 15 and 18 are inversion gates, 1
Reference numerals 6 and 17 indicate NAND gates, and other symbols are the same as those in FIG. 1 or have the same functions. Although only the pulse width modulation circuit 7 is detailed in FIG. 5, circuits similar to those in FIG. 1 are provided around it, and the description of this circuit is omitted.

In a device having such a configuration, the latch circuit 6
A coincidence signal h obtained by comparing the information of 1 and each bit of the reference counter 8 is inputted to a latch circuit composed of NAND gates 16 and 17 through an inverting gate 15. Now, when the coincidence signal h shown in FIG. 62 outputs a coincidence output "H",
The output signal k of the NAND gate 16 becomes "H" as shown in FIG. 3, and at the same time the PWM signal g via the inverting gate 18 becomes "L" as shown in FIG. The signal j also becomes "L" as shown in FIG. At this time, T-FF1
9 is canceled.

After that, the signal i is input to the trigger input T of T-FF19.
When the falling edge of is input, its negative phase output becomes "L". As a result, the signal j is “H” and the signal k
is “L” and the signal g is “H”. Thereafter, when the coincidence signal h becomes "H" again, each signal is inverted and the PWM signal g is output in accordance with the latch information.

Now, at startup or during a transition, the signals i, h, and g have the phase relationships shown in Figure 4 1, 2, and 3, and the PWM signal g has a long "H" level time and an "L" level time. Suppose it becomes shorter. At this time, consider a case where the match signal h is in a state like h' in FIG. 6 due to gate delay or the like, that is, the falling edge of the signal i and the "H" level of the match signal h' overlap.

Now, if the coincidence signal h' becomes "H",
The output signal k' of the NAND gate 16, the output signal j' of the NAND gate 17, and the PWM signal g' are as shown in FIG. 6, 7, 8, and 9, respectively.
Inverted to “H”, “L”, “L”. At this time, T-FF
Since the reset signal No. 19 is released at the same time as the signal g' is inverted, even at the falling edge of the trigger signal i immediately after, the reverse phase of the T-FF 19 is changed as shown in FIG. 10. Flip to “L”,
As a result, the signal j' becomes "H". At this time,
Since the signal h' is still delayed and is at "H", the signal k' remains at "H" and the signal g' remains at "L". After a while, when the signal h′ falls, the signal
k' is "L", signal g' is inverted again to "H", and PWM
The signal g' becomes a predetermined signal whose majority is "H". At this time, the output of the T-FF 19 becomes "H" and enters the reset state again.

In other words, by adopting the configuration of this embodiment, even if the coincidence signal h is delayed for some reason with respect to the trigger signal i, the predetermined value can be maintained without malfunctioning.
PWM signal g can be obtained.

Note that in the above embodiment, the PWM signal g
Although the example has been explained in which the PWM signal g is connected to the reset input terminal, it is of course possible to design the circuit so that this PWM signal g is connected to the set input terminal of the T-FF 19.

As described above, according to the present invention, when the phase difference between the comparison signal and the reference signal becomes large, even if the coincidence signal is delayed with respect to the T input signal of the T-FF that generates the PWM signal. , a desired PWM signal can be obtained without malfunction, and a stable digital servo device can be provided with a slight increase in elements.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a digital servo device according to the prior art, FIGS. 2, 3, and 4 are waveform diagrams of essential parts for explaining the operation of FIG. 1, and FIG. 5 is a block diagram of a digital servo device according to the present invention. A circuit diagram showing an embodiment, FIG. 6 is a waveform diagram of the main part of FIG. 5. 5...Detection counter, 6...Latch circuit, 7...
...Pulse width modulation circuit, 8...Reference counter, 10
...NOR gate, 19...T-type flip-flop.

Claims (1)

[Claims] 1. A reference signal generation circuit consisting of a counter means for counting clock pulses and operating at a scheduled cycle, and a digital detector outputting a digital signal according to the error from the target value of the controlled object at a cycle longer than the above cycle. , a pulse width modulation circuit that digitally compares the output signal of the digital detector with the reference signal and outputs a signal with a pulse width commensurate with the information of the digital detector output signal and with the predetermined period. In the digital servo device configured, the pulse width modulation circuit includes means for digitally comparing the digital detector output signal and the reference signal to generate a coincidence signal, and a constant count value of the counter means. and a flip-flop to which the signal output from the reference signal generation circuit is input at the trigger terminal at the scheduled period, and a latch circuit to which the output signal of the flip-flop and the coincidence signal are input, and the output of the latch circuit is is connected to the reset or set input terminal of the flip-flop, and the match signal is connected to the input terminal at which the output of the latch circuit is determined preferentially when signals are simultaneously applied to two input terminals of the latch circuit. A digital servo device characterized by: