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JPS6367333B2 - - Google Patents
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JPS6367333B2 - - Google Patents

Info

Publication number
JPS6367333B2
JPS6367333B2 JP57210264A JP21026482A JPS6367333B2 JP S6367333 B2 JPS6367333 B2 JP S6367333B2 JP 57210264 A JP57210264 A JP 57210264A JP 21026482 A JP21026482 A JP 21026482A JP S6367333 B2 JPS6367333 B2 JP S6367333B2
Authority
JP
Japan
Prior art keywords
film
tantalum oxide
oxide film
capacitor
tantalum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57210264A
Other languages
Japanese (ja)
Other versions
JPS5999726A (en
Inventor
Shinichi Inoe
Mamoru Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57210264A priority Critical patent/JPS5999726A/en
Publication of JPS5999726A publication Critical patent/JPS5999726A/en
Publication of JPS6367333B2 publication Critical patent/JPS6367333B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は半導体装置の製造方法のうち、酸化タ
ンタル(Ta2O5)からなる誘電体膜の形成方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method of forming a dielectric film made of tantalum oxide (Ta 2 O 5 ) among methods of manufacturing a semiconductor device.

(b) 従来技術と問題点 半導体集積回路(IC)は益々高密度化、高集
積化されてLSI、VLSIが開発製造されるように
なつてきた。従つて、ICを構成する素子も極め
て微細化されており、例えば一個のMOS型半導
体素子は10平方ミクロン程度の面積内に納められ
ている。
(b) Prior Art and Problems Semiconductor integrated circuits (ICs) are becoming increasingly dense and highly integrated, and LSIs and VLSIs are being developed and manufactured. Accordingly, the elements constituting the IC have also become extremely miniaturized; for example, one MOS type semiconductor element is housed within an area of about 10 square microns.

このような半導体集積回路において、特に半導
体記憶装置は高集積化されて64KRAMや
256KRAMが作成され、これらは一個のMOS型
半導体素子と一個のキヤパシタ(容量素子)とが
組合わされた単純な構造のメモリセルからなるも
のである。
In such semiconductor integrated circuits, semiconductor memory devices in particular have become highly integrated, such as 64KRAM and more.
256KRAM was created, and these are composed of memory cells with a simple structure in which one MOS type semiconductor element and one capacitor (capacitive element) are combined.

かようなメモリセルの断面図例を第1図に示し
ており、これはスタツク型1トランジスタメモリ
と呼ばれてMOS型半導体素子1上にキヤパシタ
2が積み重ねられた構造で、キヤパシタ2は誘電
体膜3を電極4,5の間に介在させた構造となつ
ている。また、その他の構造の1トランジスタメ
モリセルもこのような誘電体膜が必要なことは言
うまでもない。
An example of a cross-sectional view of such a memory cell is shown in FIG. 1. This is called a stacked one-transistor memory, and has a structure in which a capacitor 2 is stacked on a MOS semiconductor element 1, and the capacitor 2 is made of a dielectric material. It has a structure in which a membrane 3 is interposed between electrodes 4 and 5. It goes without saying that one-transistor memory cells of other structures also require such a dielectric film.

ところで、このような誘電体膜として、従来は
一般に二酸化シリコン(SiO2)膜を利用してお
り、時には窒化シリコン(Si3N4)も用いられて
いるが、上記のように全体が微細化されてくる
と、同一のキヤパシタンス(容量値)を保持する
ためには面積が小さくなる程その膜厚を薄くしな
ければならない。しかし、余り薄くなると絶縁性
を保つことが難しくなつて、その点から二酸化シ
リコン膜より誘電率(ε)の大きい酸化タンタル
膜が注目されている。即ち、誘電率が大きくなれ
ば膜厚を厚くしてもキヤパシタンスは変わらなく
なるからである。その酸化タンタル膜の誘電率は
二酸化シリコン膜が3.8、窒化シリコン膜が6に
対して、酸化タンタル膜は27と極めて大きいこと
が知られている。
By the way, in the past, silicon dioxide (SiO 2 ) films were generally used as such dielectric films, and sometimes silicon nitride (Si 3 N 4 ) was also used, but as mentioned above, the overall size has been miniaturized. In order to maintain the same capacitance (capacitance value), the smaller the area, the thinner the film must be. However, if the film becomes too thin, it becomes difficult to maintain insulation properties, and from this point of view, tantalum oxide films, which have a higher dielectric constant (ε) than silicon dioxide films, are attracting attention. That is, if the dielectric constant becomes large, the capacitance will not change even if the film thickness is increased. It is known that the dielectric constant of the tantalum oxide film is extremely large, at 27, while that of the silicon dioxide film is 3.8 and that of the silicon nitride film is 6.

しかしながら、酸化タンタル膜は二酸化シリコ
ン膜と比べて漏れ電流が多く絶縁性が悪いのが次
点で、未だ余り使用されていない状況にある。
However, compared to silicon dioxide films, tantalum oxide films have a higher leakage current and poor insulation properties, so they are still not widely used.

(c) 発明の目的 本発明はこのような酸化タンタル膜の絶縁性を
改善する形成方法を提案するものである。
(c) Object of the Invention The present invention proposes a method of forming such a tantalum oxide film to improve its insulation properties.

(d) 発明の構成 その目的は、基板上に形成した酸化タンタル膜
に、酸素分子イオンあるいは酸素原子イオンを注
入してアモルフアスな酸化タンタル膜とする工程
が含まれる製造方法によつて達成することができ
る。
(d) Structure of the invention The object is to be achieved by a manufacturing method that includes a step of implanting oxygen molecular ions or oxygen atomic ions into a tantalum oxide film formed on a substrate to form an amorphous tantalum oxide film. I can do it.

(e) 発明の実施例 以下、図面を参照して一実施例によつて詳しく
説明する。第2図ないし第3図は工程順断面図を
示しており、第2図は半導体基板10上に一部分
絶縁膜11を介して多結晶シリコン膜12(キヤ
パシタの一方の電極)を被着し、その上にスパツ
タ法または気相成長法で膜厚100〜200Åのタンタ
ル膜13を被着した図である。
(e) Embodiment of the invention Hereinafter, an embodiment will be described in detail with reference to the drawings. 2 and 3 show cross-sectional views in the order of steps, and FIG. 2 shows a polycrystalline silicon film 12 (one electrode of a capacitor) deposited on a semiconductor substrate 10 with a partial insulating film 11 interposed therebetween. This is a diagram in which a tantalum film 13 having a thickness of 100 to 200 Å is deposited thereon by a sputtering method or a vapor phase growth method.

次いで、第3図に示すように500〜600℃の酸化
気流中で処理してタンタル膜13を酸化タンタル
膜14に変える。また、第2図の工程を経ない
で、直接に膜厚200〜500Åの酸化タンタル膜14
を被着してもよい。それにはタンタル膜を酸素ガ
スを用いてリアクテイブスパツタすれば形成でき
る。
Next, as shown in FIG. 3, the tantalum film 13 is changed into a tantalum oxide film 14 by processing in an oxidizing gas flow at 500 to 600°C. In addition, the tantalum oxide film 14 with a thickness of 200 to 500 Å can be directly formed without going through the process shown in FIG.
may be coated with This can be formed by reactive sputtering of a tantalum film using oxygen gas.

次いで、第4図に示すように酸化タンタル膜1
4中に1〜20KeVの低加速エネルギーで酸素分
子イオン(O2 +)を注入する。注入量は1016
1018/cm2とし、低加速大電流型イオン注入装置を
使用して注入する。このようにして過剰の酸素を
注入すると、酸化タンタル(Ta2O5)結晶が破壊
されてもアモルフアスとなり、たとえ高温アニー
ルしても結晶化しにくい緻密な膜質がえられる。
且つ、絶縁度は二酸化シリコン膜に近くなつて著
しく向上する。これは、従来は未結合なタンタル
が存在して熱処理によつて結晶化し、それが絶縁
性低下の原因になつていたが、本発明ではそれが
なくなるものと考えられる。
Next, as shown in FIG. 4, a tantalum oxide film 1 is formed.
Oxygen molecule ions (O 2 + ) are injected into 4 at low acceleration energy of 1 to 20 KeV. The injection volume is 10 16 ~
10 18 /cm 2 , and implantation is performed using a low-acceleration, high-current ion implanter. When excessive oxygen is implanted in this manner, even if the tantalum oxide (Ta 2 O 5 ) crystal is destroyed, it becomes amorphous, and a dense film quality that is difficult to crystallize even during high-temperature annealing can be obtained.
In addition, the degree of insulation is significantly improved as it approaches that of a silicon dioxide film. This is because in the past, unbonded tantalum existed and crystallized during heat treatment, which caused a decrease in insulation properties, but it is thought that this problem can be eliminated in the present invention.

次いで、第5図に示すように他方の電極となる
多結晶シリコン膜15を被着してキヤパシタが完
成する。このようにすれば、誘電率のよい酸化タ
ンタル膜を誘電体にした絶縁性のよいキヤパシタ
を形成することができる。
Next, as shown in FIG. 5, a polycrystalline silicon film 15, which will become the other electrode, is deposited to complete the capacitor. In this way, it is possible to form a capacitor with good insulation using a tantalum oxide film with a good dielectric constant as a dielectric.

また、酸素分子イオン(O2 +)を注入する代わ
りに、酸素原子イオン(O+)を注入しても同様
である。更に、注入の加速エネルギーは酸化タン
タル膜の膜厚によつて変化させて、均一に注入す
ることが必要である。
Further, the same effect can be achieved even if oxygen atomic ions (O + ) are implanted instead of implanting oxygen molecular ions (O 2 + ). Further, it is necessary to uniformly implant the implant by changing the implant acceleration energy depending on the thickness of the tantalum oxide film.

(f) 発明の効果 以上の説明から判るように、本発明によれば誘
電率のよい酸化タンタル膜を誘電体にしたキヤパ
シタを用いることが可能になり、高密度化する
ICメモリの特性並びに信頼性の向上に役立つも
のである。
(f) Effects of the invention As can be seen from the above explanation, according to the present invention, it is possible to use a capacitor using a tantalum oxide film with a good dielectric constant as a dielectric material, and the density can be increased.
This is useful for improving the characteristics and reliability of IC memory.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は1トランジスタメモリセルの断面図
例、第2図ないし第5図は本発明にかかる一実施
例の形成工程順断面図である。 図中、1はMOS型半導体素子、2はキヤパシ
タ、3は誘電体膜、4,5は電極、10は半導体
基板、11は絶縁膜、12,15は多結晶シリコ
ン膜(電極)、13はタンタル膜、14は酸化タ
ンタル膜を示している。
FIG. 1 is an example of a cross-sectional view of a one-transistor memory cell, and FIGS. 2 to 5 are cross-sectional views of one embodiment of the present invention in the order of forming steps. In the figure, 1 is a MOS type semiconductor element, 2 is a capacitor, 3 is a dielectric film, 4 and 5 are electrodes, 10 is a semiconductor substrate, 11 is an insulating film, 12 and 15 are polycrystalline silicon films (electrodes), and 13 is a The tantalum film 14 indicates a tantalum oxide film.

Claims (1)

【特許請求の範囲】[Claims] 1 基板上に形成した酸化タンタル膜に、酸素分
子イオンあるいは酸素原子イオンを注入してアモ
ルフアスな酸化タンタル膜とする工程が含まれて
なることを特徴とする半導体装置の製造方法。
1. A method for manufacturing a semiconductor device, comprising the step of implanting oxygen molecular ions or oxygen atomic ions into a tantalum oxide film formed on a substrate to form an amorphous tantalum oxide film.
JP57210264A 1982-11-29 1982-11-29 Manufacture of semiconductor device Granted JPS5999726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57210264A JPS5999726A (en) 1982-11-29 1982-11-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57210264A JPS5999726A (en) 1982-11-29 1982-11-29 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5999726A JPS5999726A (en) 1984-06-08
JPS6367333B2 true JPS6367333B2 (en) 1988-12-26

Family

ID=16586502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57210264A Granted JPS5999726A (en) 1982-11-29 1982-11-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5999726A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7335570B1 (en) 1990-07-24 2008-02-26 Semiconductor Energy Laboratory Co., Ltd. Method of forming insulating films, capacitances, and semiconductor devices
DE69125323T2 (en) * 1990-07-24 1997-09-25 Semiconductor Energy Lab Methods of making insulating films, capacitors, and semiconductor devices

Also Published As

Publication number Publication date
JPS5999726A (en) 1984-06-08

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