JPS6367342B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing a semiconductor device using a two-dimensional electron gas generated at a selectively doped hetero interface.

(Prior art) In two types of semiconductors such as GaAs and GaAlAs, and InP and InGaAs, which have different forbidden band widths and can form a flat hetero interface, donor impurities are selectively added only to the one with the larger forbidden band width. , when a heterointerface is formed with the other side being a high-purity crystal, electrons from the other side move to the high-purity crystal side with a narrow forbidden band width, forming a two-dimensional electron gas, and these electrons are scattered by ionized impurities. It is known that it exhibits high mobility especially at low temperatures because it is less susceptible to oxidation. For GaAs and GaAlAs, only for GaAlAs,
In the case of InP and InGaAs, if a donor impurity is added only to InP, a two-dimensional electron gas is formed at the hetero interface.

FET using this high mobility two-dimensional electron gas,
Prototype integrated circuits have been manufactured mainly using GaAs and GaAlAs systems, but in order to produce integrated circuits with low power consumption and high speed, it is necessary to combine normally-off FETs and normally-on FETs on the same substrate. need to be manufactured. To achieve this, a method as shown in FIG. 1 is used.

First, on a semi-insulating GaAs substrate 1, a high-purity GaAs layer 2 with no additives formed by molecular beam epitaxial growth, an n-type GaAlAs layer 3,
The n-type GaAs layer 4 is grown, and the GaAs layer 2 and
A two-dimensional electron gas layer 5 is formed at the interface of the GaAlAs layer 3.

In order to fabricate a normally-off type FET using this, as shown in Figure 1a, the n-type
Only a portion of the GaAs layer 4 where a shot gate metal 6 is to be formed is removed, and a shot gate metal 6 is formed thereon, and a source electrode 7 and a drain electrode 8 as ohmic electrodes are further formed.

With this configuration, now the n-type
If the thickness of the GaAlAs layer 3 is made thin, the depletion layer will extend to the two-dimensional electron gas under the gate only by the height of the shot barrier between the gate metal 6 and the GaAlAs layer 3. No current flows between the electrode 8 and the source electrode 7, resulting in a normally-off type FET.

On the other hand, to make a normally-on type FET, as shown in FIG. 1b, a shot gate metal 6' is formed on the n-type GaAs layer 4 on the same substrate without etching it. Then, the n-type GaAs layer 4
Therefore, the depletion layer does not extend to the two-dimensional electron gas only due to the height of the Schottky barrier, and a normally-on type FET in which current flows between the drain electrode 8' and the source electrode 7' without applying a positive potential to the gate is formed. can.

In addition, in FIGS. 1a and 1b, 9 and 9' are surface protection films made of an insulator.

However, according to the above method,
There were other problems, such as requiring precise selective etching of the GaAs layer 4 and not having a completely planar structure.

(Object of the invention) This invention was made in view of the above points, and
The present invention aims to provide a method for manufacturing a semiconductor device that allows normally-off and normally-on FETs using dimensional electron gas to be easily manufactured on the same substrate with a completely planar structure.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows an embodiment of the present invention, in which a shows a normally-off type FET and b shows a normally-on type FET. As shown in these figures, an n-type GaAs layer 11 of high purity is grown on a semi-insulating GaAs substrate 10 by molecular beam epitaxial growth or the like.
GaAlAs layer 12 is grown, and GaAs layer 11 and
A two-dimensional electron gas layer 13 is formed at the interface of the GaAlAs layer 12. In that case, the donor concentration and thickness of the n-type GaAlAs layer 12 must be selected to values that do not deplete the two-dimensional electron gas only by the barrier height of the shot junction with the metal.

To manufacture a normally-off type FET using this, as shown in Figure 2a, the gate part must be
A P-type region 14 is formed in the GaAlAs layer 12 by ion implantation of Zn or Be, and a gate is formed by a PN junction. The depth of the P-type region 14 at this time needs to be such that the two-dimensional electron gas can be completely depleted at the height of the barrier of this PN junction. Then, on top of that (above the P-type region 14) is a gate metal 15, and on both sides of this gate metal 15 is an n-type
A normally-off type FET is manufactured by forming an ohmic source electrode 16 and a drain electrode 17 on the GaAlAs layer 12.

On the other hand, to make a normally-on type FET,
As shown in FIG. 2b, a gate metal 15' and a source electrode 1 are directly shot onto the epitaxially grown crystal (on the n-type GaAlAs layer 12).
6', an ohmic electrode of the drain electrode 17' is formed.

In addition, in Figure 2 a and b, 18,1
8' is a surface protection film made of an insulator.

As explained above, in one embodiment, normally-off and normally-on FETs can be fabricated on the same substrate, so low power consumption semiconductor devices that take advantage of the high mobility of two-dimensional electron gas, such as digital integrated circuits, can be manufactured. It can be easily manufactured. Furthermore, by controlling the depth of the PN junction, the threshold voltage of the normally-off FET can be controlled. Furthermore, there are no etching processes that require precise control, and the device can be manufactured with a completely planar structure, which is advantageous in terms of process.

In addition, in the above embodiment, the n-type GaAlAs layer is of high purity.
Although we have explained the case where the electron gas layer is on the GaAs layer, it is also possible to grow a high-purity GaAs layer on the n-type GaAlAs layer and form a two-dimensional electron gas layer on the GaAs side of the hetero interface. As in the example, normally-on type
FETs and normally-off FETs can be fabricated with a planar structure using a PN junction gate.

Moreover, although GaAs and GaAlAs-based materials have been described above, the same applies to other materials.

(Effect of the invention) As detailed above, according to the method of this invention,
A normally-on type and a normally-off type can be connected on the same substrate using a shotgun junction gate and a PN junction gate.
Since we manufacture FETs, we will develop high-performance normally-on and normally-off types that use two-dimensional electron gas.
FETs can be easily manufactured on the same substrate.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view showing a conventional method for manufacturing normally-on and normally-off type FETs on the same substrate using two-dimensional electron gas, and Fig. 2 shows an embodiment of the method for manufacturing a semiconductor device according to the present invention. FIG. 11... High purity GaAs layer, 12... n-type GaAlAs
layer, 13... two-dimensional electron gas layer, 14... P-type region, 15... gate metal, 15'... Schottky gate metal, 16, 16'... source electrode, 17, 17'...
drain electrode.

Claims (1)

[Claims] 1. A step of forming a high-purity first semiconductor layer on a semi-insulating semiconductor substrate, a step of forming a donor impurity on the first semiconductor layer and having a band gap larger than that of the first semiconductor layer. a step of forming a second semiconductor layer doped with , introducing an acceptor impurity into a predetermined region of the second semiconductor layer to a depth where the barrier height of the PN junction can deplete the two-dimensional electron gas under the predetermined region; , a step of forming a P-type region, a step of forming a gate electrode on the P-type region, forming a source electrode and a drain electrode on a second semiconductor layer sandwiching the P-type region, and manufacturing a normally-off type FET. A method for manufacturing a semiconductor device, comprising: forming a shot gate electrode, a source electrode, and a drain electrode directly on the second semiconductor layer to manufacture a normally-on FET.