JPS6367681B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a dual-system digital control device using two independent microprocessors that perform the same processing using the same input signal, and particularly relates to The present invention relates to a dual-system digital control device equipped with an output verification device suitable for output verification.

[Conventional technology]

In recent years, with the advancement of electronics, electric power,
Microprocessors are often used in control devices in general industries. These microprocessors use highly integrated semiconductor elements and can be configured as extremely compact and multifunctional control devices; however, failure of one element can bring down the entire control device. There is.

In addition, the stored program method using a microprocessor makes it possible to easily configure highly multiplexed control devices, and for controlling important equipment on a system, the output of multiple control devices can be easily configured. The dual-and method is often used, in which the device is controlled only when the results match.

However, according to the dual-AND method, all the multiplexed microprocessors perform calculations asynchronously, so even if the same conditions are given as input data, the difference in the scan timing of the calculation part will be reflected in the calculation part as it is. This results in a shift in the output timing, and even if the arithmetic unit outputs a pulse with a width of the required amount, a pulse with a width shorter than the width of the pulse will be output as a result of verification. In this case, the pulse width may be too short and the target control equipment may not operate.

A conventional output verification method will be explained using FIGS. 1 and 2.

According to the conventional method, input data A is taken into the calculation section 2 and the calculation section 3 via the data input section 1. Here, the calculation unit 2 performs predetermined processing with the storage unit 4 and outputs output data B. Similarly, the calculation section 3 and the storage section 5 output the output data C. However, the data output section 6
As shown in graphs B and C in Fig. 2, the data sent to the processor 2 and 3 may be output with a certain degree of deviation because the processors 2 and 3 operate asynchronously using their own clocks. is common. Therefore, when the output data B and C are temporarily stored in the data latch circuits 7 and 8 of the data output section 6 and then collated in the AND circuit 9 for comparison, the final output D is obtained from the data initially given by the arithmetic section 2 and the arithmetic section 3. It becomes shorter than the pulse width. In order to solve this problem, a collation device as described in Japanese Patent Application Laid-Open No. 87201/1983 has been proposed. This device has a logic circuit between the microprocessors that make up the dual system, which outputs the internal state of its own system and inputs the internal state output to the other system. This is to synchronize and verify the output signals of the processor.

[Problem that the invention seeks to solve]

Arithmetic means such as microprocessors have a large number of parts and generally have a high probability of failure. If a verification device is installed inside a microprocessor that is prone to failure, there is a high probability that when the microprocessor fails, the output verification device will also fail at the same time, resulting in erroneous outputs and a lack of reliability in the entire control device. Ta.

Of course, software verification using a stored program using a microprocessor is also considered, but
The problem remains that the reliability of the entire system depends on the hardware in the common parts.

An object of the present invention is to provide a dual system digital control device having a highly reliable output verification device.

[Means for solving problems]

The above purpose is an output verification device that performs the AND and OR of the output signals of two arithmetic means, sets the data latch circuit at the rising edge of the AND output pulse, and resets the data latch circuit at the fall of the OR output pulse. This is achieved by providing

[Effect]

The independent signals output from the two microprocessors are input to the data latch circuit via an AND circuit and an OR circuit. The data latch circuit operates at the rising edge of the output pulse from the AND circuit, and operates at the falling edge of the output pulse from the OR circuit. As a result, the data latch circuit operates and outputs pulses from the set time to the reset time, and therefore outputs pulses having the same width as the output pulses from the microprocessor.

〔Example〕

An embodiment of the present invention will be described below with reference to block diagrams and time charts shown in FIGS. 3 and 4.

Input data A is taken into a calculation unit 2 and a calculation unit 3 via a data input unit 1 . Here, the output data B and C processed through the storage section 4 and the storage section 5 have a time lag due to the asynchronization of the calculation section 2 and the calculation section 3, as shown in graphs B and C in FIG. This time difference remains the same in the outputs of the data latch circuits 7 and 8 provided in the data output section 6, and is intended to be corrected by the subsequent circuit. That is, the pulses output from the data latch circuits 7 and 8 are connected to an AND circuit (hereinafter referred to as AND circuit) 9 and an OR circuit (hereinafter referred to as OR circuit).
The output pulse of the AND circuit 9 is directly input as a set signal to a data latch circuit (hereinafter referred to as a flip-flop circuit) 10, and the output pulse of the OR circuit 11 is input as a reset signal to the flip-flop circuit 10 via a NOT circuit 12. do. As a result, the flip-flop circuit 10 becomes
It operates from the rising edge of the pulse of the AND circuit 9,
Pulses are output until the pulse of the note circuit 12 rises. In other words, the flip-flop circuit 10 outputs a pulse from the time when both the output pulse of the AND circuit 9 and the output pulse of the OR circuit 11 exist until the time when they cease to exist. Therefore, the same pulse width as that of data latch circuit 7 or 8 can be output. In addition, the on time of the output pulses of microprocessors 2 and 3 is shorter than the off time, and before the output pulse of one microprocessor 2 or 3 falls, the output pulse of the other microprocessor 2 or 3 is output. The input side is adjusted so that the

〔Effect of the invention〕

According to the present invention, it is possible to prevent the influence of output timing deviation due to asynchronous operation when two sets of arithmetic units and storage units are operating normally, and to ensure that the pulse width of the comparison result is the same as the output pulse width of the microprocessor. This has the effect of improving reliability as a verification device for obtaining the same pulse width. As other accompanying effects, the verification device is configured with a simple circuit, so there is a low probability of failure, and since verification is performed near the target control equipment, noise between the verification device and the target control equipment can be reduced, preventing control equipment from malfunctioning. rate will be lower.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional dual system output verification method, FIG. 2 is a time chart thereof, FIG. 3 is a block diagram showing a dual system output verification method according to an embodiment of the present invention, and FIG. 4 shows the time chart. 1...Data input section, 2, 3...Calculation section, 4,
5... Storage section, 6... Data output section, 7, 8...
Data latch circuit, 9...AND circuit for verification,
A...Input data, B, C...Computation unit output data, D...Verification output data.

Claims (1)

[Claims] 1. In a dual-system digital control device in which the same input signal is applied to two mutually independent calculating means having the same processing function and performing calculations, a logical product for calculating the logical product of the output signals of both said calculating means a calculation means, a logical sum calculation means for calculating the logical sum of the output signals of both said calculation means, and a point in time when the output signal of said logical product calculation means and the output signal of said logical sum calculation means both exist and cease to exist together; 1. A dual-system digital control device comprising an output verification device having data latch means for producing an output signal only during the period of time.