JPS6367771B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a phase circuit.

Generally, in a phase circuit, the amount of attenuation of the circuit changes depending on the frequency, and the amplitude characteristics (frequency characteristics) of the output are not flat. The first phase circuit to date with flat frequency characteristics from low to relatively high frequencies.
There is a circuit as shown in the figure. This circuit is well known, and consists of connecting a series circuit of a capacitor and a resistor to signal sources with opposite phases and equal amplitude, and outputting the output from the connection point of the capacitor and resistor.
Ideally, the output amplitude would be constant regardless of frequency. In Figure 1, input terminal 11 is connected to the base of transistor Q ₁₁ , resistor R ₁₁ is connected between the emitter and ground (reference potential point), and the collector and power supply V _{cc are} connected.
(Reference potential point) A resistor _R12 is connected between the two. A resistor is connected between the emitter of transistor _Q11 and output terminal 12.
R ₁₃ is connected, and a capacitor C ₁₁ is connected between the collector and the output terminal 12.

Semiconductor integrated circuit with multiple stages of circuits with the above configuration
It is easy to convert it into an IC because the number of elements is small.
Multi-stage connection means, as shown in Fig. 2, that if the functional block in Fig. 1 is An, its input terminal is 11n, and its output terminal is 12n, the output terminal 12n and the input terminal 11 _o+1 are connected. say.

Conventionally, the use of ICs for multi-stage connections has the following drawbacks.

(1) Due to the use of ICs, transistor _Q11 has a parasitic capacitance _CSO between the collector and the substrate as shown in Figure 3. For this reason, the flatness of the frequency characteristics deteriorates at high frequencies.

(2) Between the input and output terminals, there is a potential drop across the resistor _R13 due to the forward voltage _VBE1 between the base and emitter of the transistor _Q11 and the base current of the transistor connected to the next stage via the resistor _R13 . There is a potential difference equal to the sum of V and _R , and the operating point gradually decreases due to multi-stage connections, and the dynamic range disappears. In other words, there are limits to multi-stage connections. Further, this potential difference between the input and output terminals is also affected by temperature drift, and the operating point tends to fluctuate.

This invention was made in order to deal with the above-mentioned circumstances, and it is possible to obtain flatness of frequency characteristics up to high frequencies, to set the operating level of the input and output terminals at the same potential, and to prevent this operating level from temperature drift, etc. It is an object of the present invention to provide a phase circuit that is not affected by this.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIGS. 4 and 5 are diagrams for explaining the structure and operation for flattening the frequency characteristics up to high frequencies, which is one of the features of the present invention.

First, in Figure 4, the base of transistor Q ₂₁ is connected to input terminal 21, and the collector is connected to a resistor.
Connected to power supply V _cc via R ₂₁ . The emitter of transistor Q ₂₁ is grounded via a series connection of diode-connected transistor Q ₂₂ and resistor R ₂₂ . A series circuit consisting of a capacitor C ₂₁ and a resistor R ₂₃ is inserted in parallel between the collector and emitter of the transistor Q ₂₁ . The output terminal 22 is connected to the midpoint between the capacitor C ₂₁ and the resistor R ₂₃ .

Note that a diode may be used in place of the diode-connected transistor _Q22 , but in semiconductor integrated circuits, a diode is often formed by shorting the base and collector of the transistor.

The operation in the above configuration will be explained. Now, assume that the parasitic capacitances between the collectors and substrates of transistors Q ₂₂ and Q ₂₁ are C _S1 and C _S2 , respectively.

When the input signal e ₁ is applied to the terminal 21, the output signal e ₂ is determined from FIG. FIG. 5 shows an equivalent circuit of FIG. 4. Let i ₁ be the current flowing through the parallel impedance of capacitor C _S1 and resistor R ₂₂ . Resistance R ₂₁ ,
Let i ₂ be the current flowing through the capacitor C _S2 . Resistance R ₂₁ and capacitance
As is clear from the figure, current i ₁ flows through the parallel impedance of C _S2 .

From FIG. 5, the following equation is established.

i ₁ = 1 + SC _a R _a /R _a・e ₁ (1) Where, R _a is the resistance R ₂₂ value C _a is the capacitance C _S1 value S is jω (ω is the angular frequency) e ₁ = (R _c +1 /SC _c )i ₀ −R _b /1+SC _b R _b ×i ₁ (2) However, R _b is the resistance R ₂₁ value R _c is the resistance R ₂₃ value C _b is the capacitance C _S2 value C _c is the capacitance Value of C ₂₁ Substituting equation (1) into equation (2), e ₁ = (R _c +1/SC _c )i ₀ −R _b /1+SC _b R _b ×1+SC _a R _a /R _a ×e ₁ ( 3) From formula (3), i ₀ is i ₀ =1+1+SC _a R _a /1+SC _b R _b・R _b /R _a /R _c +1/SC
_c・e ₁ (4) The following equation is further derived from Figure 3.

e ₂ = e ₁ −R _S i ₀ =1−1+1+SC _a R _a /1+SC _b R _b・R _b /R _a /R _c +1/
SC _c・R _c e ₁ (5) Here, if we choose R _a = R _b = R _x , equation (5) becomes e ₂ = 1−1+1+SC _a R _x /1+SC _b R _x /R _c +1/SC _c・R
_c e ₁ (6). Furthermore, to cancel the effect of parasitic capacitance
If we choose C _a = C _b = C _x , e ₂ = 1-2R _c /R _c +1/SC _C e ₁ =1-SC _c R _c /1+SC _c R _c
・e ₁ (7). From equation (7), it can be seen that the coefficient of e ₁ has the same absolute value regardless of the frequency. That is, the amplitude characteristic of e ₂ is constant with respect to frequency.

Thus the value of parasitic capacitance C _S1 of transistor Q ₂₂
When fabricating a semiconductor IC, it is easy to set the collector area of the transistor _Q22 so that C _a is equal to the value C _b of the parasitic capacitance C _S2 of the transistor Q ₂₁ . Also, even if C _a = C _b , it is close to C _b
With C _a , the flattening of the frequency characteristics is significantly improved compared to the conventional example without the parasitic capacitance C _S1 .

Next, a circuit that can equalize the operating voltage levels between input and output will be described with reference to FIG. In addition, in FIG. 6, the same parts as in FIG. 3 are given the same reference numerals.

A resistor _R24 is inserted between the base and collector of the transistor _Q22 . Transistor Q ₂₃ ,
The respective emitters of Q ₂₄ are coupled together and further connected to the current source I ₂₁ . Transistor Q ₂₅ , Q ₂₆
becomes a current mirror type active load, and the collector of transistor Q ₂₅ is connected to the bases of transistors Q ₂₅ and Q ₂₆ , and to the collector of transistor Q ₂₃ . The collector of transistor Q ₂₆ is connected to the base of transistor Q ₂₁ which in turn is connected to the collector of transistor Q ₂₄ . The emitter of transistor _Q22 is connected to the base of transistor _Q24 . The base of transistor Q ₂₃ is connected to input terminal 21 . Also with C ₂₁
The base of transistor Q ₂₇ is connected to the connection point of R ₂₃ . The emitter of transistor _Q27 is connected to output terminal 22 and grounded via resistor _R25 . Further, the collector of transistor _Q27 is connected to the power supply _Vcc .

The operation in the above configuration will be explained. A differential amplifier using transistors Q ₂₃ and Q ₂₄ is
By providing an active load with Q ₂₅ and Q ₂₅ and at the same time applying positive feedback to the base of the transistor Q ₂₄ via the transistors Q ₂₁ and Q ₂₂ , the base potential of the transistor Q ₂₄ is always equal to the potential V ₁ of the input terminal 21.
It is made to follow so that it is equal to . Therefore, the potential V ₂ of the output terminal 22 is as follows.

V ₂ = V ₁ + V _BE2 + R _d I _B2 −R _c I _B7 −V _BE7 (8) Where, R _d : Value of resistor R ₂₄ V _BE2 : Forward voltage value for base and emitter of transistor Q ₂₂ V _BE7 : Forward voltage value between the base and emitter of transistor _Q27 I _B2 : Base current value of transistor _Q22 I _B7 : Base current value of transistor _Q27 Where, V _BE2 ≒V _BE7 , I _B2 ≒I _B7 (9 ), then equation ( ₈ ) becomes _{V 2 ≒} V ₁ (10). Equation (9) can be easily realized by setting, for example, R _c =R _d and R _a =R _e . However, R _e is the resistance R ₂₅
is the value of

It is easy to make elements with the same characteristics such as R _c = R _d and R _a = R _e in a semiconductor IC, and this condition can be stably satisfied. In other words, equation (10) remains stable. Therefore,
In the phase circuit shown in FIG. 6, the operating levels of the input/output terminals 21 and 22 are stable even against variations in element characteristics and temperature changes. This allows multi-stage connection.

In the circuit shown in FIG. 6, the equivalent resistance between the emitter and collector of the transistor Q ₂₂ is small due to the potential drop of the resistor R ₂₄ , so the transistor Q ₂₂ in FIG.
It can be assumed that the equivalent resistance between the emitter and the collector is approximately equal to the equivalent resistance between the emitter and the collector.

FIG. 7 shows a different embodiment from FIG. 6. The differences from Figure 6 are as follows. transistor Q ₂₂
Short-circuit the base and collector of the transistor
Insert a resistor _R26 between the base of _Q24 and the emitter of transistor _Q22 . Since the base potential of transistor _Q24 is equal to the input potential _V1 , the resistance
The amount of potential drop in R ₂₆ and R ₂₃ is equal, and the transistor
If the forward voltages between the bases and emitters of _Q22 and _Q27 are set to be equal, the same effect as in the previous embodiment can be obtained.

Note that the present invention is not limited to the above embodiments. For example, in the previous embodiment, the transistor
In addition to the function of generating parasitic capacitance C _S1 at the emitter of transistor _{Q 21 ,} Q 22 has a function of configuring a part of the feedback circuit, but it is designed to have only the former function. Therefore, a feedback circuit may be provided separately.

As described above, according to the present invention, flatness of frequency characteristics can be obtained up to high frequencies, and the operating levels of input and output terminals can be set to the same potential, and furthermore, this operating level is not affected by temperature drift, etc. It is possible to provide a phase circuit that does not

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional phase circuit, Figure 2 is a block diagram showing the configuration when the circuit in Figure 1 is connected in multiple stages, and Figure 3 is for explaining the drawbacks of the circuit in Figure 1. 4 is a circuit diagram showing a part of the characteristic configuration of an embodiment of the phase circuit according to the present invention; FIG. 5 is a circuit diagram for explaining the operation of the circuit of FIG. 4; FIG. 6 is a circuit diagram for explaining the configuration of another feature of the first embodiment, and FIG. 7 is a circuit diagram showing a second embodiment of the invention. Q ₂₁ - Q ₂₇ ... Transistor, R ₂₁ - R ₂₆ ... Resistor, C ₂₁ ... Capacitor, I ₂₁ ... Constant current source, 21
...Input terminal, 22...Output terminal.

Claims (1)

[Claims] 1. An amplifier that has a pair of differential input terminals and an input signal is applied to one differential input terminal, and the output signal of this amplifier is supplied to the collector and emitter to derive signals with mutually opposite phases and approximately equal amplitudes. A transistor, a capacitor having one end connected to the collector of the transistor, a resistor inserted between the other end of the capacitor and the emitter of the transistor, and an output circuit formed at the midpoint of connection between the resistor and the capacitor. , a semiconductor element connected to the emitter of the transistor such that a parasitic capacitance having a value substantially equal to the capacitance value of the parasitic capacitance generated between the collector of the transistor and the reference potential point is generated between the emitter of the transistor and the reference potential point. and a feedback circuit that applies feedback to the other differential input terminal of the amplifier so that the potential of one differential input terminal of the amplifier is equal to the potential of the output terminal of the output circuit.