JPS636892B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to an interprocessor communication scheme in a single bus coupled multiprocessor system.

Prior Art and Problems In a multiprocessor system in which multiple processors are connected via a single bus, when a communication request occurs from one processor to another, a common memory that can be commonly accessed by each processor is created. The sending processor writes a message or the like to a predetermined area of the receiving processor, and then writes specific data from the sending processor to a register in the receiving processor via the bus, thereby generating an interrupt in the receiving processor. The receiving processor reads the message written in the common memory by identifying the interruption of the communication request, and the communication is completed when the reading process is completed.

In inter-processor communication in such conventional multiprocessor systems, if the receiving processor that has accepted an interrupt needs to identify the transmitting processor that has made the communication request, the transmitting processor must identify the transmitting processor. The program used some means to transfer information necessary for identification to the receiving processor. However, this conventional method has the disadvantage that it increases the burden on the program and that incorrect identification information may be given to the receiving processor due to a program bug.

OBJECTS OF THE INVENTION It is an object of the present invention to make it possible to easily and error-freely identify a processor that is a communication request source using a bus use permission signal line. Examples will be described in detail below.

Embodiment of the invention The figure is a block diagram of the main part of an embodiment of the invention.
1 and 2 are processors, 3 is a bus that connects each processor, 4 is a bus arbiter, 5 is a group of bus use permission signal lines consisting of signal lines corresponding to the processor, 10,
20 is an internal bus, 11, 21 is an internal bus, 10,
20 is a bus driver/receiver that transmits and receives data between the bus 3, 12 and 22 are registers for inter-processor communication, 13 and 23 are control circuits that control inter-processor communication, and 14 and 24 are inter-processor communication requests. Original processor identification register, 15,
25 is an interrupt signal line. The processors 1 and 2 include an arithmetic unit, various registers, internal memory, etc., but for the sake of simplicity, they are designated by reference numerals 10-15 and 20-2
Only the portion indicated by 5 is shown. In addition, the bus arbiter 4 performs control to grant bus usage permission to only one processor at a time in response to bus usage requests from each processor, and only transmits the bus usage permission signal line corresponding to the processor that is granted bus usage permission. is turned on. Further, registers 13 and 23 are directly accessed via bus 3 from other processors.

When communicating from processor 1 to processor 2, the bus arbiter 4 turns on the bus permission signal line for processor 1, so that
Processor 1 executes an instruction to specify register 22 of processor 2 and write predetermined data via bus 3, and sends an inter-processor communication request to processor 2.
Notify. The control circuit 25 of the processor 2 identifies that it is an inter-processor communication request based on the data written in the register 22, detects the signal line in the on state among the bus use permission signal line group 5, and issues that signal line. For example, an identification code of the corresponding processor (processor 1 in this case) is written into the identification register 24, and interrupt processing is executed in accordance with the data written into the register 22.

The identification data written in the identification register 24 is
The purpose is to identify the communication request source by reading the program of the processor 2 via the internal bus 20. For example, when processing data is to be returned to the communication request source, the processor 1, the identification data is used to immediately send the data to the processor 1. can be identified. Note that the identification data can also be in a format in which bits in the identification register 24 correspond to each processor. Also, when the processor 2 communicates with the processor 1 or another processor, the same operation as described above is performed. The on-state signal line is detected and the identification code of the processor making the communication request is written into the identification register 14.

Effects of the Invention As explained above, in a multiprocessor system connected by a single bus 3, the bus arbiter 4 allows one processor to use the bus 3 at a time via a bus use permission signal line. In addition, each processor has a register 12, 22 that is directly accessed by the other processor via the bus, and by writing specific data to this register from the other processor,
Notifies the processor of an inter-processor communication request, and upon notification of the inter-processor communication request, the control circuits 13 and 23 monitor the bus use permission signal line to identify the processor that has requested the inter-processor communication; Since the program of the inter-processor communication requesting processor eliminates the need to transfer information identifying the communication requesting processor to the specified receiving processor, the program can be simplified, and erroneous identification information due to program bugs can be avoided. It will no longer be given to the receiving processor. Furthermore, since the bus use permission signal line is used to identify the communication requesting processor, there is an advantage that the communication requesting processor can be reliably identified with a small amount of additional hardware.

[Brief explanation of the drawing]

The figure is a main part block diagram of an embodiment of the present invention. 1 and 2 are processors, 3 is a bus, 4 is a bus arbiter, 5 is a bus use permission signal line, 10 and 20 are internal buses, 11 and 21 are bus drivers/receivers,
12 and 22 are registers for interprocessor communication;
3 and 23 are control circuits, 14 and 24 are identification registers, and 15 and 25 are interrupt signal lines.

Claims (1)

[Claims] 1. A plurality of processors are connected by a single bus, and a bus arbiter grants permission to use the bus to one processor at a time via a bus permission signal line, and each processor receives requests from other processors via the bus. In a multiprocessor system that includes a directly accessed register and notifies the processor of an interprocessor communication request by writing specific data to the register, the specific data is written in the register. An inter-processor communication method characterized in that the processor that has made the inter-processor communication request is identified by monitoring the bus use permission signal line in a control circuit of the processor.