JPS636896B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-word instantaneous input type digital input circuit system that can be miniaturized and economical, and is intended for sequential operation of momentary switches on, for example, an operation panel of a measurement control system.

FIG. 1 shows a block diagram of a conventional instantaneous input type digital input circuit system with 16 bits per word.
FIG. 2 shows a block diagram of the instantaneous input type digital input circuit system for a plurality of words in the case of FIG. In the figure, 1 is the CR filter, 2 is the 16-bit memory, and 3 is the CR filter.
is a driver, 4 is an address selector, 5 is a delay circuit, S ₁ to _{S 16} are momentary switches, d ₁ to
d ₁₆ is a differential circuit, Vcc is a positive DC power supply, A ₀₀ ~ _{A 07}
1 is an address bus, and X ₁ to Xn are instantaneous input type digital input circuits shown in FIG. When any one of the momentary switches S ₁ to S ₁₆ is turned on, the circuit corresponding to the momentary switch turned on among the differentiating circuits d ₁ to _{d 16} emits a pulse signal. This pulse signal sets the corresponding location in the memory 2 to 1, and by accessing the address previously assigned to this circuit from the address bus _A00 to _A07 side, a match is made in the address selector 4 and the driver 3, and the data input to memory 2 can be read. After reading, the memory 2 is reset via the delay circuit 5. Here, the delay circuit 5 is provided so that the memory 2 is not reset while the address is being accessed. However, in the circuit system shown in Fig. 1, when the number of input words increases, as shown in Fig. 2, instantaneous input type digital circuits X ₁ to X _o are required for the number of words, and the number of printed circuit boards increases, resulting in miniaturization and economy. There was a drawback that I couldn't do it.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-word instantaneous input type digital input circuit system that can be miniaturized and economical in order to eliminate the above-mentioned drawbacks.

According to the present invention, the above object is an input buffer register in which a plurality of words of data are sequentially inputted word by word in the form of a plurality of pulse signals constituting a word through a common line, and the data is stored in the input buffer register. It includes a data detection circuit that detects the presence or absence of changed data in the input word, and a read buffer register, and when the data detection circuit detects a change in the data stored in the input buffer register, the input buffer register is The scanning of subsequent words on the input side is stopped, and the data stored in the input buffer register is read out sequentially as serial data and stored in the read buffer register, and the register is updated with the next data. is stopped, and after storage, the data is sent to the bus at the corresponding time for sending the data, and when the sending is finished, the read buffer register and data detection circuit are reset, and a new word is transferred to the input buffer register. This is achieved by a multi-word, instantaneous digital input circuit characterized in that scanning for storage of the data is resumed.

An embodiment of the present invention will be described below with reference to the drawings. Fig. 3 is a block diagram of an instantaneous input type digital input circuit system of 8 words with 16 bits per word in an embodiment of the present invention, and Fig. 4 is a time chart for the case of Fig. 3. This shows the case where a signal indicating that the switch is turned on is received; B is the input buffer register IBR set signal generated by the timing circuit 9; C is the word clock signal (signal at point b) generated by the timing circuit 9; D is the output signal of the word selector 14, E is the output signal of the input buffer register IBR, F is the output signal of the data detection circuit 12 at point a, G is the output signal of the data detection circuit 12 at point d, and H is the read buffer. The output signal of the far register RBR, I is the read signal at point c, and J is the output signal of the delay circuit 10. Components in the figure that have the same functions as those in FIG. 1 are indicated by the same symbols. 16 is an input buffer register (hereinafter referred to as IBR), and 17 is a read buffer register (hereinafter referred to as IBR).
RBR) 6 and 7 are AND circuits, 8 is a 16-bit signal clock generator, 9 is a timing circuit, 1
0 is a delay circuit, 11 is an address selector and a matching circuit for a preset address, a signal from the address bus, a word signal, and an output signal at point d (hereinafter referred to as the address selector and matching circuit); 12
is a data detection circuit, 13 is a word counter, 14
15 is a word selector, 15 is a driver, and a to d are points for explanation. B, C from timing circuit 9
Outputs the IBR set signal shown in and the word clock signal to point b. Since the data detection circuit 12 outputs 0 at point A until it detects ON data, the word counter 13, word selector 14 driver 1
The operation of sequentially scanning words 1 to 8 through 5 is repeated. The output of the selector 14 in this case is as shown in D. If there is an ON signal in the 4th word as shown in A (a momentary switch with 4 words is ON), the set signal shown in B causes the 4th word data (16 bits) to be stored in the IBR16 while the ON signal is present. The clock signal generated by the clock generator 8 outputs serial data from the IBR 16 and stores 16-bit data in the RBR 17. On the other hand, data detection circuit 1
In step 2, upon detection of data that has become 1 in the output data of IBR, a signal as shown in F is output to immediately stop the increment of the word counter 13 (selector output 4W in D). When the data of the IBR 16 is stored in the RBR 17, the data detection circuit 12 outputs a signal as shown in G to stop the clock generated by the clock generator 8 to the RBR 17, thereby stopping data updating. Note that when the signal indicated by G becomes 1, data can be read. Data is read using signals from address buses A ₀₀ to A ₀₇ , signal 1 at point d, and the output of word selector 14 [here, D
When the preset address matches the 4-word value (as shown in Figure 1), a read signal shown at I is obtained, and the driver 3 is turned on, and the 4-word data stored in the RBR 17 is transferred via the driver 3. output to the bus. The read signal shown at I is delayed by the delay circuit 10 as shown at J and output to RBR1.
7. The data detection circuit 12 is reset and the word counter 13 starts scanning from the next word clock signal. In other words, if an on signal exists in a word, the on signal in the word is detected, and only the word with an on signal is input to the RBR 17, which is output via the driver 3, so it is an instantaneous input type digital input for one word. All you need is a circuit.

As explained in detail above, according to the present invention, for example, when a sequential operation of a momentary switch on an operation panel of a measurement control system is targeted, even if there is an input circuit for multiple words, an instantaneous input type digital input circuit for one word can be used. Since it is only necessary to have one, it has the effect of downsizing and economicalization.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional instantaneous input type digital input circuit system with 16 bits per word, Figure 2 is a block diagram of a multiple word instantaneous input type digital input circuit type in the case of Figure 1, and Figure 3. 4 is a block diagram of an 8-word instantaneous input type digital input circuit system with 16 bits per word according to an embodiment of the present invention.
The figure is a time chart for the case of Fig. 3, where A shows the case where the momentary switch is turned on at the 4th word, B shows the IBR set signal generated by the timing circuit 9, and C shows the timing. The word clock signal (signal at point b) generated by the circuit 9, D is the output signal of the word selector 14, and E
is the output signal of IBR, F is a of the data detection circuit 12
G is the output signal of point d of the data detection circuit 12, H is the output signal of RBR, I is the read signal at point c, and J is the output signal of the delay circuit 10. In the figure, 1 is a CR filter, 2 is a 16-bit memory, 3 and 15 are drivers, 4 is an address selector, 5 and 10 are delay circuits, _S1 to _S16 are momentary switches, _d1 to _d16 are differential circuits, Vcc
is positive DC power supply, A ₀₀ ~ A ₀₇ is address bus, X ₁
~X _o is the instantaneous input type digital input circuit shown in Fig. 1, 16 is an input buffer register, 17 is a read buffer register, 6 and 7 are AND circuits, and 8 is an
16-bit signal clock generator, 9 is a timing circuit, 11 is an address selector and matching circuit, 1
2 is a data detection circuit, 13 is a word counter, 1
4 is a word selector, and a to d indicate points for explanation.

Claims (1)

[Claims] 1. An input buffer register in which a plurality of words of data are sequentially inputted word by word in the form of a plurality of pulse signals forming a word through a common line; It includes a data detection circuit for detecting the presence or absence of data, and a read buffer register, and when the data detection circuit detects a change in the data stored in the input buffer register, the read buffer register detects the presence or absence of data. Scanning is stopped, and the data stored in the input buffer register is sequentially read out as serial data and stored in the read buffer register, and updating of the register with the next data is stopped, and after storage, the data is The data is sent to the bus at the corresponding time for sending the data, and when the sending is finished, the read buffer register and data detection circuit are reset and scanning resumes for storing a new word in the input buffer register. A multi-word instantaneous input type digital input circuit characterized in that: