JPS638194B2 - - Google Patents
Info
- Publication number
- JPS638194B2 JPS638194B2 JP54101718A JP10171879A JPS638194B2 JP S638194 B2 JPS638194 B2 JP S638194B2 JP 54101718 A JP54101718 A JP 54101718A JP 10171879 A JP10171879 A JP 10171879A JP S638194 B2 JPS638194 B2 JP S638194B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit pattern
- printed wiring
- plating
- wiring board
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Electroplating Methods And Accessories (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
【発明の詳細な説明】 本発明は印刷配線板の製造方法に関する。[Detailed description of the invention] The present invention relates to a method of manufacturing a printed wiring board.
従来、選択的めつきを施こす印刷配線板の製造
方法は耐めつき性レジスト層でめつきの不必要部
をマスクする方法が用いられ、このマスクは各製
造工程に於ける操作・加工性および人的・物的資
源の有効活用を考慮した複数個のマスクパターン
を有するスクリーン原版(以下マスク原版と称
す)で形成する方法が用いられている。 Conventionally, the manufacturing method for selectively plating printed wiring boards uses a method of masking unnecessary parts of plating with a plating-resistant resist layer, and this mask is used to improve operability and processability in each manufacturing process. A method of forming a screen using a screen original (hereinafter referred to as a mask original) having a plurality of mask patterns is used in consideration of effective utilization of human and material resources.
この時同じマスクパターンを並べることが一般
的に行なわれていた。 At this time, it was common practice to arrange the same mask patterns side by side.
このため電子時計用印刷配線板の如く選択的め
つきを施こす面積が大きく、かつ表裏面の面積の
差が大きい回路設計を余儀なくされた印刷配線板
ではめつき厚を均一に制御することが難しく、高
価な貴金属を浪費して安価な印刷配線板の提供を
阻害する欠点があつた。 For this reason, it is difficult to control the plating thickness uniformly in printed wiring boards for electronic watches, which require a large area to be selectively plated and which require a circuit design with a large difference in area between the front and back surfaces. This method has the drawback of wasting difficult and expensive precious metals and hindering the provision of inexpensive printed wiring boards.
本発明の目的は上記従来欠点を除去した印刷配
線板の製造方法を提供することにある。 An object of the present invention is to provide a method for manufacturing a printed wiring board that eliminates the above-mentioned conventional drawbacks.
本発明によれば、表裏面の回路パターンを同一
面上に1対にして複数の組として形成した印刷配
線基板に表裏面のマスクパターンを有する耐めつ
き性のレジスト層のマスクを順次印刷配線基板の
表裏面から印刷する工程と耐めつき性のレジスト
層のマスクで被覆した部分以外に貴金属めつきを
する工程とからなる選択的めつき工程を用いるこ
とを特徴とする印刷配線板の製造方法が得られ
る。 According to the present invention, a mask of a plating-resistant resist layer having a mask pattern on the front and back surfaces is sequentially printed on a printed wiring board in which circuit patterns on the front and back sides are formed in pairs on the same surface as a plurality of sets. Manufacture of a printed wiring board characterized by using a selective plating process consisting of a process of printing from the front and back sides of the substrate and a process of plating precious metal on areas other than those covered with a mask of a resist layer with anti-plating properties. method is obtained.
以下本発明を図面を参照して説明する。 The present invention will be explained below with reference to the drawings.
第1図、第2図は本発明の一実施例であり、第
1図a,bはそれぞれ印刷配線基板1の表面およ
び裏面に貴金属めつき層2を選択的に施こした状
態を示す。 1 and 2 show an embodiment of the present invention, and FIGS. 1a and 1b show a state in which a noble metal plating layer 2 is selectively applied to the front and back surfaces of a printed wiring board 1, respectively.
参照符号3は表面マスク層、4は裏面マスク
層、5は表面の回路パターン6および裏面の回路
パターン7に貴金属めつき層2を施こす時用いる
導電路としてのリードを示す。 Reference numeral 3 indicates a front mask layer, 4 indicates a back mask layer, and 5 indicates a lead as a conductive path used when applying the noble metal plating layer 2 to the circuit pattern 6 on the front surface and the circuit pattern 7 on the back surface.
周知の方法を用いてスルーホール接続用の孔
(図示省略)を穿孔し孔壁に銅めつきを施こし、
感光性レジストで回路パターンの像を形成したの
ち、回路パターン以外の不必要部の銅を腐蝕除去
して表面の回路パターン6および裏面の回路パタ
ーン7を形成する。 Using a well-known method, holes for through-hole connections (not shown) are drilled, and the walls of the holes are plated with copper.
After forming an image of a circuit pattern with a photosensitive resist, unnecessary portions of copper other than the circuit pattern are removed by corrosion to form a circuit pattern 6 on the front surface and a circuit pattern 7 on the rear surface.
この時印刷配線基板1に投影図状に展開した表
面の回路パターン6および裏面の回路パターン7
を1対にして複数の組として並べて両面に形成す
る。 At this time, the circuit pattern 6 on the front surface and the circuit pattern 7 on the back surface developed in a projected pattern on the printed wiring board 1
A plurality of pairs are arranged and formed on both sides.
次に表面の回路パターン6には表面マスクパタ
ーンを有する表面マスク層3、裏面の回路パター
ン7には裏面マスクパターンを有する裏面マスク
層4を印刷する。 Next, a front mask layer 3 having a front mask pattern is printed on the circuit pattern 6 on the front side, and a back mask layer 4 having a back mask pattern on the circuit pattern 7 on the back side.
次に貴金属めつき浴(図示省略)内で、耐めつ
き性のレジスト層で形成した表面マスク層3およ
び裏面マスク層4で被覆させた部分以外に貴金属
めつき層2をリード5を通電路として必要量のめ
つき電流を通電しめつきする。 Next, in a noble metal plating bath (not shown), the noble metal plating layer 2 is placed on the lead 5 on the parts other than the parts covered with the front mask layer 3 and the back mask layer 4 formed of a plating-resistant resist layer. The required amount of plating current is applied as described above.
以上本発明によつて貴金属めつきをする時、印
刷配線板の上下面で通電量を同等に制御すること
ができるので、貴金属めつきの厚みを均一にする
ことができ、かつ貴金属の消費を抑制することが
できる効果が大である。 As described above, when plating precious metals according to the present invention, the amount of current applied to the upper and lower surfaces of the printed wiring board can be controlled equally, so the thickness of the precious metal plating can be made uniform, and the consumption of precious metals can be suppressed. It can be very effective.
第1図a,b、第2図は本発明の一実施例を示
す平面図である。
1……印刷配線基板、2……貴金属めつき層、
3……表面マスク層、4……裏面マスク層、5…
…リード、6……表面の回路パターン、7……裏
面の回路パターン。
FIGS. 1A and 1B and FIG. 2 are plan views showing an embodiment of the present invention. 1...Printed wiring board, 2...Precious metal plating layer,
3... Front mask layer, 4... Back mask layer, 5...
...Lead, 6...Circuit pattern on the front side, 7...Circuit pattern on the back side.
Claims (1)
造方法において、同一基板の一方の面上に前記印
刷配線板の表面の回路パターンと裏面の回路パタ
ーンとを複数配列するとともに前記基板の他方の
面上で前記表面の回路パターンと対向する位置に
前記裏面の回路パターンを形成し、かつ前記基板
の他方の面上で前記一方の面上の裏面の回路パタ
ーンに対向する位置に前記表面の回路パターンを
形成する工程と、耐めつき性のレジスト層のマス
クを前記回路パターンに施こす工程と、前記耐め
つき性のレジスト層のマスクを被覆した部分外の
部署にめつきを施こす選択的めつき工程とを有す
ることを特徴とする印刷配線板の製造方法。1. In a method for manufacturing a printed wiring board having circuit patterns on both sides, a plurality of circuit patterns on the front side and a circuit pattern on the back side of the printed wiring board are arranged on one side of the same substrate, and a plurality of circuit patterns on the front side and the circuit pattern on the back side are arranged on one side of the same substrate, and forming the circuit pattern on the back surface at a position facing the circuit pattern on the front surface, and forming the circuit pattern on the front surface at a position opposite to the circuit pattern on the back surface on the other surface of the substrate. a step of applying a mask of a plating-resistant resist layer to the circuit pattern; and a step of selectively applying plating to areas other than the portions covered with the mask of the plating-resistant resist layer. 1. A method for manufacturing a printed wiring board, comprising a step of attaching the printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10171879A JPS5626490A (en) | 1979-08-09 | 1979-08-09 | Method of manufacturing printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10171879A JPS5626490A (en) | 1979-08-09 | 1979-08-09 | Method of manufacturing printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5626490A JPS5626490A (en) | 1981-03-14 |
| JPS638194B2 true JPS638194B2 (en) | 1988-02-22 |
Family
ID=14308077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10171879A Granted JPS5626490A (en) | 1979-08-09 | 1979-08-09 | Method of manufacturing printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5626490A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7876906B2 (en) | 2006-05-30 | 2011-01-25 | Sonitus Medical, Inc. | Methods and apparatus for processing audio signals |
| US7682303B2 (en) * | 2007-10-02 | 2010-03-23 | Sonitus Medical, Inc. | Methods and apparatus for transmitting vibrations |
| US8433082B2 (en) | 2009-10-02 | 2013-04-30 | Sonitus Medical, Inc. | Intraoral appliance for sound transmission via bone conduction |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54142637A (en) * | 1978-04-28 | 1979-11-07 | Sony Corp | Electronic-controlled cooking machine |
-
1979
- 1979-08-09 JP JP10171879A patent/JPS5626490A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5626490A (en) | 1981-03-14 |
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