JPS63822B2 - - Google Patents

Description

[Detailed description of the invention]

This invention relates to a microcomputer and a ROM or
It relates to a program theft prevention device for an electronic device whose main component is a program stored in a RAM, and is particularly configured to output a key signal specified based on a history of signals sent and received in the past. The present invention provides a program theft prevention device including a key device. In recent years, with the spread of microcomputers,
Various devices incorporating microcomputers began to be manufactured and sold in large quantities. For such devices, the creation of programs accounts for a considerable proportion of the cost and has great property value, but on the other hand, it is relatively easy to imitate by direct copying from sold devices. The reality is that program plagiarism is rampant, and manufacturers and sellers who have developed original programs are suffering tremendous damage. Such damage is becoming more serious as a result of the increasing opportunities for theft due to the increasing distribution of devices incorporating the program, as well as the increasing property value due to the increasing complexity and sophistication of programs. Previous program plagiarism prevention devices use specific key figures known only to the program creator.
The key values are stored at specific addresses in the ROM, read out at predetermined steps as the program progresses, and used as variables for arithmetic processing specified in the program (hereinafter referred to as key processing work). It was configured to be used as Examples of the above key processing work include: (1) Multiplying the calculation result of the main work by a key value. (2) Compare the calculation result of key processing work with a specific key value, and if there is a mismatch, jump to a specific address. (3) Use indirect addresses specified by key figures. Such processing has been proposed. However, by including a program for such key processing work in a program, it is possible to make it considerably difficult for someone else to decode the program; Since it also includes programs, it has the disadvantage that it is difficult to prevent plagiarism as is. An object of the present invention is to provide a key device in which the main part of the program for key processing work is implemented in hardware, in view of the problem of theft in the original program theft prevention device. It is an object of the present invention to provide a program theft prevention device which can eliminate the above-mentioned drawbacks by making it impossible to plagiarize programs unless the above configuration is duplicated, and which can extremely effectively prevent theft. In accordance with the above object, the present invention includes a key operation signal means that sends and receives a series of signals (hereinafter referred to as key operation signals) to and from a key device via an address bus or a data bus, and upon key processing operations, When a signal is read from a specific address of the key device (hereinafter referred to as a key address), the key device receives a signal defined by a specific function whose variables are a series of key operation signals sent and received in the past (hereinafter referred to as a key signal). is output, and this key signal is processed by a key signal processing means,
The present invention is characterized in that if a predetermined key signal known to the program creator cannot be obtained, the main operation of the program is brought into an abnormal state. The structure and operation of an embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, 1 is a central processing unit (hereinafter referred to as
It includes key operation signal means 1a and key signal processing means 1b which are functionally realized by a program. 2 is a data bus, often consisting of 8 conductors; 3 is an address bus, often consisting of 16 conductors; and 4 are control lines. The buses 2, 3 and the control line 4 are branched and extend to a read-only memory (hereinafter referred to as ROM) or a random access memory (hereinafter referred to as RAM) 5, with bus 2 being the data input/output terminal, and bus 3 being The control line 4 is commonly connected to the address terminal and the read/write control terminal. 6 is a key device,
Similar to ROM or RAM, a data bus 2 is connected to its data input/output terminal, an address bus 3 is connected to its address terminal, and a control line 4 is connected to its read/write control terminal. In general, in a device consisting of a CPU and a ROM or RAM that stores programs, the contents of a sequentially incrementing program counter built into the CPU 1 are sent to the address bus 3 as an address signal consisting of a device selection signal and a key operation signal. The address for selecting one of the plurality of ROMs or RAMs 5 is specified by the device selection signal, and the selected ROM or
An address in the RAM is designated by a key operation signal, and at the same time, a read signal is transmitted from the CPU 1 to the ROM or RAM 5 through the control line 4, and these are set to read mode, and the designated address in the ROM or RAM selected through the data bus 2 is transmitted. The instructions (constituting the program) stored at the specified address are sequentially read out and executed.
The operation to be decoded and executed by the CPU 1, the address signal specified by a specific instruction in the program, and the read signal are transmitted in the same manner as described above, and the ROM or
The operation of reading the storage contents at a specified address for any one of the RAMs 5 and the address signal and write signal instructed by a specific command in the program are transmitted in the same manner as described above, and the ROM or
The basic operation is to store specific data at a designated address for any one of the RAMs 5. The key device 6 is also exactly the same as the ROM or RAM 5 as far as the transmission and reception of signals with the CPU 1 is concerned, and is compatible by sharing the connection pins. However, the key device 6 is ROM or
The device 6 does not read out the contents stored at a specified address as is, as in the RAM 5, but responds to either a write signal or a read signal supplied via the control line 4 to the device 6 via the address bus 3. or a series of key operation signals transmitted to the device 6 via the data bus 2.
Temporarily stores a series of data signals sent and received here, uses these as variables and performs arithmetic processing on the unique functions of a specific key device to calculate a key signal, and stores this in the key address. It is composed of a group of memory elements and logic circuit elements connected in this way. And when processing keys,
A key operation signal, which is an address signal for specifying a specific key address among the addresses of the selected key device 6, is read out via the address bus 3, and the operating mode of the key device is read out via the control line 4. Each time the key device 6 is accessed, the data bus 2 receives the key operation signal for each past access to the key address of the device 6. or, in addition, a key signal unique to the device 6 associated with the history of data transmitted and received in the past with respect to the device 6 via the data bus 2. Next, the operation for calculating a key signal specific to a specific key device will be described below with reference to FIG. 1 and Table 1. Now, when address 2000 is assigned to a key device with a capacity of 2 Kbytes, a 16-bit address signal (hereinafter referred to as A ₁₅ ,

【table】

[Table] Represented by A ₁₄ , A ₁₃ , A ₄ , A ₃ , A ₂ , A ₁ , A ₀ . ) of the 12th bit A ₁₁ to 16th bit A ₁₅ ,
When only the 14th bit _A13 is "1" and the other bits are "0", this key device 6 is specified,
Furthermore, the storage area within the key device 6, ie, the address of the key device 6, is specified by the first bit _A0 to the eleventh bit _A10 of the address signal.
If the bit states of _A11 to _A15 are different from the above,
Other elements connected to the bus, such as ROM or RAM 5, are selected. For the key device 6, it is possible to specify 2048 key addresses using A ₀ to A ₁₀ , but as an example, A ₀ = "0", A ₄ =
When "1" is selected as the key address, among the address signals supplied from the key operation signal means 1a,
When A ₀ = “0” and A ₄ = “1” are key operation signals and a read signal is received, the key device 6 outputs an 8-bit key signal to the data bus 2. I will do it. These 8-bit key signals (hereinafter referred to as R ₇ , R ₆ ,
…Represented by R ₁ and R ₀ . ) is defined by the following function based on the history of address signals supplied to the key device 6. R ₀ = A ₁ (n-1) R ₁ = A ₇ (n-3) R ₂ = ₂ () R ₃ = A ₁₀ (n-2) R ₄ = A ₃ (n-2) R ₅ = A ₁ (n-2) *A ₄ (n) R ₆ = ₉ (-1) R ₇ = A ₅ (n-1) + A ₃ (n) However, (n) (n-1) (n-2) (n-3) is the order in which the key address of the key device is accessed (the key device is the key operation signal, A ₀ = "0",
A ₄ = “1”, the received rank),
For example, (n-1) indicates the time point at which the access was made one time before the current access. Therefore, for example, R ₀ = A ₁ (n-1) means that the state of the second bit A ₁ of the address signal at the time of the previous access is the same as the state of the first bit R ₀ of the key signal at the time of the current access. It means to become. Then _{, a} series _{of key} operation signals (in _{this implementation} In the example, when the address signal itself) is supplied from the key operation signal means 1a to the key device 6, the data bus 2 is sent from the key device 6 to the data bus 2 for each access.
Key signals to be output to R ₇ , R ₆ ...... R ₁ , R ₀
Table 1 shows the bit states of . Note that blank parts in the table indicate undefined states, and X indicates redundancy. During key processing work, the key operation signal means 1
A plurality of key operation signals with address signals A ₀ = "0" and A ₄ = "1" are sequentially supplied to the key device 6 from a, and for example, at the fifth access order in Table 1, the key operation signals are When a readout signal is supplied from the signal processing means 1b to the device 6 via the control line 4 and the key signal is read out, a key signal "10111001" is obtained. This key signal is transmitted to the key signal processing means 1b through the data bus 2.
Step b determines whether this key signal is the scheduled key signal "10111001", and if it is not the scheduled key signal, the program progresses to an abnormal state. The program creator can decide what key operation signals to give to the key device 6 and in what order, and also knows the function that defines the key signals unique to this key device 6. The key signal to be obtained during the key processing operation can be scheduled. In the above embodiment, only the address signal is used as the key operation signal, but it is also possible to use the data signal sent to and received from the key device 6 through the data bus 2. Furthermore, although one address, A ₀ = "0" and A ₄ = "1", is selected, it is optional to select two or more key addresses for one key device. Furthermore, in the above embodiment, the key device 6 is configured to be used only for the purpose of key processing work and does not store data related to the main work of the program, but it is configured to have the same function as a normal RAM. You can also do that. In this case, it is sufficient to designate a normal address to operate as a RAM, designate a key address, and output a key signal determined in accordance with the key address. However, since the key operation signal cannot be freely selected apart from the main work of the program, the key signal is also bound to the main work program. Figure 2 shows the form of the key device 6, which is the main component of this invention. Figure A is a perspective view showing the key device and socket, and Figure B shows the key device mounted on a printed circuit board. FIG. In FIG. 1A, the key device 6 has a standard shape and is further provided with pins 7 having a standard arrangement and shape. The pin 7 fits into a pin hole 9 of a socket 8, and a fixing pin 10 is implanted in the bottom of the socket 8. As shown in Figure B, the socket 8 is fixed to the top surface of the board with a fixing pin 10 that passes through the printed circuit board 11 and is connected to the printed pattern, and the key device 6 is fixed to the socket by fitting the pin 7 and the pin hole 9. It is mounted on the upper surface of the printed circuit board 11 via 8. When the key device 6 is put together in the form described above, it is a standard device that is often used when collecting sold video game devices, exchanging programs, and equipping them with new game functions.
By additionally installing a key device using the ROM or RAM spare socket,
There is a practical benefit in that it is possible to prevent theft of programs after replacement without modifying the hardware. As described above, the present invention provides a key device that outputs a unique key signal expressed as a function of a series of key operation signals supplied from a key operation signal means, and furthermore, the hardware of this key device has a unique key signal. Since the program is configured in such a way that a key signal of This has the excellent effect of effectively preventing plagiarism. Furthermore, as shown in one embodiment of the present invention, it is practically unavoidable to make the program theft prevention device compact, so the program theft person inevitably copies the key device with a custom integrated circuit or the like. There must be. Therefore, since plagiarism requires advanced technology and a large amount of funds, there is an advantage in that the economic motivation for plagiarism is reduced and plagiarism can be effectively prevented. In addition, according to the present invention, the key operation signal of the address signals supplied from the key operation signal means via the address bus and the write signal or read signal supplied from the signal means via the control line can be used to control the key device. Each time a specific key address is accessed by the key address, a key signal defined by the history of key operation signals for each past access to the key address is supplied from the key signal processing means via the control line. By configuring the program to be output in response to a read signal, a group of program instructions similar to those for executing data write or read access to other storage elements ROM and RAM are inserted into the program instruction group. By doing this, the key signal from the key device can be obtained, so by simply making changes to the program commands for the main work, program theft prevention can be implemented at the desired time during the execution of the program commands for the main work. It also has the excellent effect of being able to perform the tasks simultaneously and extremely easily, and because of this effect, it has a software configuration that does not require program loading work in addition to the main work at the start of operation. Typically, this method has the advantage that it is easy to prevent program plagiarism in video game devices and the like. Moreover, according to the present invention, the key device is connected to the address bus, data bus, and control line so as to be compatible with other storage elements ROM and RAM.
The key device itself can be added to a known device using a simple device by selecting the device selection signal from among the address signals from the key operation signal means and selectively activating it. Therefore, an excellent effect can be achieved in that program plagiarism can be prevented even through post-processing at the time of program expansion and improvement work.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of an embodiment of the present invention, Figure 2 shows the form of a key device, Figure A is a perspective view showing the key device and socket, Figure B is a perspective view of the key device. FIG. 3 is a perspective view showing a state where the device is mounted on a printed circuit board. 1...Central processing unit, 1a...Key operation signal means, 1b...Key signal processing means, 2...Data
Bus, 3...Address Bus, 4...Control line, 5
...Read-only memory or random access memory, 6...Key device, 7...Pin, 8
...Socket, 9...Pin hole, 10...Fixing pin, 11...Printed circuit board.

Claims (1)

[Claims] 1. Based on the program command being executed, device selection signals A11 to A15 and key operation signals A0 to
A key operation signal means 1a for outputting address signals A0 to A15 consisting of A10 onto the address bus 3 and a write signal onto the control line 4, respectively; It consists of a semiconductor integrated circuit that is compatiblely connected to the storage elements ROM and RAM, and the address signals A0 to A15 are supplied via the address bus 3.
Only when the device is selected by the device selection signals A11 to A15 among the address signals, the key operation signals A0 to A10 of the address signals and the control line 4
For each access to a specific key address with the write signal supplied via the key operation signal A0 to each previous access to the key address
Key signals R0 to R defined by the history of A10
7 on the data bus 2 in response to a read signal on the control line 4; hand,
a key signal processing means 1b that makes it impossible to carry out the main work based on the program command being executed when the key signals R0 to R7 supplied from the key device 6 via the data bus 2 are not predetermined key signals scheduled in advance; A program plagiarism prevention device equipped with