JPS6410095B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device having a redundant function, and more particularly to a semiconductor integrated circuit device in which whether or not the redundant function is being used can be checked from the outside.

[Technical background of the invention]

Recently, in the field of semiconductor memory, regular memory cells and spare memory cells are formed in advance in the same integrated circuit device, and if a defective cell is found in the regular memory cell after manufacturing, the defective cell An increasing number of devices have a redundant function in which they are used by replacing them with spare memory cells. This is because even if only one of the normal memory cells is defective, the entire memory becomes defective, so conventionally, such memories are discarded as defective products. However, as memory storage capacity increases,
The probability of defective cells occurring is increasing,
If memories with defective cells are discarded, the yield will be low and the price will be high. Therefore, in the past, in order to improve the overall yield, a method has been adopted in which spare memory cells are provided, and if some of the regular memory cells are defective, they are switched to use. .

FIG. 1 is a block diagram of a semiconductor memory provided with the above-mentioned spare memory cells. In the figure, 1 is an address buffer to which an address signal is supplied. The output from address buffer 1 is supplied to two decoders 2 and 3 in parallel. One of the decoders 2 is for selecting memory cells in the regular memory cell array 4, and by supplying its decoded output to the regular memory cell array 4, one or more memory cells are selected. Data is then stored in or read from the selected memory cell. The other decoder 3 is for selecting a memory cell in the spare memory cell array 5 when a defective memory cell occurs in the regular memory cell array 4, and its decoding output is supplied to the spare memory cell array 5. The memory cell is selected by selecting the memory cell. Further, the decoding operation of the decoder 2 is controlled by the output of the other decoder 3.

If there is a defective cell in the regular memory cell array 4, the decoder 3 is configured so that the decoder 3 selects a memory cell in the spare memory cell array 5 when an address signal corresponding to the defective cell is supplied. is programmed. Note that this program selectively blows out fuses made of aluminum or polycrystalline silicon provided inside the decoder 3 by laser irradiation, or selectively blows out polycrystalline silicon, which is in a high resistance state in the initial state. This is done by laser annealing to lower the resistance. Therefore,
If a defective cell exists in the regular memory cell array 4, a memory cell in the spare memory cell array 5 is selected by the output of the decoder 3, and the decoding operation of the decoder 2 is stopped by the output of the decoder 3. Ru. As a result, the defective cells in the regular memory cell array 4 are replaced with good cells in the spare memory cell array 5, and this memory can be made substantially good.

By using the redundancy function of a semiconductor memory having such a redundancy function, many products including defective cells can be shipped as non-defective products.

[Problems with background technology]

By the way, conventionally, there is no means to determine whether a defective cell has occurred and its redundant function is being used, or whether there are no defective cells and the redundant function is not being used. The only way to do this is to break the container that encloses it and take out the chips.

Generally, when performing a failure analysis of a semiconductor integrated circuit device having a redundant function, it is first checked whether the redundant function is being used. It would be extremely troublesome to break the containers one by one for this purpose.

[Purpose of the invention]

This invention was made in consideration of the above circumstances, and its purpose is to easily determine from outside the integrated circuit device whether or not the redundant function is being used in a semiconductor integrated circuit device equipped with a redundant function. The purpose is to provide a means by which one can investigate the situation.

[Summary of the invention]

According to the present invention, if the redundant function is not used, the connection between the source and drain terminals of an N-channel MOS transistor between one signal input terminal and the power supply potential supply terminal is not fused and is used. A semiconductor integrated circuit device is provided in which a fuse that is blown in some cases is inserted in series, and the potential of the signal input terminal is supplied to the gate terminal of the MOS transistor.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a circuit diagram showing the configuration of the main part of the present invention, and this circuit is configured, for example, in an integrated semiconductor memory having a redundant function as shown in FIG.

In FIG. 2, reference numeral 11 denotes one of a plurality of signal input terminals for supplying signals to the inside of the integrated circuit device. This terminal 11 is provided with an input protection circuit 12 for removing surge voltage applied from the outside, and normal signals supplied to the terminal 11 are sent to the internal circuit via this input protection circuit 12. It is becoming more and more popular.

The gate terminal and drain terminal or source terminal of an N-channel MOS transistor 13 are commonly connected to the output terminal side of the input protection circuit 12. Furthermore, the connection between the source terminal or drain terminal of this MOS transistor 13 and the potential point 14 to which the positive power supply voltage V _DD is supplied during operation is fused when the redundant function is used, and is not used. When the fuse 15 is not blown, the fuse 15 is inserted without being blown. Also, above
Another N-channel MOS transistor 17 is connected to the series connection point 16 between the source or drain terminal of the MOS transistor 13 and the fuse 15.
The drain or source terminal of is connected,
The source or drain terminal and gate terminal of this MOS transistor 17 are connected together to the potential point 14. Note that both of the MOS transistors 13 and 17 are of enhancement type.

In the integrated circuit device having the circuit configured as described above, after manufacturing, the fuse 15 is blown out depending on the state of use of the redundant function. That is, if the redundant function is used, this fuse 15 is blown, and if it is not used, it is not blown. The fuse 15 is blown at the same time as the decoder 3 in the circuit shown in FIG. 1 is programmed.

Next, a method of checking the usage status of the redundant function will be explained. First, the power supply voltage V _DD is not applied, and the potential point 14 is held at the ground potential. This can be achieved by grounding the power supply terminal (not shown) for supplying _VDD . Next, in this state, a positive potential, for example the same potential as V _DD , is supplied to the signal input terminal 11.
A potential equal to the potential supplied to the terminal 11 is output to the output end of the input protection circuit 12.
Since this potential is applied to the gate terminal of the MOS transistor 13, this MOS transistor 13
turns on. At this time, if the fuse 15 is not blown, a current flows from the signal input terminal 11 toward the potential point 14 via the MOS transistor 13 and the fuse 15 in series. on the other hand,
Since the ground potential of the potential point 14 is supplied to the gate terminal of the MOS transistor 17, the MOS transistor 17 is in an off state. Therefore,
If the fuse 15 is blown, no current will flow through the signal input terminal 11.

Therefore, in order to check whether the redundant function is being used, it is sufficient to check with an ammeter or the like whether or not current flows through the signal input terminal 11 when a positive potential is supplied to this terminal 11. This can be done extremely easily from the outside.

On the other hand, when an integrated circuit device including such a circuit is actually used, the potential point 14 is kept at V _DD . In addition, in actual use, the signal input terminal 11
A potential in the range between the ground potential and V _DD is supplied as an input signal potential. If the fuse 15 is not blown now, the MOS transistor 13
source or drain terminal and fuse 1
The potential of the series connection point 16 with 5 is kept approximately at V _DD . That is, in this state, the MOS transistor 13 is in an off state and does not adversely affect the internal circuit. On the other hand, when the fuse 15 is blown, the MOS transistor 17 is in an on state.
Because of this MOS transistor 17, the potential at the series connection point 16 is reduced from V _DD by the threshold voltage, so even in this state,
The MOS transistor 13 is turned off, and in this case as well, the internal circuit is not adversely affected.

The MOS transistor 17 is provided to prevent potential fluctuations at the series connection point 16 due to noise or the like when this integrated circuit device is actually used with the fuse 15 blown. There is.

That is, when this MOS transistor 17 is not provided and the fuse 15 is blown, the potential at the series connection point 16 is in a floating state. At this time, there is a possibility that the potential of the series connection point 16 becomes lower than the output terminal potential of the input protection circuit 12 due to noise or capacitive coupling. Then, in this case, MOS transistor 1
3 becomes on state, and this MOS transistor 1
A displacement current flows through the capacitor 3, increasing the rise time of the output terminal potential of the input protection circuit 12 to be supplied to the internal circuit.

As described above, according to the circuit of the above embodiment, it is possible to easily check from the outside whether or not the redundant function is being used, and there is no adverse effect on the internal circuit.

FIG. 3 shows the structure of another embodiment of the invention.
This embodiment circuit differs from the one shown in FIG. 1 by inserting the drain and source terminals of another N-channel MOS transistor 18 between the series connection point 16 and the fuse 15. The gate terminal is connected to the drain or source terminal closer to the signal input terminal 11.

In such a configuration, when checking the usage status of the redundant function, the potential point 14 is held at the ground potential as described above, and V _DD is applied to the signal input terminal 11.
supply. At this time, the MOS transistors 13,
18 are each in an on state. Now, if the fuse 15 is blown, no current will flow through the signal input terminal 11 as described above. On the other hand, if the fuse 15 is not blown, a current flows from the signal input terminal 11 toward the potential point 14 via the two MOS transistors 13 and 18 and the fuse 15 in series. Now, set the channel width of all MOS transistors 13, 17, and 18 in Figure 3 to 20μ.
m, when the channel length is set to 2 μm and the value of _VDD is set to +5V, a current of 50 μA or more flows from the signal input terminal 11.

Therefore, in this embodiment circuit, the use state of the redundant function can be determined by checking whether a current of 50 μA or more is flowing through the signal input terminal 11.

On the other hand, during actual use when the potential point 14 is held at V _DD , if the fuse 15 is not blown,
Since the potential of the drain or source terminal of the MOS transistor 18 on the fuse 15 side is maintained at approximately V _DD , both MOS transistors 13 and 18
Both are in an off state, and no current flows through both MOS transistors 13 and 18. On the other hand, when the fuse 15 is blown and the MOS transistor 17 is not provided, the MOS transistors 13 and 18 are each turned on. However, since fuse 15 is blown, no current flows through both MOS transistors 13 and 18 in this case as well. Therefore, during actual use, fuse 1
MOS transistor 13, regardless of the state of 5.
Since no current flows through 18, it does not adversely affect the internal circuit. Further, the MOS transistor 17 is provided to prevent the generation of displacement current due to noise or the like, as described above.

In the above embodiment circuit, one MOS transistor is inserted between the series connection point 16 and the fuse 15, but two or more MOS transistors may be inserted. And the gate terminals of these MOS transistors are
Similar to the MOS transistor 13, each MOS
It may be connected to the drain or source terminal of the transistor closer to the signal input terminal 11,
Alternatively, they may be commonly connected to the drain or source terminal of the MOS transistor 13 that is closer to the signal input terminal 11. As the number of MOS transistors inserted between the series connection point 16 and the fuse 15 increases, the value of the current flowing through the fuse 15 becomes smaller. In addition, it is inserted between the series connection point 16 and the fuse 15.
When the gate terminals of the MOS transistors are commonly connected as described above, the impedance of each gate terminal in the on state becomes lower than when the gate terminals are not commonly connected, and the flowing current increases.

FIG. 4 shows the structure of another embodiment of the present invention. In this embodiment circuit, the N-channel MOS transistor in the embodiment circuit shown in FIG. 3 is replaced with a P-channel MOS transistor. That is, in this embodiment circuit, the N
P-channel MOS transistors 23, 27, and 28 are provided corresponding to channel MOS transistors 13, 17, and 18, so that the potential point 14 is always held at the ground potential.

In this embodiment circuit, when checking the usage status of the redundant function, this is done by supplying a negative potential to the signal input terminal 11. The operation in this case is different only in that the direction of the current flowing through the fuse 15 is opposite to that in the case of FIG. 3, so a description thereof will be omitted.

Further, during actual use, a signal having a potential in the range between the ground potential and the positive power supply potential _VDD is supplied to the signal input terminal 11. At this time, regardless of whether or not the fuse 15 is blown, no current flows through the MOS transistors 23 and 28 as described above, so there is no adverse effect on the internal circuit. In addition,
Similarly to the above, the MOS transistor 27 in this embodiment is for preventing the generation of displacement current due to noise or the like, and if there is no risk of generation of noise or the like, this MOS transistor 27 can be omitted.

Note that this invention is not limited to the above-described embodiments, and various modifications are possible. For example, the MOS transistor 28 in the embodiment circuit shown in FIG. 4 may be removed to create a configuration corresponding to that shown in FIG. 2, or two or more MOS transistors may be inserted in series instead of one MOS transistor 28. You can.

Further, in the above embodiment, the fuse 15 is blown when the redundant function is used, but the fuse 15 may be blown when the redundant function is not used. In this case, a current is detected at the signal input terminal 11 when the redundancy function is used.

Furthermore, instead of the fuse 15 in each of the above embodiments, polycrystalline silicon, which is in a high resistance state immediately after manufacture, is provided, and this is selectively laser annealed depending on the use state of the redundant function to lower the resistance. You can.

〔Effect of the invention〕

As explained above, according to the semiconductor integrated circuit device according to the present invention, whether or not the redundant function is used is determined by checking the presence or absence of current at the signal input terminal. can be easily inspected from outside. Moreover, it does not affect the internal circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor memory equipped with a redundant function, FIG. 2 is a circuit diagram showing the configuration of a main part of an embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of another embodiment of the invention. FIG. 4 is a circuit diagram showing the configuration of another embodiment of the present invention. 11... Signal input terminal, 12... Input protection circuit, 13, 17, 18... N channel MOS transistor, 15... Fuse, 23, 27, 28
...P channel MOS transistor.

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit device having a redundant function, an impedance means having one end connected to a potential supply terminal and having an impedance changed according to the state of use of the redundant function, and the other end of the impedance means and the signal input terminal, the source and drain terminals are inserted between the gate terminal and the signal input terminal, and the gate terminal is supplied with a potential corresponding to the signal potential applied to the signal input terminal.
and a source or drain between the drain or source terminal of the transistor located closest to the signal input terminal of the first MOS transistor and the drain or source terminal of the transistor located at the position closest to the signal input terminal, and the potential supply terminal. A semiconductor integrated circuit device comprising: a second MOS transistor inserted between the terminals and having a gate terminal connected to the potential supply terminal. 2. The semiconductor integrated circuit device according to claim 1, wherein two or more of the first MOS transistors are provided. 3. Each gate terminal of the first MOS transistor is commonly supplied with the potential of the drain or source terminal of the first MOS transistor located closest to the signal input terminal, which is closer to the signal input terminal. A semiconductor integrated circuit device according to claim 2.