JPS6410949B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device constituted by a lateral structure static induction transistor.

The inventor of the present invention has already revealed that if one of the main electrodes of a vertical structure static induction transistor (hereinafter referred to as SIT) is made into a floating electrode to form a capacitance, the transistor immediately becomes a memory cell. (Japanese Unexamined Patent Publication No. 103330/1983 "Semiconductor Memory", Patent No.
1217658 "Semiconductor Memory", Patent No. 1207716 "Semiconductor Memory", Patent No. 1144576 "Semiconductor Memory"). Since memory is structured three-dimensionally,
The integration density is extremely high, making it extremely suitable for integrated circuits where high density is desired. However, for example, since the bit line is constructed from a region buried inside the semiconductor, it has the disadvantage that the capacitance of the bit line tends to increase.

Of course, these drawbacks can be removed by using an insulating substrate or utilizing insulating material separation, but
Manufacturing becomes a little more complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of high-speed writing, reading, or transfer using a lateral structure SIT that eliminates the above-mentioned drawbacks.

The present invention will be explained in detail below using the drawings.

Figure 1a shows a RAM (Random Access Memory) of the present invention using a horizontal n-channel SIT in which the source, gate, and drain are arranged on one surface.
FIG. 1b is a sectional view of an example of the structure, and FIG. 1b is a plan view of the structure mainly showing the electrode wiring. FIG. 1c is a plan view showing n ⁺ , p ⁺ , n ⁺ regions provided on the surface.
FIG. 1d shows an equivalent circuit of a memory cell. The n ⁺ region 11 constitutes a bit line, and the p ⁺ region 12 serves as a gate for opening and closing a channel and serves as a word line. The n ⁺ region 13 exchanges electrons with the n ⁺ region 11, forms a capacitance with an electrode 13' provided on the surface via the insulating layer 16, and accumulates charges. Electrode 13' is kept at a constant potential, usually at ground potential. The n ^- region 14 is a channel, and the p ⁺ region 15 is a substrate or a buried region, and operates as a fixed potential gate. 1
7 is an insulating layer, and 18 is an insulating layer that isolates each memory cell. p ⁺ n ^- narrowed to regions 12 and 15
The impurity density in the region is such that when the word line is at an off-state potential, the channel is pinched off, creating a high potential barrier, and when the word line is at an on-state potential, the n ⁺ region 11 (called the drain) and
The dimensions and impurity density are selected so that conduction occurs between n ⁺ regions 13 (referred to as sources). At the same time, when the word line is at an off-state potential, a punch-through state is prevented between the gate region 12 and the p ⁺ region 15. When an on-state voltage is applied to the word line and a positive voltage (for example, about +5 to 10 V) is applied to the bit line, electrons flow from the source region 13 toward the drain, and the source region 13 becomes positively charged. . When the word line changes to an off voltage and the channel closes, the charge on the source region 13 is maintained. At the time of reading, when an ON voltage is applied to the word line to open the channel, the voltage stored in the source flows to the bit line, increasing the bit line potential and increasing the potential of the sense amplifier (not shown) provided at the end of the bit line. (not detected). The insulating layer 16 is made of SiO ₂ ,
It is an insulating layer made of Si ₃ N ₄ , Al ₂ O ₃ , etc., or a stack of multiple layers thereof. The insulating layer 17 may be the above-mentioned insulating layer, or may be a resin-based insulator such as polyimide. Further, the isolation insulator 18 is a resin-based insulator such as SiO ₂ or polyimide. electrode 11',
12' and 13' are formed of metal such as Al or Mo or low resistance polysilicon.

FIG. 2 shows another example of the memory device of the present invention. FIG. 2a is a sectional view, and FIG. 2b is a plan view mainly showing the electrode wiring. The arrangement of n ⁺ and p ⁺ regions is
It is almost the same as Fig. 1c.

A feature of the structure shown in FIG. 2 is that the p ⁺ gate region 12 connected to the word line in FIG. 1 is used as a floating electrode. At the same time, p ⁺ below the p ⁺ gate region
A buried region 19 is provided. The channel dimensions and impurity density are selected such that the channel pinches off during operation, creating a potential barrier of appropriate height. In the example of FIG. 2, the bit line 11' is connected to the drain region 11, and the word line is constituted by an electrode 13' provided through a thin insulating layer on the surface of the source region. The p ⁺ region 19 may be a floating region or may have a fixed potential. The potential may be changed depending on the desired operation. When writing, a positive voltage (for example, +
When a voltage of about 5 to 10 V) is applied, electrons flow from the source region 13 to the drain region 11, and the source region 13 becomes positively charged. When the bit line voltage is removed, the potential barrier created in the channel causes
The charge in the source region is maintained. For memory cells to which writing is not desired, almost the same voltage can be applied to the word line at the same time as a positive voltage is applied to the bit line. Reading can be performed by applying a positive voltage to the word line.

1 and 2 show an example of a structure in which each memory cell is completely isolated from an insulator, but in order to simplify the surface electrode wiring, the bit line is connected to the n ⁺ region 11.
Sometimes it consists of only one. In that case, n ⁺
The region 11 is long and continuous in one direction, and it is sufficient that the region 11 is not separated by an insulating material.

It is desirable for a memory cell to have a large storage capacitance because it allows the memory cell to be made smaller and improves read sensitivity. By increasing the facing area between the source region and the electrode via the insulating layer,
FIG. 3 shows an example in which the storage capacitance is increased. It has a structure in which an electrode is provided within the separation region and a capacitance is also provided on the side surface of the n ⁺ region. The arrangement of bit lines and word lines is shifted by 90 degrees from that in FIG.

It goes without saying that the structure shown in FIG. 3 is also effective in the example shown in FIG.

Horizontal SIT enables CCDs (Charge Coupled Devices) that operate at extremely high speeds. This is a semiconductor memory device that can perform so-called charge transfer.

FIG. 4 shows an example of the structure of a semiconductor memory capable of charge transfer according to the present invention, which operates in four phases. Along the surface of the high resistance n ^- region 24 on the p ⁺ substrate 25, n ⁺ regions and p ⁺ regions are alternately provided. An insulating layer 1 is formed on the surfaces of the n ⁺ regions 21 and 22.
An electrode is provided through the p + region 23, and an ohmic electrode is provided in the p ⁺ region 23. The p ⁺ substrate may be in a floating state or may be provided with a predetermined potential. n ⁺
Every other region and p ⁺ region are wired. For example, when positive charges are accumulated in the leftmost n ⁺ region 22, when transferring positive charges to the rightmost n ⁺ region 21, the four-phase driving pulses are as shown in Figure 4b. Bye. A positive pulse that opens the channel is applied to _φ4 , and at the same time a positive voltage is applied to _φ2 . Electrons flow from the n ⁺ region 21 on the right to the n ⁺ region 22 on the left. That is, positive charges will be transferred to the right side. Next, when a positive direction pulse is applied to φ ₃ to open the channel and a positive direction voltage is applied to φ ₁ , positive charges are further transferred to the n ⁺ region 22 on the right side.

FIG. 4 shows a complicated four-phase drive operation.
FIG. 5 shows an example in which three-phase drive operation can be performed. The structure is such that a p ⁺ region 23 serving as a control electrode is provided adjacent to one of the adjacent n ⁺ regions. Assume now that positive charges are accumulated in the leftmost n ⁺ region 22. A positive voltage is applied to φ ₃ in the direction in which the channel opens. At the same time, when a positive voltage is applied to φ ₂ , electrons flow from the right n ⁺ region to region 22,
Positive charge is transferred to the right side. When a positive voltage is applied to φ ₃ and a positive voltage is applied to φ ₁ at the same time, positive charges are further transferred to the n ⁺ region 22 on the right side.

An example in which two-phase drive can be performed is shown in FIG. A p ⁺ buried region is provided near the boundary between the p ^- substrate 25' and the high resistance layer n ^- . The gate region 23 is provided adjacent to one of the n ⁺ regions as in the example shown in FIG ^.
This is an example in which a potential barrier position for controlling current is provided adjacent to one of the n ⁺ regions by introducing the buried region 27. In this example, the gate region 23 is provided with a floating potential or a predetermined constant potential. Of course, p ⁺ region 27 may also be at a floating potential or may be maintained at a predetermined constant potential.
Now, assume that positive charges are accumulated in the leftmost n ⁺ region 21. When a positive voltage is applied to φ ₁ , the right side n ⁺
Electrons flow in from region 22, and positive charges are transferred to the right side. When a positive voltage is applied to φ ₂ , positive charges are further transferred to the n ⁺ region 21 on the right side.

The impurity density in each region of FIGS. 1 to 6 is as follows:
n ⁺ region 11, 13, 21, 22: 10 ¹⁷ ~ 10 ²¹ cm ^-3 ,
p ⁺ regions 12, 23, 15, 25 are 10 ¹⁷ to 10 ²¹ cm ^-3
degree, n ^-regions 14 and 24 are about 10 ¹² to 10 ¹⁵ cm ^-3 ,
The p ^- region 25' is about 10 ¹³ to 10 ¹⁷ cm ^-3 . The thickness of the insulating layer on the high impurity density region constituting the storage capacitance is about 100 Å to 3000 Å.

In the semiconductor memory device for charge transfer of the present invention, carrier transfer is performed not by diffusion but mostly by drift caused by an electric field.
Compared to the case where charge transfer was performed by diffusion, the difference is that charge transfer depends on the applied voltage.
It is easy to transfer data at least one order of magnitude faster. Compared to the current MOS CCD, which has an upper limit of operating with a clock pulse of several MHz,
A transfer memory device that operates with a clock of several tens of MHz is realized.

It goes without saying that the semiconductor memory device of the present invention is not limited to the structure example described here. It goes without saying that a material whose conductivity type is completely reversed may be used. In short, a source, gate, and drain are provided on one surface of a high-resistance region, and it operates by raising or lowering the potential barrier that occurs in the channel using the gate voltage or source/drain voltage, or by completely opening the channel. Any structure is fine.
In the illustrated example, all channels are high-resistance regions of the same conductivity type as the source and drain regions, but a high-resistance region of the opposite conductivity type that is mostly punch-through may be interposed therebetween. Further, although all control electrodes are shown as junction type, they may be of shotgun type or insulated gate type.

The semiconductor memory device of the present invention can be manufactured using conventionally known crystal growth techniques, diffusion techniques, ion implantation techniques, microfabrication techniques, and the like.

The semiconductor memory device of the present invention, in which the source, gate, and drain, which are the constituent elements of the memory, are arranged on one surface of a high-resistance semiconductor region is easy to manufacture, can have a high degree of integration, and can operate at high speed. Its industrial value is extremely high.

[Brief explanation of drawings]

FIG. 1 is a structural example of the RAM of the present invention, a is a cross-sectional view, b is a plan view, c is a plan view, d is an equivalent circuit diagram,
FIG. 2 is another structural example of the RAM of the present invention, a is a cross-sectional view, b is a plan view, FIG. 3 is a cross-sectional structural example of an improved memory cell, and FIG. 4 is a charge transfer semiconductor of the present invention. An example of a memory device structure, a is a cross-sectional view, b is a timing chart, and FIGS. 5 and 6 are structural examples of a charge transfer semiconductor memory device of the present invention.

Claims (1)

[Claims] 1. A source consisting of a second conductivity type high impurity density semiconductor region formed within the surface of a second conductivity type high resistance semiconductor layer formed on a first conductivity type high impurity density semiconductor substrate. a gate region made of a first conductivity type high impurity density semiconductor region, and a drain region made of a second conductivity type high impurity density semiconductor region. The memory cell includes a bit line and a word line arranged in a matrix, and in the memory cell, the drain is connected to the bit line, the gate is connected to the word line, and the source region is connected to an insulating layer. A semiconductor memory device, characterized in that the semiconductor memory device is coupled to an electrode brought to a ground potential via an electrode. 2 A source region consisting of a second conductivity type high impurity density semiconductor region formed within the surface of a second conductivity type high resistance semiconductor layer formed on a first conductivity type high resistance semiconductor substrate, a drain region and a second conductivity type high impurity density semiconductor region. The memory cell includes at least one memory cell constituted by a horizontal static induction transistor including a first gate region made of a high impurity density semiconductor region of one conductivity type, and includes bit lines and word lines arranged in a matrix. , in the memory cell, the drain is connected to the bit line, the first gate region is at a floating potential, the source region is coupled to the word line through an insulating layer, and the second gate region is connected to the bit line. a first conductivity type high impurity density semiconductor buried region in a floating state to be provided at a junction between the semiconductor substrate and a second conductivity type high resistance semiconductor layer formed on the semiconductor substrate; Features of semiconductor memory device. 3 Along one direction of the surface of a high resistance region of an opposite conductivity type provided on a substrate of one conductivity type, a high impurity density region of the same conductivity type as the high resistance region and a high impurity density region of a conductivity type opposite to the high resistance region. 1. A semiconductor memory device characterized in that the semiconductor memory device is arranged through a control region formed by a semiconductor memory device, and an electrode is provided on the surface of the high impurity density region of the same conductivity type via an insulating layer to transfer charges. 4. The semiconductor memory device according to claim 3, wherein the control region is provided close to one of the mutually adjacent high impurity density regions of the same conductivity type. 5. A high impurity density region of a conductivity type opposite to the high impurity density region of the same conductivity type is buried between the control region and the other of the mutually adjacent high impurity density regions of the same conductivity type, separated from the control electrode. 5. The semiconductor memory device according to claim 4, wherein the semiconductor memory device is provided as a semiconductor memory device. 6. The semiconductor according to claims 3 to 5, characterized in that a plurality of charge transfer columns each consisting of the high impurity density region of the same conductivity type and the control region are arranged in one direction. memory device.