JPS6410962B2 - - Google Patents
Info
- Publication number
- JPS6410962B2 JPS6410962B2 JP11268679A JP11268679A JPS6410962B2 JP S6410962 B2 JPS6410962 B2 JP S6410962B2 JP 11268679 A JP11268679 A JP 11268679A JP 11268679 A JP11268679 A JP 11268679A JP S6410962 B2 JPS6410962 B2 JP S6410962B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- time constant
- constant circuit
- differential
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 13
- 238000009499 grossing Methods 0.000 claims 2
- 230000000087 stabilizing effect Effects 0.000 claims 1
- 239000003990 capacitor Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 238000007599 discharging Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/02—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal
- H03D3/04—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal by counting or integrating cycles of oscillations
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manipulation Of Pulses (AREA)
- Circuits Of Receivers In General (AREA)
Description
【発明の詳細な説明】
本発明はFM検波器に関し特にパルスカウント
型FM検波器に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an FM detector, and more particularly to a pulse count type FM detector.
パルスカウント型FM検波器は第１図にそのブ
ロツク図を示す如く、IF（中間周波）信号をリミ
ツタ１において矩形波に変換して、この矩形波を
微分回路２により幅の狭いパルスに変換して、次
の単安定マルチ３をトリガして微分パルスに応じ
て均一のパルス幅を有するパルス列を得るもので
ある。すなわち、このパルス列は入力FM波の周
波数に対応した繰返し周波数を有することにな
り、このパルス列をLPF（低域フイルタ）４によ
つて平滑化しアンプ５で増幅すればFM検波出力
が得られるものである。 As shown in the block diagram of Fig. 1, the pulse count type FM detector converts an IF (intermediate frequency) signal into a rectangular wave in a limiter 1, and converts this rectangular wave into a narrow pulse by a differentiating circuit 2. Then, the next monostable multi 3 is triggered to obtain a pulse train having a uniform pulse width according to the differential pulse. In other words, this pulse train has a repetition frequency corresponding to the frequency of the input FM wave, and if this pulse train is smoothed by an LPF (low-pass filter) 4 and amplified by an amplifier 5, an FM detection output can be obtained. be.
第２図はかゝるパルスカウント型FM検波器の
単安定マルチ３の部分を具体的に回路例を掲げて
示した図であり、第１図と同等部分は同一符号に
より示されている。微分回路２の微分パルスは２
入力NORゲート３１の１入力となり、このNOR
ゲート出力は単安定パルスの幅を定める時定数回
路を構成するコンデンサC1の充放電制御用のト
リガとなつている。この時定数回路のコンデンサ
C1の充電のために抵抗R1が設けられて、時定数
C1・R1によりパルス幅が定まる。この時定数回
路のコンデンサC1の端子電圧を基準電圧Ｅと比
較する差動接続構成の比較器が設けられており、
これは差動対トランジスタTR1，TR2、電流源I1
及び抵抗R2，R3よりなつている。トランジスタ
TR1のコレクタ出力がNORゲート３１の他入力
となつていわゆる正帰還がなされ、もつてトラン
ジスタTR2のコレクタ出力から均一なパルス幅を
有する単安定マルチ出力であるパルス列が導出さ
れるものである。尚、TR5はコンデンサC1の充
電々荷を周期的に放電リセツトするトランジスタ
である。そしてこのパルス列をコンデンサC2を
介してLPF４へ入力して平滑化しFM検波出力が
得られる。 FIG. 2 is a diagram showing a concrete example of the circuit of the monostable multi 3 part of such a pulse count type FM detector, and the same parts as in FIG. 1 are indicated by the same reference numerals. Differential pulse of differentiating circuit 2 is 2
This NOR becomes one input of the input NOR gate 31.
The gate output serves as a trigger for controlling the charging and discharging of capacitor C1 , which constitutes a time constant circuit that determines the width of the monostable pulse. Capacitor of this time constant circuit
A resistor R 1 is provided for charging C 1 and the time constant
The pulse width is determined by C 1 and R 1 . A comparator with a differential connection configuration is provided to compare the terminal voltage of the capacitor C1 of this time constant circuit with the reference voltage E.
This is a differential pair of transistors TR 1 , TR 2 and a current source I 1
and resistors R 2 and R 3 . transistor
The collector output of TR 1 becomes the other input of the NOR gate 31 and so-called positive feedback is performed, and a pulse train that is a monostable multi-output having a uniform pulse width is derived from the collector output of transistor TR 2 . . Note that TR5 is a transistor that periodically discharges and resets the charge of the capacitor C1 . This pulse train is then input to the LPF 4 via the capacitor C 2 and smoothed to obtain an FM detection output.
かゝる回路構成において、トランジスタTR1及
びTR2より成る差動接続構成の差動出力の一方を
時定数回路へフイードバツクして単安定機能を行
わせるのに用いており、他方の出力を検波出力を
得るための単安定出力として用いているものであ
り、単一の差動回路を単安定を動作させるための
機能とFM検波出力を得るための機能とを併用し
ていることになる。従つて、単安定機能に必要な
パルス応答特性及びそれに必要な振幅特性を得る
ための電流源I1の電流値を決定すれば、FM検波
出力のＳ／Ｎを最良とするために必要な電流源I1
の電流値が得られないことになつて、両者を共に
満足させることは不可能である。 In such a circuit configuration, one of the differential outputs of the differential connection configuration consisting of transistors TR 1 and TR 2 is used to feed back to the time constant circuit to perform a monostable function, and the output of the other is used for detection. It is used as a monostable output to obtain an output, and a single differential circuit is used in combination with the function of operating a monostable and the function of obtaining an FM detection output. Therefore, by determining the current value of current source I1 to obtain the pulse response characteristics necessary for the monostable function and the amplitude characteristics necessary for it, the current value required to optimize the S/N of the FM detection output can be determined. Source I 1
Therefore, it is impossible to satisfy both conditions.
更に、差動回路の一方の出力のみからパルス列
出力を取り出さざるを得ないために、差動回路の
能力を十分に利用できず、出力振幅も小となつて
効率の低下を招来している。 Furthermore, since the pulse train output must be extracted from only one output of the differential circuit, the capability of the differential circuit cannot be fully utilized, and the output amplitude becomes small, resulting in a decrease in efficiency.
本発明の目的は上記欠点を排除して特性の良好
なFM検波出力を得ることが可能なパルスカウン
ト型FM検波器を提供することである。 An object of the present invention is to provide a pulse count type FM detector that can eliminate the above-mentioned drawbacks and obtain an FM detection output with good characteristics.
本発明のパルスカウント型FM検波器はパルス
列発生手段としての単安定マルチ部分を改良した
ものであつて、パルス幅を定める時定数回路と共
に単安定機能をなす第１の比較器と、時定数回路
の出力と基準電圧とを比較してFM検波用の出力
パルス列を発生する例えば差動増幅器構成の第２
の比較器とを含むことを特徴としている。 The pulse count type FM detector of the present invention is an improved monostable multi-section as a pulse train generation means, and includes a first comparator that performs a monostable function together with a time constant circuit that determines the pulse width, and a time constant circuit. For example, a second circuit in a differential amplifier configuration that generates an output pulse train for FM detection by comparing the output of the
It is characterized by including a comparator.
以下に本発明を図面を用いて説明する。 The present invention will be explained below using the drawings.
第３図は本発明の実施例を示す回路図であり、
第２図と同等部分は同一符号により示されてい
る。図において、差動接続されたトランジスタ
TR1とTR2、電流源I1及び抵抗R2よりなる第１の
比較器が時定数回路（コンデンサC1と抵抗R1）
と協働して単安定機能をなすように構成されてお
り、別の差動接続されたトランジスタTR3と
TR4、電流源I2及び抵抗R7，R8より成る第２の比
較器がパルス列出力を発生するよう構成されてい
る。すなわち、時定数回路のコンデンサC1の充
放電電圧と基準電圧Ｅとが差動トランジスタTR3
及びTR4の各ベース差動入力となり、これら各コ
レクタ間出力が差動出力として取り出される。こ
の差動出力間のコンデンサC3は積分用として用
いられており、パルス列出力を積分して次段のア
ンプ５へ直結して印加している。 FIG. 3 is a circuit diagram showing an embodiment of the present invention,
Parts equivalent to those in FIG. 2 are designated by the same reference numerals. In the figure, differentially connected transistors
The first comparator consisting of TR 1 and TR 2 , current source I 1 and resistor R 2 is a time constant circuit (capacitor C 1 and resistor R 1 )
It is configured to perform a monostable function in cooperation with another differentially connected transistor TR 3 .
A second comparator consisting of TR 4 , current source I 2 and resistors R 7 and R 8 is configured to generate a pulse train output. That is, the charging/discharging voltage of the capacitor C1 of the time constant circuit and the reference voltage E are connected to the differential transistor TR3.
and TR 4 base differential inputs, and these collector-to-collector outputs are taken out as differential outputs. A capacitor C 3 between the differential outputs is used for integration, and the pulse train output is integrated and directly connected to and applied to the amplifier 5 at the next stage.
このアンプ５はオペアンプ５１と抵抗R5，R6
より成り、この増幅出力をLPF４を介して平滑
化せしめFM検波信号としている。 This amplifier 5 consists of an operational amplifier 51 and resistors R 5 and R 6
This amplified output is smoothed through the LPF 4 to become an FM detection signal.
このように比較器を単安定機能用の比較器と、
FM検波出力を得るためのパルス列発生用の比較
器とに分離して設けたことにより、それぞれの電
流源I1及びI2を独立に設計することが可能となる
ので、単安定動作に要求される電流値を最適とす
ることができると共に、FM検波用出力に必要な
特性を得るように電流値を最適に設定することが
できる。 In this way, the comparator can be used as a comparator for monostable function,
By providing a separate comparator for pulse train generation to obtain the FM detection output, it is possible to design each current source I1 and I2 independently, which is required for monostable operation. The current value can be optimized, and the current value can be optimally set to obtain the characteristics necessary for the output for FM detection.
更には、差動出力として取り出すことができる
ので、差動回路の能率を十分に利用できることに
なると共に出力信号のレベルをも適当に定められ
るので次段回路との直結が可能となつて広帯域の
検波特性とすることができる。 Furthermore, since it can be output as a differential output, it is possible to fully utilize the efficiency of the differential circuit, and the level of the output signal can also be determined appropriately, allowing direct connection to the next stage circuit, allowing broadband It can be a detection characteristic.
以上の如く、本発明によればパルス応答特性も
良好でかつＳ／Ｎも最適とすることができ、差動
出力も得られ、更にはDC直結アンプ構成としう
るので、いわゆるHi−FiのFMチユーナが得られ
ることになる。 As described above, according to the present invention, the pulse response characteristics are good, the S/N can be optimized, differential output can be obtained, and furthermore, a DC direct-coupled amplifier configuration is possible, so the so-called Hi-Fi FM Chiyuna will be obtained.
第１図はパルスカウント型FM検波器のブロツ
ク図、第２図は従来のパルスカウント型FM検波
器の一部具体例を示す回路図、第３図は本発明の
実施例を示す回路図である。
主要部分の符号の説明、２……微分回路、３…
…単安定マルチ、４……LPF、TR1〜TR5……ト
ランジスタ、C1……時定数回路のコンデンサ、
R1……時定数回路の抵抗。
Fig. 1 is a block diagram of a pulse count type FM detector, Fig. 2 is a circuit diagram showing a partial example of a conventional pulse count type FM detector, and Fig. 3 is a circuit diagram showing an embodiment of the present invention. be. Explanation of the symbols of the main parts, 2...Differential circuit, 3...
...monostable multi, 4...LPF, TR 1 to TR 5 ...transistor, C 1 ...capacitor of time constant circuit,
R 1 ...Resistance of time constant circuit.
Claims (1)
分出力に応じて均一のパルス幅を有するパルス列
を発生するパルス列発生手段とを含み、このパル
ス列を平滑してFM検波出力をうるパルスカウン
ト型FM検波器であつて、前記パルス列発生手段
は、 前記パルス幅を定める時定数回路と、 この時定数回路の出力と基準電圧とが各々のベ
ースに入力される差動対構成の第１、第２のトラ
ンジスタより成り前記第１のトランジスタの出力
から前記時定数回路に対して正帰還を施し該時定
数回路出力と基準電圧とを比較することによつて
前記時定数回路と共に単安定機能をなす第１の差
動増幅器と、 前記時定数回路の出力と基準電圧とが各々のベ
ースに入力される差動対構成の第３、第４のトラ
ンジスタより成り該時定数回路出力と基準電圧と
を比較する第２の差動増幅器 とを含み、前記第２の増幅器の差動出力を平滑化
してFM検波出力とすることを特徴としたパルス
カウント型FM検波器。[Scope of Claims] 1. Includes differentiating means for differentiating an FM received signal, and pulse train generating means for generating a pulse train having a uniform pulse width according to the differentiated output, and smoothing this pulse train to generate an FM detection output. The pulse train generation means includes a time constant circuit that determines the pulse width, and a differential pair configuration in which the output of the time constant circuit and a reference voltage are input to respective bases. It consists of a first transistor and a second transistor, and by applying positive feedback to the time constant circuit from the output of the first transistor and comparing the output of the time constant circuit with a reference voltage, It consists of a first differential amplifier that performs a stabilizing function, and third and fourth transistors in a differential pair configuration in which the output of the time constant circuit and a reference voltage are input to the bases of each, and the output of the time constant circuit and the reference voltage are input to the bases of each transistor. A pulse count type FM detector, comprising a second differential amplifier for comparing the voltage with a reference voltage, and smoothing the differential output of the second amplifier to obtain an FM detection output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11268679A JPS5636205A (en) | 1979-09-03 | 1979-09-03 | Pulse count type fm detector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11268679A JPS5636205A (en) | 1979-09-03 | 1979-09-03 | Pulse count type fm detector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5636205A JPS5636205A (en) | 1981-04-09 |
| JPS6410962B2 true JPS6410962B2 (en) | 1989-02-22 |
Family
ID=14592929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11268679A Granted JPS5636205A (en) | 1979-09-03 | 1979-09-03 | Pulse count type fm detector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5636205A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4253735B2 (en) * | 2000-05-12 | 2009-04-15 | Ｏｋｉセミコンダクタ株式会社 | Digital / analog converter |
-
1979
- 1979-09-03 JP JP11268679A patent/JPS5636205A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5636205A (en) | 1981-04-09 |
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