JPS6412025B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sector check circuit for a memory disk of an electronic computer, and more particularly to the same circuit when the rotation of the disk deviates from a reference speed. Generally, when a magnetic disk is used for memory, as shown in FIGS. 1 and 2, a sector disk 1 has a notch 2 for deriving an index signal and a notch 3 for deriving a sector signal. It is done at regular intervals. The notches 2 and 3 are detected by the sensor 4 and added to the detection circuit 5. If the period is within a certain range, a predetermined density is applied to the memory disk 6 coaxially provided on the sector disk 1. Data is written by . However, when the frequency of the power source is low, the rotation of the motor 7 becomes slow and the interval between sector signals from the notch 3 becomes long, and the data written to the memory disk 6 becomes dense. (In the case of a period of 520 μs when the power supply frequency is 50 Hz as shown in FIG. 3) On the other hand, when the frequency is high, the rotation of the motor 7 becomes faster and the interval between sector signals from the notch 3 becomes shorter. The data written to the disk becomes sparse, and there is a possibility that it may extend to the next sector (in the case of a period of 463 μs when the power frequency is 50 Hz as shown in FIG. 3). In FIG. 1, 8 is a head selection circuit, and 9 is a head selection circuit.
10 is a central control device such as a microcomputer, 11 is a power plug, and 12 is a brake means. Furthermore, in accordance with the conditions for using the memory disk, the entire system is turned on in about 2 seconds after turning on the AC and DC power, and at this time, the device on signal is generated from the control device 10, and the rotation speed of the memory disk 6 is changed. is 1000rpm. It takes about 30 seconds (maximum 60 seconds) after this device-on signal is generated for the rotation speed to become normal. Write W and read R after this time has elapsed.
Unless this is done, there is no data guarantee. Therefore, it takes 30 to 60 seconds for the computer system to be usable after the power is turned on, and if only the DC power line is turned off and on while the AC power for the disk is turned on, it will take less time to use. Both memory disks are spinning normally, so there should be no need to wait 30 to 60 seconds. The present invention provides a novel sector check circuit for a memory disk of an electronic computer which eliminates the above-mentioned drawbacks. The following description will be given with reference to the drawings. FIG. 4 is a block diagram of the circuit of the present invention, and FIGS. In FIG. 4, 13 is a sector signal application terminal;
14 is an extraction circuit, 15 and 16 are JK flip-flops, 17 is an address counter AD counter, 18 is a read-only memory ROM, 19 is a delay flip-flop as a latch means,
20 is a reset signal output terminal, 21 is an AND gate, 22 and 23 are AND gates, 24 is a negative write clock signal terminal, 25 is a positive write clock signal application terminal, 26 is a clock signal application terminal, 27 indicates a sector error signal output terminal. Next, the circuit of the present invention will be explained using the timing chart shown in FIG. First, a write clock signal (positive polarity) shown in FIG. 5A is applied to terminal 25, a write clock signal (negative polarity) is applied to terminal 24, and the
A clock signal is added to 6. At this time, when the sector signal (FIG. 5B, negative polarity) obtained by the notch 3 provided on the sector disk 1 is applied to the cutout circuit 14 via the terminal 13, the falling edge of the sector signal SECT A cutout signal S is generated from the cutout circuit 14 using the clock signal CLK. At this time, when the power supply frequency is 50Hz, the selection switches 28 and 29 are set to the 1 and 2 sides, respectively, and the sector check signals SC1 and SC2 shown in FIG.
2 and flip-flop 19. As a result, the check signal SC1 has a pulse width of 461μ (202 steps of the clock signal), and the pulse width of SC2 has a pulse width of 520μ (228 steps of the clock signal), respectively, as the sector signal.
It plays the role of checking the side of SECT and checking the delay of sector signal. As an example, when the power supply frequency is 50Hz as described above, the check signal SC1 is logic "1" from address 0 to address 202, and logic "0" from address 203 thereafter.
The check signal SC2 is stored as data in the ROM 18 as data, and the check signal SC2 is logic "1" from address 0 to address 228, and logic "0" from address 229 after that.
It is stored as data in the ROM 18 so that The timing for starting the ROM 18 from address 0 is the fall of the sector signal SECT, and in FIG.
The signal is extracted by the extraction circuit 14 at CLK, and the extraction signal S shown in FIG. 5C is obtained as its output. The cutout signal S is output from the flip-flop 15.
In addition, the cutout signal S is delayed by one clock, and the reset signal R appears as its output. By the reset signal R, the A-D counter 1
7 is reset, and the reset signal R and the sector check signal SC1 are sent to the NAND gate 22.
The sector check signal SC2 is applied to the flip-flop 16 via the delay flip-flop 19 as a latch circuit, and its output signal is sent to the terminal 27.
The sector error signal ER shown in FIG. Therefore, the sector check signal SC1 is logic “0”.
to “1” and the sector check signal SC
1 and the cutout signal S is established, and even though the notch for the sector is detected at the normal position, an error signal is generated and the error signal is latched in the delay flip-flop 19. This is because Note that the 2.28 μs width clock signal applied to the clock terminal 26 is generated by a clock signal generation circuit (including a step-down circuit from the reference oscillator) connected to the clock terminal 26.
This is a pulse signal obtained from Next, the reason why the sector check signal SC2 is latched to the delay flip-flop 19 will be explained below. If the sector signal does not come to the check circuit, it is detected as an error that the delay flip-flop 19
The error signal is latched. With that output A-D
The clock (2.28 μs) of counter 17 is turned off. By doing so, the address of the ROM 18 is fixed at the error address, and the sector check signal SC2 of the ROM 18 also remains outputting an error (remains "0"). Therefore, by latching the delay flip-flop 19, the error can be set immediately even if the central control unit 10 unlatches the error signal flip-flop 16. If an error signal is generated after the sector check, an alarm device, for example, a warning light is turned on or a sound is emitted from the alarm means to notify the operator of an abnormality in the sector, that is, an abnormality in the rotational speed of the motor. If a sector error occurs, if the error signal output from the check circuit described above closes the write gate circuit, the data on the memory disk can be protected by always setting it as an error. I can do it. In the above example, the selection switches 28 and 29 were set to the side when the power frequency was 50 Hz. However, when the power frequency was 60 Hz, the selection switches 28 and 29 were set to the side and the sector check signal was set to the side. The pulse width of SC1 is set to 392 μs (172 steps of the clock signal). Sector check signal SC2
pulse width of 440 μs (193 steps of clock signal)
You can get exactly the same effect by setting it to . As described above, according to the present invention, the rotation of a memory disk can be detected and analyzed by a central control device in a short period of time, and can be done accurately. There is no waiting time required, leading to improved work efficiency,
The check circuit of the present invention can be extremely effective in detecting the rotation of a memory disk in an electronic computer.

[Brief explanation of drawings]

Fig. 1 is a block diagram for the present invention, Fig. 2 is a sector disk, Fig. 3 is an explanatory waveform diagram of the present invention, and Fig. 4 is a block diagram for the present invention.
The figure shows a sector check circuit for a memory disk of an electronic computer according to the present invention, and FIGS. Explanation of main drawing numbers, 1 ... Sector disc, 2...
Notch for index, 3... Notch for sector, 6... Memory disk, 13... Sector signal application terminal, 14... Extraction circuit, 15, 16...
...J-K flip-flop, 17...address counter (A-D counter), 18...read-only memory ROM, 19...delay flip-flop, 20...sector error signal output terminal.

Claims (1)

[Claims] 1 Comprising a memory disk driven by a motor, a sector disk in which notches are provided at regular intervals, a sensor for detecting the notches, and a detection circuit to which a detection signal from the sensor is applied. In the memory disk device, the sector signal from the notch is applied to a flip-flop circuit via an extraction circuit to derive a reset signal, and an address counter connected to the output side of the flip-flop circuit is reset by the reset signal; A plurality of check signals having different periods of high or low level stored in a predetermined location of the read-only memory are read out, and the check signals and the sector signal of the detection circuit are added to a comparison means to determine whether the sector signal deviates from the predetermined time. A sector check circuit for a memory disk of an electronic computer, which is characterized by deriving an error signal.