JPS6412040B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ROM output read circuit for latching the output of a ROM (read only memory).

FIG. 1 shows a conventional example of a ROM section in a microcomputer, for example, where 11 is a dynamic ROM, 12 is an address decoder, and 13 is an output latch circuit. φ _ADR is the precharge signal of address decoder 12, φ _ROM
is the precharge signal of the ROM 11, φ _R is the latch signal of the latch circuit 13, and φ _W is the address decoder 1
These drive signals are generated at the timing shown in FIG. 2, for example. In addition, in Fig. 2, φ ₁ and φ ₂ are two-phase clocks, and RTN
is a control signal generated in synchronization with the above clock φ ₂ in the last basic cycle of a certain instruction cycle of the CPU of a microcomputer, such as a return signal, RTN ₁ is the above RTN until the clock φ _{1 following the clock φ 2 corresponding} to the above RTN is a delayed return signal, RTN ₂ is a return signal delayed by RTN ₁ until clock φ ₂ following clock φ ₁ corresponding to RTN ₁ ,
In other words, the RTN is 1 bit (basic cycle)
This is the return signal delayed by 1 minute. Here, the drive signal φ _W includes a return signal RTN ₂ and a clock φ ₁
The latch signal φ _R is the AND output of the return signal RTN ₁ and the clock φ ₂ .

In the above ROM section, return signal RTN ₂
After the address decoder 12 and ROM11 are precharged by the precharge signals φ _ADR and φ _ROM synchronized with the address decoder 12 and ROM 11, the drive signal φ _W specifies the address of the ROM 11 according to the address input signal A _i , and the ROM 11 is in a state ready for output. become. Then, the ROM11 is activated by the next generated latch signal _φR .
It is latched by the output latch circuit 13 of.

By the way, the above-mentioned latch signal φ _R is in a state where the ROM 11 can output from the drive signal φ _W when the return signal RTN is generated at an interval of 4 bits (for example, one machine cycle) as shown in FIG. It occurs 4 bits after the
The ROM output can be latched before being discharged. However, in processing a certain opcode, the return signal RTN is 8
It may occur only once per bit (for example, two machine cycles), and in this case, the return signals RTN ₁ , RTN ₂ , drive signal φ _W , latch signal φ _R ,
The precharge signals φ _ADR and φ _ROM are also generated only once every 8 bits. Therefore, when the latch signal φ _R is generated 8 bits after the drive signal φ _W makes the ROM 11 ready for output, the ROM output may have been discharged and normal latching may not be performed. .

In other words, conventionally, the control signal (in this example, the return signal) involved in determining the read timing of the ROM
RTN) occurs irregularly, such as once every 4 bits or once every 8 bits, when the
Unable to latch ROM output.

The present invention has been made in order to eliminate the above-mentioned drawbacks, and even if the control signals involved in determining the read timing of the ROM are generated irregularly, the minimum interval between the occurrences of the control signals is more than one basic cycle of the ROM read operation. The first latch signal is delayed for a short time by
The ROM output can be accurately latched by performing a two-stage latch in which the ROM output is latched and the contents of the latch are latched and output using a second latch signal prior to the next address specification.
It provides a ROM output read circuit.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

The ROM output readout circuit shown in FIG. 3 is different from the circuit described above with reference to FIG.
The latch signal φ _R is supplied to the second latch circuit 32, and the return signal RTN is output by 3 bits, which is one basic cycle shorter than the minimum interval (4 bits) of the generation interval of the return signal RTN.
Return signal equivalent to RTN ₂ delayed
The difference is that the latch signal φ _A , which is the AND output of RTN ₃ and clock φ _1, is supplied to the first latch circuit 31, and the other parts are the same, so the parts in FIG. 3 are the same as those in FIG. 1. are given the same reference numerals and their explanations will be omitted. Note that the second latch circuit 32
corresponds to the latch circuit 13 in FIG.

In the above configuration, even if the return signal RTN is generated every 8 bits as shown in FIG. 4, the latch signal φ will be generated 3 bits after the ROM 11 becomes ready for output by the drive signal φ _W. Since the ROM output is latched by the first latch circuit 31 due to _A , the ROM output is not discharged and data is not lost, and latching is performed normally. Then, the above latch signal _φA
Subsequently, as shown in FIG. 4, in this example, the output of the first latch circuit 31 is switched to _the second latch by _{the latch signal φ R at} the timing of clock φ ₂ , which is 6 bits after the latch signal φ A and before the clock φ 1. It is latched in circuit 32 and is derived as a readout output.

Furthermore, if the return signal RTN is generated every 4 bits as described above with reference to FIG.
(shown by the dotted line in the figure), following the latch by the latch signal φ _A , the latch signal φ _R is performed at the timing of clock φ ₂ two bits later, and the drive signal φ is activated at the timing of the next clock φ ₁ . _W allows the next address to be specified, and again a normal latch occurs before the ROM output is discharged.

As described above, according to the ROM output readout circuit of the present invention, even if the return signal occurs irregularly, such as once every 4 bits or once every 8 bits,
Return signal after ROM becomes ready for output
After one basic cycle shorter than the minimum RTN generation interval, the ROM output is latched by the first latch signal φ _A , and the above-mentioned latch contents are latched by the second latch signal φ _R prior to the next address specification. Since it uses a two-stage latch that latches and outputs the ROM output, it can be accurately latched before the ROM output is discharged, and the readout output is accurate, making it suitable for microcomputers etc. using this circuit. Normal operation can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a conventional ROM output readout circuit, Fig. 2 is a timing chart shown to explain the operation of Fig. 1, and Fig. 3 is a diagram according to the present invention.
FIG. 4 is a block diagram showing one embodiment of the ROM output readout circuit, and FIG. 4 is a timing chart shown to explain the operation of FIG. 3. 11...ROM, 31...first latch circuit, 3
2...Second latch circuit.

Claims (1)

[Claims] 1 A first latch circuit provided on the output side of a ROM (read only memory) and latching the ROM output using a first latch signal; a second latch circuit latching the output of the first latch circuit using a second latch signal; means for generating a delayed control signal that is delayed by one basic cycle of a ROM read operation than the minimum interval between occurrences of the control signal with respect to the control signal for determining the read timing of the ROM; and a delay caused by the means. Means for generating the first latch signal by logical processing of a control signal and a first phase clock, and generating the second latch signal in synchronization with a second phase clock delayed by one basic cycle from the generation timing of the control signal. 1. A ROM output reading circuit comprising: means for reading.