JPS6412140B2 - - Google Patents
Info
- Publication number
- JPS6412140B2 JPS6412140B2 JP57072758A JP7275882A JPS6412140B2 JP S6412140 B2 JPS6412140 B2 JP S6412140B2 JP 57072758 A JP57072758 A JP 57072758A JP 7275882 A JP7275882 A JP 7275882A JP S6412140 B2 JPS6412140 B2 JP S6412140B2
- Authority
- JP
- Japan
- Prior art keywords
- code
- pseudo
- spread spectrum
- synchronization
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 25
- 238000001228 spectrum Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 11
- 230000010363 phase shift Effects 0.000 claims description 2
- 238000007796 conventional method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005311 autocorrelation function Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J13/00—Code division multiplex systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
Description
【発明の詳細な説明】
この発明は、スペクトラム拡散受信機における
受信信号の同期方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for synchronizing received signals in a spread spectrum receiver.
一般に、スペクトラム拡散受信機において、受
信信号を復調する過程では、内部で発生させる局
部擬似雑音信号の同期を受信信号に対して高い同
期検出率で、かつ短時間に確立させることが望ま
れる。従来、この種の同期回路は、局部擬似雑音
信号を発生させ、この信号の位相を周期的にある
微少量だけスリツプさせながら、受信信号を相関
検出により捕捉する方法が採られている。また、
同期の捕捉後、同期状態を維持するための追跡回
路も付加されている。 Generally, in a spread spectrum receiver, in the process of demodulating a received signal, it is desired to establish synchronization of an internally generated local pseudo-noise signal with respect to the received signal at a high synchronization detection rate and in a short time. Conventionally, this type of synchronization circuit generates a local pseudo-noise signal, periodically slips the phase of this signal by a certain minute amount, and captures a received signal by correlation detection. Also,
Tracking circuitry is also added to maintain synchronization after synchronization is acquired.
このような従来例は、第1図に見られるよう
に、電圧制御発振器10からクロツク信号が局部
擬似雑音符号発生回路12に与えられ、クロツク
制御回路13を介してn段シフトレジスタ15に
入力される。擬似雑音符号は、n段シフトレジス
タ15の最終段出力と特定の段間出力とを排他的
論理和回路16を介して初段に帰還することによ
つて発生する。n段シフトレジスタ15の1ビツ
ト隣り合つた出力と1/2ビツトシフトレジスタ1
1とにより、位相関係が固定量シフトされた3種
の符号系列d,eおよびfが得られる。これらの
符号はスペクトラム拡散された受信信号RXSSを
3個の相関器1〜3で各各逆拡散し、包絡線検波
器4〜6で相関検出される。検出された3種の相
関出力a,bおよびcは、同期検出回路14にお
いて同期検出の判定に用いられ、同期が生ずるま
で局部符号の位相をスリツプさせるようにクロツ
ク制御回路13を制御し、同期が検出されると、
サーチ操作を停止させる。同期捕捉後、相関検出
出力a,cは同期を維持するために、遅延ロツク
ループの相関弁別回路8およびループフイルタ9
を通して電圧制御発振器10に与えられ、ここで
発振出力の位相が制御される。又、相関器1の出
力は、擬似雑音符号の極性の反転により得られる
情報信号のベースバンドを復調のために、帯域通
過フイルタ7を介して逆拡散された信号DESSと
して出力側に送出される。 In such a conventional example, as seen in FIG. Ru. The pseudo-noise code is generated by feeding back the final stage output of the n-stage shift register 15 and a specific inter-stage output to the first stage via the exclusive OR circuit 16. 1-bit adjacent outputs of n-stage shift register 15 and 1/2-bit shift register 1
1, three types of code sequences d, e, and f whose phase relationships are shifted by a fixed amount are obtained. These codes are obtained by despreading the spread spectrum received signal RXSS by three correlators 1 to 3, and detecting the correlation by envelope detectors 4 to 6. The detected three types of correlation outputs a, b, and c are used in the synchronization detection circuit 14 to determine synchronization detection, and the clock control circuit 13 is controlled to slip the phase of the local code until synchronization occurs. is detected,
Stop the search operation. After synchronization acquisition, the correlation detection outputs a and c are sent to the correlation discrimination circuit 8 and loop filter 9 of the delay lock loop in order to maintain synchronization.
is applied to the voltage controlled oscillator 10 through the oscillator, where the phase of the oscillation output is controlled. Further, the output of the correlator 1 is sent to the output side as a despread signal DESS via a bandpass filter 7 in order to demodulate the baseband of the information signal obtained by inverting the polarity of the pseudo-noise code. .
しかし乍ら、この方法によれば、同期検出の機
会は擬似雑音符号の1周期に1度しかなく、特に
符号周期が長い場合、全符号を位相シフトしてサ
ーチする過程で検出誤りを生ずることが多く、同
期確立に長時間を要するという欠点があつた。 However, according to this method, the opportunity for synchronization detection is only once per period of the pseudo-noise code, and especially when the code period is long, detection errors may occur during the process of searching by phase shifting all codes. The problem was that it took a long time to establish synchronization.
この発明の目的は、上記従来の欠点を除去し、
同期検出の確率が高く、かつ短時間で同期を確立
することのできるスペクトラム拡散受信機の同期
方式を提供するにある。 The purpose of this invention is to eliminate the above-mentioned conventional drawbacks,
An object of the present invention is to provide a synchronization method for a spread spectrum receiver that has a high probability of synchronization detection and can establish synchronization in a short time.
本発明によれば、情報化された最長線形系列の
擬似雑音符号により変調されたスペクトラム拡散
信号の受信機において、前記最長線形系列の擬似
雑音符号と該擬似雑音符号を位相シフトした符号
との2を法とする和をとることによつて、元の符
号系列を別の大きさだけ位相シフトする複数個の
符号系列を発生させる手段と、該発生手段から得
られるそれぞれの符号系列を選択する手段とを含
み、該選択手段により選択されたそれぞれの出力
を情報信号の復調および遅延ロツクループ用に備
えられる複数個の相関器に対応させ、これ等の相
関器に加えられるスペクトラム拡散信号を相関検
出することを特徴とするスペクトラム拡散受信機
の同期方式が得られる。 According to the present invention, in a receiver for a spread spectrum signal modulated by a pseudo-noise code of the longest linear sequence converted into information, a pseudo-noise code of the longest linear sequence and a code obtained by phase-shifting the pseudo-noise code of the longest linear sequence are combined. means for generating a plurality of code sequences that phase shift the original code sequence by a different amount by calculating the sum modulo , and means for selecting each code sequence obtained from the generating means. and making each output selected by the selection means correspond to a plurality of correlators provided for demodulating the information signal and delay lock loop, and detecting the correlation of the spread spectrum signals applied to these correlators. A synchronization method for a spread spectrum receiver is obtained.
次に、本発明によるスペクトラム拡散受信機の
同期方式について実施例を挙げ、図面を参照して
詳細に説明する。 Next, a synchronization method for a spread spectrum receiver according to the present invention will be described in detail by giving examples and referring to the drawings.
第2図は本発明による実施例の構成をブロツク
図により示したものである。この図において、電
圧制御発振器10からのクロツク信号は局部擬似
雑音符号発生回路17のクロツク信号制御回路1
8を通してn段シフトレジスタ20に供給され
る。一般に、スペクトラム拡散の擬似雑音符号に
は自己相関関数が最大となる最長符号系列が選ば
れるが、これは、n段シフトレジスタ20の最終
段出力と特定の段間出力とを排他的論理和21を
介して初段に帰還することにより得られる。ま
た、最長符号系列の擬似雑音符号には、位相シフ
トした符号と元の符号との排他的論理和が元の符
号を別の大きさだけ位相シフトした第3の符号に
なるという性質があるため、任意に希望する大き
さだけ位相シフトした符号を発生するように設定
することができる。したがつて、n段シフトレジ
スタ20から特定の出力を選び出し、排他的論理
和22および23によりそれぞれ出力を得ること
によつて擬似雑音符号の1周期に対して互いに約
1/3だけ位相シフトした3組の符号出力が得られ
る。そして、これ等の出力は1ビツトシフトレジ
スタを含んで構成されるデータセレクタ24に加
えられる。 FIG. 2 is a block diagram showing the structure of an embodiment according to the present invention. In this figure, the clock signal from the voltage controlled oscillator 10 is clocked by the clock signal control circuit 1 of the local pseudo-noise code generation circuit 17.
8 and is supplied to the n-stage shift register 20. Generally, the longest code sequence with the maximum autocorrelation function is selected as a spread spectrum pseudo-noise code, but this is done by exclusive ORing the final stage output of the n-stage shift register 20 and a specific interstage output. It is obtained by returning to the first stage via. Additionally, the pseudo-noise code with the longest code sequence has the property that the exclusive OR of the phase-shifted code and the original code becomes a third code that is the original code phase-shifted by a different amount. , it can be set to generate a code whose phase is shifted by any desired amount. Therefore, by selecting specific outputs from the n-stage shift register 20 and obtaining outputs by exclusive ORs 22 and 23, the phases are shifted by about 1/3 from each other for one period of the pseudo-noise code. Three sets of code outputs are obtained. These outputs are then applied to a data selector 24 that includes a 1-bit shift register.
このデータセレクタ24は1/2ビツトシフトレ
ジスタ11と組み合わされて、3組の各符号を独
立に出力したり、1組の符号だけを選択して1/2
ビツト位相シフトした3組の符号d′,e′および
f′を出力する。これらの符号は3個の相関器1〜
3で受信信号RXSSを各々逆拡散し、包絡線検波
器4〜6で相関検出する。相関検出出力a′,b′お
よびc′はデータ選択機能を備えた同期検出回路1
9で同期検出の判定に用いられる。初期捕捉およ
び再捕捉の場合、3組の符号d′,e′およびf′は1/3
周期位相シフトした形である微少量周期的に位相
シフトして全符号をサーチする。そして、3組の
いずれかの符号により相関が検出されると、同期
検出回路19は遅延ロツクループのために、相関
検出された信号をデータセレクタ24に与えて、
該信号に対応する符号をデータセレクタ24で選
択するように制御する。この制御の結果、同期が
検出されると、クロツク制御回路18を制御して
サーチ操作を停止させ、同期状態が保持される。 This data selector 24 is combined with the 1/2 bit shift register 11 to output each of the three sets of codes independently, or to select only one set of codes and output 1/2
Three bit phase-shifted codes d', e' and
Output f′. These codes are processed by three correlators 1~
3 despread the received signals RXSS, and envelope detectors 4 to 6 perform correlation detection. Correlation detection outputs a', b' and c' are synchronization detection circuit 1 with data selection function.
9 is used for determining synchronization detection. For initial acquisition and reacquisition, the three sets of codes d', e' and f' are 1/3
All codes are searched by periodically shifting the phase by a small amount. When correlation is detected by any one of the three codes, the synchronization detection circuit 19 supplies the detected correlation signal to the data selector 24 for the delay lock loop.
The data selector 24 is controlled to select the code corresponding to the signal. As a result of this control, when synchronization is detected, the clock control circuit 18 is controlled to stop the search operation and the synchronization state is maintained.
この実施例によれば、初期捕捉および再捕捉の
場合に、擬似雑音符号の位相が互に1/3周期ずつ
シフトされた3つの区分のうち、いずれの時間に
受けられるも、それぞれ独立に相関検出のために
役立てられるから、検出の機会が従来の3倍とな
り、擬似雑音符号のサーチ時間が1/3に短縮され
る。但し、擬似雑音符号の相関性は2ビツト間と
狭いために、同期検出の判定タイミングは1/2ビ
ツトサーチで行われ、従来の1ビツトサーチによ
る検出誤りの確率が高くなることを防いでいる。
それによるも、総合的には、同期検出の確率は従
来より高く、かつ同期の確立に要する時間は短縮
される。なお、第3図AおよびBは、それぞれ第
1図の従来方式と第2図の実施例とによる相関検
出の比較をタイムチヤートにより示したものであ
る。この図から判るように、従来方式においては
判定のタイミングが1ビツトサーチになつてお
り、殆ど1周期中の1個所でしか相関が検出され
ないが、実施例の方式は判定のタイミングが1/2
ビツトシフトサーチであり、1周期中3個所で検
出の機会が得られる。また、同じ時間Tに対して
比較して見ると、実施例の方式では、相関検出の
機会が従来の方式の2倍になつていることが判る
であろう。 According to this embodiment, in the case of initial acquisition and reacquisition, the phase of the pseudo-noise code received at any time among the three divisions shifted by 1/3 period from each other is independently correlated with each other. Since it is useful for detection, the detection chances are tripled compared to the conventional method, and the search time for pseudo noise codes is reduced to one-third. However, since the correlation of pseudo-noise codes is narrow between two bits, the judgment timing for synchronization detection is performed by a 1/2-bit search to prevent a high probability of detection errors caused by the conventional 1-bit search.
Even so, overall, the probability of synchronization detection is higher than in the past, and the time required to establish synchronization is shortened. 3A and 3B are time charts showing a comparison of correlation detection by the conventional method shown in FIG. 1 and the embodiment shown in FIG. 2, respectively. As can be seen from this figure, in the conventional method, the timing of determination is a 1-bit search, and correlation is detected only at one point in one cycle, but in the method of the embodiment, the timing of determination is 1/2.
This is a bit shift search, and detection opportunities are obtained at three locations in one cycle. Furthermore, when compared for the same time T, it will be seen that in the method of the embodiment, the chances of correlation detection are twice as large as in the conventional method.
以上の説明により明らかなように、本発明によ
れば、元の符号系列を別の大きさだけ位相シフト
する複数個の符号系列発生手段と、該手段から得
られるそれぞれの符号系列を選択する手段とを設
けることによつて、スペクトラム拡散信号の受信
に際し、相関の検出率を高め、かつ同期の確立ま
でに要する時間を大きく短縮させることが可能と
なり、スペクトラム拡散受信機の性能および信頼
性を向上すべく得られる効果は大きい。 As is clear from the above description, according to the present invention, there are provided a plurality of code sequence generation means for phase-shifting the original code sequence by a different amount, and means for selecting each code sequence obtained from the means. By providing this, when receiving spread spectrum signals, it is possible to increase the correlation detection rate and greatly reduce the time required to establish synchronization, improving the performance and reliability of the spread spectrum receiver. The effects that can be achieved are significant.
第1図はスペクトラム拡散受信機における従来
の同期方式の構成例を示すブロツク図、第2図は
本発明による実施例の構成を示すブロツク図、第
3図AおよびBは、それぞれ第1図の従来例と第
2図の実施例とにおける相関検出の動作を比較的
に説明するためのタイムチヤートである。
図において、1〜3は相関器、4〜6は包絡線
検波器、7は帯域通過フイルタ、8は相関弁別回
路、9はループフイルタ、10は電圧制御発振
器、11は1/2ビツトシフトレジスタ、12,1
7は局部擬似雑音符号発生回路、13,18はク
ロツク信号制御回路、14,19は同期検出回
路、15,20はn段シフトレジスタ、16,2
1,22,23は排他的論理和回路、24はデー
タセレクタである。
FIG. 1 is a block diagram showing a configuration example of a conventional synchronization method in a spread spectrum receiver, FIG. 2 is a block diagram showing a configuration of an embodiment according to the present invention, and FIGS. 2 is a time chart for comparatively explaining the correlation detection operation in the conventional example and the embodiment of FIG. 2. In the figure, 1 to 3 are correlators, 4 to 6 are envelope detectors, 7 is a band pass filter, 8 is a correlation discrimination circuit, 9 is a loop filter, 10 is a voltage controlled oscillator, and 11 is a 1/2 bit shift register. ,12,1
7 is a local pseudo-noise code generation circuit; 13 and 18 are clock signal control circuits; 14 and 19 are synchronization detection circuits; 15 and 20 are n-stage shift registers;
1, 22, and 23 are exclusive OR circuits, and 24 is a data selector.
Claims (1)
より変調されたスペクトラム拡散信号の受信機に
おいて、前記最長線形系列の擬似雑音符号と該擬
似雑音符号を位相シフトした符号との2を法とす
る和をとることによつて、元の符号系列を別の大
きさだけ位相シフトする複数個の符号系列を発生
させる手段と、該発生手段から得られるそれぞれ
の符号系列を選択する手段とを含み、該選択手段
により選択されたそれぞれの出力を情報信号の復
調および遅延ロツクループ用に備えられる複数個
の相関器に対応させ、これ等の相関器に加えられ
るスペクトラム拡散信号を相関検出することを特
徴とするスペクトラム拡散受信機の同期方式。1. In a receiver of a spread spectrum signal modulated by a pseudo-noise code of the longest linear sequence that has been converted into information, a sum modulo 2 of the pseudo-noise code of the longest linear sequence and a code obtained by phase-shifting the pseudo-noise code. means for generating a plurality of code sequences that phase shift the original code sequence by different amounts by taking Each output selected by the selection means is made to correspond to a plurality of correlators provided for demodulating information signals and delay lock loops, and the spread spectrum signals applied to these correlators are subjected to correlation detection. Synchronization method for spread spectrum receivers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57072758A JPS58190143A (en) | 1982-04-30 | 1982-04-30 | Synchronizing system of spread spectrum receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57072758A JPS58190143A (en) | 1982-04-30 | 1982-04-30 | Synchronizing system of spread spectrum receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58190143A JPS58190143A (en) | 1983-11-07 |
| JPS6412140B2 true JPS6412140B2 (en) | 1989-02-28 |
Family
ID=13498574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57072758A Granted JPS58190143A (en) | 1982-04-30 | 1982-04-30 | Synchronizing system of spread spectrum receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58190143A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07120968B2 (en) * | 1989-02-07 | 1995-12-20 | クラリオン株式会社 | Spread spectrum communication device |
-
1982
- 1982-04-30 JP JP57072758A patent/JPS58190143A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58190143A (en) | 1983-11-07 |
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