JPS641943B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in insulated gate field effect transistors.

Conventionally, as an insulated gate field effect transistor,
As shown in FIG. 1, an N ⁺ type semiconductor region 3 and a P type semiconductor region 4 are formed in an N ^- type semiconductor substrate 1 from the main surface 2 side, and in the semiconductor region 4 from the main surface 2 side. An N ⁺ type semiconductor region 5 is formed, and a surface 8 on the main surface 2 side in a region 7 between the semiconductor region 5 of the semiconductor region 4 and the region 6 between the semiconductor regions 4 and 3 of the semiconductor substrate 1 A conductive layer 10 is disposed thereon through an insulating layer 9, and conductive layers 11 and 12 are ohmicly applied to the semiconductor regions 3 and 5 from the main surface 2 side, and furthermore, conductive layers 11 and 12 are ohmicly applied to the semiconductor regions 4 and 5 when viewed from the region 5. In the region 13 opposite to the region 7 side, a conductive layer 14 is ohmicly applied from the main surface 2 side, so that the semiconductor substrate 1 and the semiconductor region 3 are used as a drain region, and the semiconductor region 5 is used as a source region. , the region 7 between the semiconductor region 5 of the semiconductor region 4 and the region 6 between the semiconductor regions 4 and 3 of the semiconductor substrate 1 is a channel forming region, the insulating layer 9 is a gate insulating layer, and the conductive layer 10
A configuration has been proposed in which the conductive layers 11 and 12 are used as a gate electrode, the conductive layers 11 and 12 are used as a drain electrode and a source electrode, respectively, and the conductive layer 14 is used as a back gate electrode.

According to the structure of such an insulated gate field effect transistor, there is a conductive layer 11 side between the conductive layer 12 as the source electrode, the conductive layer 14 as the back gate electrode, and the conductive layer 11 as the drain electrode. The required operating power source 20 with positive is the load 21
With the control voltage source 23 connected between the conductive layers 12 and 14 and the conductive layer 10 serving as a gate electrode, the value of the control voltage obtained from the control voltage source 23 becomes a predetermined value ( If the value exceeds the threshold (threshold value), a channel is formed by the N-type inversion layer on the surface 8 side of the region 7 of the semiconductor region 4 as a channel formation region, and therefore an on state is obtained, so that the load 21 is connected to the operating power supply. From 20, conductive layer 1
1. Through the semiconductor region 3 as a drain region, the region 6 between regions 3 and 4 of the semiconductor substrate 1, the channel formed in the region 7 as a channel formation region, the semiconductor region 5 as a source region, and the conductive layer 12. In this case, a current of a value corresponding to the value of the control voltage is supplied, and from this state, the control voltage source 2
If the value of the control voltage obtained from 3 takes a value lower than the threshold value, the above-mentioned channel is not formed, and therefore an off state is obtained, so that the above-mentioned current is not supplied to the load 21. This function can be obtained as follows.

Further, according to the structure of the conventional insulated gate field effect transistor shown in FIG. 1 ^, the function as the insulated gate field effect transistor described above can be obtained. Conductive layer 11 as a drain electrode
The conductive layer 11 is composed of a semiconductor substrate 1 having a higher specific resistance than an N ⁺ type semiconductor region 3 having a low specific resistance.
and 12, if the semiconductor substrate 1 and semiconductor region 3 constituting the drain region are
The higher the resistivity is, the higher the resistivity of the semiconductor substrate 1 is, the higher the breakdown voltage is, the higher the resistivity of the semiconductor substrate 1 is, the higher the resistivity of the semiconductor regions 4 and 3 is. It has the characteristic that the larger the distance between the semiconductor regions 4 and 3, that is, the length of the region 7 between the semiconductor regions 4 and 3 of the semiconductor substrate 1, the higher the height can be made.

However, in the case of the structure of the insulated gate field effect transistor described above in FIG. 1, although the breakdown voltage between the conductive layers 11 and 12 is high as described above,
The resistance between the conductive layers 12 and 11, that is, the so-called on-resistance, is high when the on-state is obtained as described above, and therefore, the on-state is obtained as described above and current is supplied to the load. It has the disadvantage that there is a certain limit to the ability to obtain a large current value under certain conditions.

Therefore, the present invention proposes a novel insulated gate field effect transistor that can obtain the same function as an insulated gate field effect transistor as the conventional insulated gate field effect transistor shown in FIG. This will become clear from the detailed explanation below.

FIG. 2 shows an example of an insulated gate field effect transistor according to the present invention, in which a P ^- type semiconductor substrate 30
An N-type semiconductor layer 32 and a P-type semiconductor layer 33 are placed on the main surface 31 of the semiconductor substrate 30, with the main surfaces 34 and 35 on the opposite side to the semiconductor substrate 30 being in the same plane. The semiconductor layer 3 is formed in a juxtaposed and connected manner.
2, an N ⁺ type semiconductor region 3 is formed from the main surface 34 side.
6 is formed, and the main surface 3 is further formed in the semiconductor layer 33.
Similarly, an N ⁺ type semiconductor region 37 is formed from the 5 side, and the semiconductor layer 32 is further formed in the semiconductor substrate 30.
A P ⁺ type semiconductor region 39 is formed from the main surface 38 side opposite to the 33 side, and a surface 42 on the main surface 35 side in a region 40 between the semiconductor region 37 and the semiconductor layer 32 of the semiconductor layer 33. A conductive layer 43 is disposed thereon through an insulating layer 42, and a conductive layer 4 is disposed on the semiconductor regions 36 and 37 from the principal surfaces 34 and 35, respectively.
4 and 45 are attached to the ohmic, and a conductive layer 46 is further applied to the semiconductor layer 33 from the main surface 35 side in a region 49 on the opposite side to the region 40 side as seen from the region 37.
is attached, and furthermore, a semiconductor layer 32 is attached to the semiconductor region 39.
A conductive layer 47 is attached to the ohmic from the side opposite to the semiconductor region 36 and the N ⁺ type first semiconductor region Q1 and the semiconductor layer 33.
an N-type second semiconductor region Q2 connected to the first semiconductor region Q1 by the semiconductor region 33; Semiconductor area Q3
and an N ⁺ type fourth semiconductor region Q which is not connected to the first and second semiconductor regions Q1 and Q2 by the semiconductor region 37 but is connected to the third semiconductor region Q3.
4, and a surface 41 of the region B1 between the second and fourth semiconductor regions Q2 and Q4 of the third semiconductor region Q3 by the region 40 of the semiconductor layer 33, and an insulating layer I formed by the insulating layer 42 on the surface S1. A conductive layer MG formed by a conductive layer 43 arranged, a conductive layer MD formed by a conductive layer 44 ohmicly attached to the first semiconductor region Q1, and a conductive layer MD formed ohmicly attached to the fourth semiconductor region Q4. Conductive layer formed by the last layer 45
MS, and a conductive layer MB formed by a conductive layer 46 ohmically attached to the third semiconductor region Q3, and at least connected to the first and fourth semiconductor regions such as by the semiconductor substrate 30. First and third semiconductor regions Q1 and Q2 of second semiconductor region Q2
A fifth semiconductor region Q having a P type and having a resistivity higher than that of the P ^- type, that is, the second semiconductor region Q2, which is connected to the intervening region B2 and the third semiconductor region Q3.
5 (in the figure, region B2 of the second semiconductor region Q2
In addition, the second semiconductor region Q2 is connected to a region B3 below the first semiconductor region Q1 and a region B4 of the second semiconductor region Q2 on the opposite side to the region B2 side when viewed from the first semiconductor region Q1. ) and a conductive layer MQ formed by a conductive layer 47 attached to the fifth semiconductor region Q5 via a P ⁺ type semiconductor region 39, and A U-shaped groove H that can extend from the main surface 34 side to the semiconductor substrate 30 side without reaching there is formed in the region between the layer 33 and the semiconductor region 36, so that the above-mentioned first, second, third, Fourth and fifth semiconductor regions Q
1, Q2, Q3, Q4, and Q5, the above-mentioned insulating layer I, the above-mentioned conductive layers MG, MS, MD, and MQ, as well as a second semiconductor region formed by the semiconductor region 36 of the semiconductor layer 32 and the semiconductor layer 33. Region B2 between the first and third semiconductor regions Q1 and Q3 of Q2
In addition, the semiconductor substrate 30 is provided with a groove H that can extend from the non-contiguous side of the fifth semiconductor region Q5 to the fifth semiconductor region Q5 side without reaching the fifth semiconductor region Q5.

The above is an example of the structure of an insulated gate field effect transistor according to the present invention. According to such a structure,
The first and second semiconductor regions Q1 and Q2 are the semiconductor substrate 1 and semiconductor region 3 of the conventional insulated gate field effect transistor described above in FIG. 1, and the fourth semiconductor region Q4 is the semiconductor region of FIG. 5,
The region B1 between the second and fourth semiconductor regions Q2 and Q4 of the third semiconductor region Q3 is connected to the semiconductor region 5 of the semiconductor region 4 and the region 6 between the semiconductor regions 4 and 3 of the semiconductor substrate 1 in FIG. In the region 7 between, an insulating layer I
is the insulating layer 9 in FIG. 1, and conductive layers MG, MD,
MS and MB are respectively the conductive layers 10 and 11 of FIG.
12 and 14, the first and second semiconductor regions Q1 and Q2 are drain regions, the fourth semiconductor region Q4 is a source region, and the second and fourth semiconductor regions of the third semiconductor region Q3 are Area Q2
and Q4, the region B1 is a channel forming region,
The insulating layer I is an insulating layer for a gate, a conductive layer MG,
It is clear that an insulated gate field effect transistor is constructed in which MD, MS, and MB serve as a gate electrode, a drain electrode, a source electrode, and a back gate electrode, respectively.

Therefore, according to the structure of the insulated gate field effect transistor according to the present invention described above in FIG. 2, the conductive layer MS as the source electrode, the conductive layer MB as the back gate electrode, the conductive layer MQ as the drain electrode, A conductive layer between the conductive layer MD
The required operating power source 50 with the MD side as positive is connected to the load 51
Connected through and also conductive layers MS, MB and MQ
When the control voltage source 53 is connected between the control voltage source 53 and the conductive layer MG as a gate electrode, if the value of the control voltage obtained from the control voltage source 53 becomes a predetermined value (threshold value) or more, a channel is formed. A channel by an N-type inversion layer is formed on the surface side of the region B1 of the third semiconductor region Q3 as a storage region, and therefore an on state is obtained.
Conductive layer MD, region B of the first semiconductor region Q1 and second semiconductor region Q2 as a drain region
2. A current having a value corresponding to the value of the control voltage in this case is supplied through the channel formed in the region B1 as the channel forming region, the fourth semiconductor region Q4 as the source region, and the conductive layer MS; In addition, if the value of the control voltage obtained from the control voltage source 53 takes a value lower than the threshold value in such a state, the above-mentioned channel is not formed, and therefore an OFF state is obtained, so that the above-mentioned current is supplied to the load 51. In this case, the function as an insulated gate field effect transistor similar to that of the insulated gate field effect transistor described above in FIG. 1 can be obtained.

Further, according to the structure of the insulated gate field effect transistor according to the present invention as described above in FIG. 2, the function as the insulated gate field effect transistor described above can be obtained.
and a fifth semiconductor region Q5 connected to the third and first semiconductor regions Q3 of the second semiconductor region Q2 and the region B2 between Q1, and the third and first semiconductor regions of the second semiconductor region Q2. By having a groove H in the region B2 between the regions Q3 and Q1 that can extend from the non-contiguous side of the fifth semiconductor region Q5 to the fifth semiconductor region Q5 side without reaching it,
When a large voltage is applied between the conductive layers MS and MD, the second and fifth semiconductor regions Q2 and Q5
A depletion layer reaching the groove H is obtained by the PN junction between the two, and the depletion layer allows the second semiconductor region Q2 to form a third semiconductor region Q3 with the position of the groove H sandwiched therebetween.
It is separated into a side portion and a side portion of the first semiconductor region Q1.

Therefore, the breakdown voltage between the conductive layers MS and MD is the first
groove H in the semiconductor region Q1 and the second semiconductor region Q2.
When viewed from above, the portion on the first semiconductor region Q1 side, the fifth semiconductor region Q5, the third semiconductor region Q3, and the fourth semiconductor region Q4 are mainly the second semiconductor region Q2.
The specific resistance of the fifth semiconductor region Q5 is higher than that of the second semiconductor region Q2. Therefore, the breakdown voltage between the conductive layers MS and MD is high. Further, the breakdown voltage can be increased as the specific resistance of the fifth semiconductor region Q5 is increased.

Further, according to the structure of the insulated gate field effect transistor described above in FIG. 2, the conductive layer is
There is a method that can increase the withstand voltage between MS and MD, but in the above-mentioned on state, the fifth semiconductor region Q5
On the other hand, the on-resistance in the state where the on-state is obtained depends on the specific resistance of the region B2 of the second semiconductor region Q2; Since its on-resistance is lower than that of Q5, its on-resistance is lower than that of the conventional insulated gate field effect transistor described above in FIG. The current value when the current is being supplied to the transistor can be obtained to be larger than that of the conventional insulated gate field effect transistor shown in FIG.

Accordingly, the insulated gate field effect transistor according to the present invention described above with reference to FIG. 2 has the great feature of being able to obtain a high withstand voltage and yet a low on-resistance.

Next, referring to FIG. 3, another example of the insulated gate field effect transistor according to the present invention will be described.
Although the same reference numerals are given to corresponding parts in the figure and detailed explanation thereof is omitted, in the configuration described above in FIG. 2, the second semiconductor region Q2 is located within the third semiconductor region Q3. The groove H is formed to be extended on the semiconductor region Q5 side of No. A third semiconductor region Q3 is formed as a V-shaped groove that terminates in
The structure is similar to that of the case shown in FIG. 2, except that the surface S1 is the surface facing the trench H of the third semiconductor region Q3.

The above is the configuration of another example of the insulated gate field effect transistor according to the present invention. According to this configuration, it has the same configuration as the case of FIG. 2 except for the matters mentioned above, so the details will be explained below. Although the description thereof will be omitted, it has the same excellent characteristics as the insulated gate field effect transistor according to the present invention described above with reference to FIG.

The above description has only shown a few embodiments of the present invention, and for example, the above-mentioned "P ^- type" may be referred to as "N ^- type",
"N type" is "P type", "N ⁺ type" is "P ⁺ type", "P ⁺ type"
It is also possible to read it as "N ⁺ type",
Also, if the conductive layers MB and MS are used connected to each other as shown, the conductive layers MB
and MS could be a single conductive layer extending continuously between these locations, and various other modifications could be made without departing from the spirit of the invention.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view showing a conventional insulated gate field effect transistor, FIG. 2 is a schematic cross-sectional view showing an example of an insulated gate field effect transistor according to the present invention, and FIG. 3 is a schematic cross-sectional view showing an insulated gate field effect transistor according to the present invention. FIG. 3 is a schematic cross-sectional view showing another example of a field effect transistor. In the figure, Q1, Q2, Q3, Q4 and Q5 are first, second, third, fourth and fifth semiconductor regions, I
is an insulating layer, MG, MD, MS and MB are conductive layers,
H indicates a groove, respectively.

Claims (1)

[Claims] 1 a first semiconductor region having a first conductivity type;
a second semiconductor region that is connected to the first semiconductor region and has a higher specific resistance than the first semiconductor region and has a first conductivity type; and a second semiconductor region that is not connected to the first semiconductor region. a third semiconductor region having a second conductivity type opposite to the first conductivity type, which is connected to the second semiconductor region; and a third semiconductor region which is not connected to the first and second semiconductor regions; a fourth semiconductor region having a first conductivity type connected to the third semiconductor region;
a conductive layer disposed on a surface of a region between the second and fourth semiconductor regions of the third semiconductor region with an insulating layer interposed therebetween; The fourth semiconductor region is a source region, the region between the second and fourth semiconductor regions of the third semiconductor region is a channel forming region, the insulating layer is a gate insulating layer, and the conductive layer In an insulated gate field effect transistor having a gate electrode, the first semiconductor region of the second semiconductor region is not connected to the first and fourth semiconductor regions.
and a fifth semiconductor region having a higher specific resistance than the region between the third semiconductor regions and the second semiconductor region connected to the third semiconductor region and having a second conductivity type; the first semiconductor region of the second semiconductor region;
and an insulated gate electric field characterized by having a groove in a region between the third semiconductor regions that can extend from the non-contiguous side of the fifth semiconductor region to the fifth semiconductor region without reaching it. effect transistor.