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JPS642033B2 - - Google Patents
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JPS642033B2 - - Google Patents

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Publication number
JPS642033B2
JPS642033B2 JP57173646A JP17364682A JPS642033B2 JP S642033 B2 JPS642033 B2 JP S642033B2 JP 57173646 A JP57173646 A JP 57173646A JP 17364682 A JP17364682 A JP 17364682A JP S642033 B2 JPS642033 B2 JP S642033B2
Authority
JP
Japan
Prior art keywords
phase
voltage
input
output
rectifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57173646A
Other languages
Japanese (ja)
Other versions
JPS5963976A (en
Inventor
Ryoji Saito
Yoshio Suzuki
Kazuhiro Senoo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Origin Electric Co Ltd
Original Assignee
Origin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Origin Electric Co Ltd filed Critical Origin Electric Co Ltd
Priority to JP57173646A priority Critical patent/JPS5963976A/en
Publication of JPS5963976A publication Critical patent/JPS5963976A/en
Publication of JPS642033B2 publication Critical patent/JPS642033B2/ja
Priority to JP1030640A priority patent/JPH01252174A/en
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of DC power input into DC power output
    • H02M3/22Conversion of DC power input into DC power output with intermediate conversion into AC
    • H02M3/24Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
    • H02M3/28Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)
  • Dc-Dc Converters (AREA)
  • Inverter Devices (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

〔産業上の利用分野〕 本発明は多相交流入力の周期よりも充分に短い
周期毎に多相交流の瞬時電圧値の2乗に比例する
値と制御量との所定の関係に依存するエネルギを
出力に得るAC―DC変換に関する。 〔従来の技術〕 多相交流入力、例えば商用の3相交流入力から
所望の値の直流電圧を得たい場合の従来の代表的
なスイツチングモードの整流装置としては第1図
に示す様なものがある。この従来の整流装置は各
3相交流入力端子に直列に接続されたインダクタ
Lu,Lv,Lw6個の整流器D1〜D6からなり、3相
交流入力を全波整流する3相全波整流回路Rec
1、この3相全波整流回路の出力を平滑する平滑
回路を構成するインダクタL1とコンデンサC1
トランスTの1次巻線N1介して互いに直列接続
されたスイツチングトランジスタQ1,Q1′、これ
らのスイツチングトランジスタのオフ期間に導通
してトランスにおけるエネルギをコンデンサC1
に流すダイオードD7とD8、トランスTの2次巻
線N2の電圧を整流する整流器D9、フライホイー
ルダイオードD10、出力フイルタ回路を構成する
インダクタL2とコンデンサC2、出力端子O,
O′及び出力端子O,O′間の直流出力電圧を一定
にする様にスイツチングトランジスタQ1,Q1′を
パルス幅制御する制御回路Cpoからなつている。 〔発明が解決しようとする課題〕 斯かる従来の整流装置では3相交流入力を3相
全波整流回路Rec1で整流した後にインダクタL1
とコンデンサC1とからなる平滑回路でもつて平
滑された直流にしているので、最も電圧の高い相
のダイオードを介して各相をパルス状電流が通流
するために高調波成分を多く含んでいる。整流回
路Rec1に設けたインダクタLu,Lv,Lwをもつ
てしても少くとも低次の高調波成分は除去出来な
い。この高調波成分は通信回路に誘導障害を与え
てこれを誤動作させる大きな原因となるばかりで
なく、同じ給電源に接続された周辺機器にも悪影
響を与えたり、多相交流の給電源の電力損失の増
大及び発電機との組合せでは発電機の電力損失の
増加などによる容量の増大を招来する。また平滑
用インダクタL1とコンデンサC1が必要であると
いう欠点がある。 〔課題を解決するための手段〕 本発明はこの様な従来の欠点を除去するもので
あつて、対称の多相交流及び2相3線式の入力側
とその一定負荷を有するDC出力側においてはエ
ネルギの流れの瞬時値が一定になるという知見に
基づき、多相交流入力電流が正弦波状の波形で流
れる様に各スイツチング素子の導通期間を特定の
方法で制御することにより、多相交流入力電流の
高調波成分を低減し、且つリツプル分の小さい一
定の直流出力を得ることが出来ることを特徴とし
ている。 対称負荷を有する対称n相交流装置(n≧3)
においては、入力側の瞬時電圧Vjは、 Vj=√2Vnsin{ωt−2π(j-1)/n} ……(1) で表わされる。但しj=1、2、3、……n、 Vnは入力電圧Vjの実効値である。 ここで各相間に接続される負荷が夫々抵抗値R
を有する抵抗負荷の場合には、入力部に供給され
る瞬時電力Piは、 Pioj=1 Vj 2/R =2Vn 2/Roj=1 sin2{ωt−2π(j-1)/n} ……(2) になり、oj=1 sin2(ωt−2π(j−1)/n}はn/
2になるので、結局入力部の瞬時電力Piは、 Pi=n・Vn 2/R ……(3) になる。 この(3)式は対称n相交流装置において流れるエ
ネルギが一定であることを示す。従つてこのこと
から交流入力に対する負荷が線形になるようにし
ながら直流出力側に一定のエネルギを得る様に制
御すれば、入力側には正弦波状の多相交流入力電
流が流れるので十分に高調波成分を低減できる。 また直流出力側に一定のエネルギを取り出すに
は、上記(2)式から多相交流入力の各時点における
各相の瞬時電圧値の2乗に比例するエネルギを取
り出せば良いことが分る。 この瞬時電圧値をより精密に得るためには変換
周波数を多相交流入力の周波数と比較して、可能
な限り高い値に選ぶことが望ましい。 本発明は以上述べた様な知見に基づく具体的な
AC―DC変換を提供するものである。 〔実施例〕 以下図面により本発明に係るAC―DC変換の各
実施例について詳述する。 先ず第2図乃至第5図により本発明の一実施例
を説明する。 第2図に示す整流装置の主回路は3相交流入力
の各相U、V、Wの各ラインに直列接続されたイ
ンダクタLu,Lv,Lw、相間に接続されたコンデ
ンサCu,Lv,Cw単相全波整流器Dとコンデンサ
C1′とよりなる同一構成の整流回路Rec1,Rec
2,Rec3、同時にスイツチング動作を行う一対
のスイツチングトランジスタQ1とQ1′、1次巻線
N1と2次巻線N2とを有すする変圧器T及スイツ
チングトランジスタQ1とQ1′のオフ時に導通して
変圧器Tに蓄えられた励磁エネルギなどをコンデ
ンサC1′に帰還するためのダイオードD7とD8から
なる同一構成の変換部G1,G2,G3、各変換
部の出力を並列に組合せる様に接続された整流器
D9,D9′,D9″、フライホイーリング用ダイオー
ドD10、平滑回路を構成するインダクタL2,L2′と
コンデンサC2,C2′及びコンデンサC3からなり、
その出力端には負荷Fが接続されている。 この実施例における整流装置は各相間電圧を整
流する整流回路と変換部との間に入力周波数用の
平滑回路を設ける必要のないことを構成上の1つ
の特徴としており、後述する全く新規な制御方法
によつて各スイツチングトランジスタQ1とQ1′を
スイツチング動作させて整流された正弦波状の電
圧を開閉することにより入力電流の高調波成分を
大幅に低減すると共に、リツプル分の極めて低い
安定化した直流出力を得るものである。 第3図はこの制御方法を行う制御回路のブロツ
ク構成の一例を示し、第4図は各部の動作のタイ
ミングを示す信号を表示しており、第5図A,B
は夫々変換部の入、出力波形を説明するための図
である。第3図において、基準信号発振器1は多
相交流入力の周波数よりも充分に高い周波数、例
えば20KHzの基準パルス信号を生ずる。この基準
パルス信号は第4図において時刻t1で発生される
信号aで示される。この信号aの立上りでリセツ
トパルス形成回路2は所定パルス幅、例えば1μ
秒のパルス幅のリセツトパルスを生ずる。このリ
セツトパルスはOR回路5を介してリセツト用
FET6のゲートに印加され、このFET6をその
パルス幅だけターンオンさせてキヤパシタ7の電
荷をほぼ零まで放電させる。遅延回路3はリセツ
トパルスの立下がりからスイツチングトランジス
タQ1,Q1′のキヤリア蓄積時間にほぼ等しい時間
だけ遅れた時刻、つまり信号aから時間τだけ遅
延した時刻t2にオン信号bを駆動ラツチ回路4に
与える。これに伴い駆動ラツチ回路4は第1の変
換部G1のスイツチングトランジスタQ1,Q1′の
ベースに駆動信号S1を与えて、信号dで示す様に
ターンオンさせる。 FET6に並列に接続されたキヤパシタ7は誤
差増幅器8からの誤差信号によつて定電流値が制
御される可制御定電流源9からの定電流により充
電される。誤差増幅器8が出力する誤差信号は整
流装置における直流出力電圧に比例する検出信号
Sdと基準値との間の差に依存する。従つてキヤパ
シタ7の充電々圧は基準信号aに基づくリセツト
パルスにより一且ほぼ零値まで降下した後、制御
量、この実施例では出力電圧検出信号Sdと基準値
との差の大きさに比例する上昇率をもつて上昇す
る。キヤパシタ7の充電々圧は各比較較器10,
10′,10″の正端子に印加される。これら比較
器の負端子には夫々全波整流器11,11′,1
1″の直流側端子と抵抗12,12′,12″が
夫々接続され、全波整流器11の交流側端子1
3,14間には3相交流入力のU―V相間電圧に
比例する電圧が、全波整流器11′の交流側端子
13′,14′間にはV―W相間電圧に比例する電
圧が、また全波整流器11″の交流側端子13″,
14″間にはW―U相間電圧に比例する電圧が
夫々印加されているので、比較器10の負端子に
はU―W相間の交流電圧を全波整流した正弦波形
状の電圧が現出し、同様に比較器10′,10″の
夫々の負端子にはV―W相間の交流電圧、W―U
相間の交流電圧を夫々整流した正弦波形状の電圧
が印加される。夫々の比較器10,10′,1
0″は正、負端子に印加される前述の様な電圧を
比較し、正端子の電圧が負端子の電圧に等しくな
つたときオフ信号を出力する。比較器10のオフ
信号cは時刻t3で駆動ラツチ回路4に入力され、
これに伴い駆動ラツチ回路4は変換部G1におけ
るスイツチングトランジスタQ1,Q1′に対するベ
ース駆動信号S1の供給を停止する。従つてトラン
ジスタQ1,Q1′は第4図において信号dで示す様
に蓄積時間の経過した後の時刻t4でターンオフす
る。 次に比較器10からの出力信号cは回路2と同
一構成のリセツトパルス形成回路2′に入力され
る。これに伴い回路2′は回路2が生ずるリセツ
トパルスと同様なリセツトパルスをOR回路5を
介してFET6のゲートに与え、これをターンオ
ンしてキヤパシタ7の電荷を放電させる。また回
路3と同一構成の遅延回路3′はリセツトパルス
を受けて信号cよりキヤリア蓄積時間にほぼ等し
い時間τだけ遅延した時刻t5にオン信号eを駆動
ラツチ回路4′に与える。これに伴い回路4′は変
換部G2のスイツチングトランジスタに駆動信号
S2を与えてこれをターンオンさせる(信号g)。
再びキヤパシタ7は変換部G2のオン動作期間に
おける出力電圧検出信号Sdの大きさに依存する定
電流により充電される。この充電々圧は比較器1
0′によつて前述と同様にV―W相間電圧に比例
する電圧を全波整流した正弦波形状の電圧と比較
され、双方の電圧が等しくなつた時点t6で信号f
を駆動ラツチ回路4′に与えると共にリセツトパ
ルス形成回路2″に与える。駆動ラツチ回路4′は
信号fを受けると直ちにベース駆動信号S2の送出
を停止し、これに伴い変換部G2はそのスイツチ
ングトランジスタの蓄積時間経過後の時刻t7でタ
ーンオフする。 次にリセツトパルス形成回路2″は比較回路1
0′から信号fを受けてリセツトパルスをOR回
路5を介してFET6のゲートに与え、これをタ
ーンオンさせてキヤパシタ7の電荷を瞬時に放電
させる。第3の遅延回路3″は回路2″からのリセ
ツトパルスを受けて、信号fから時間τだけ遅延
された時刻t8にオン信号hを駆動ラツチ回路4″
に与える。これに伴い該回路4″は駆動信号S3
変換部G3のスイツチングトランジスタに印加し
てこれをターンオンさせる(信号j)。キヤパシ
タ7はFET6のオンにより一且放電され、再び
出力電圧検出信号Sdに比例する定電流で充電され
る。キヤパシタ7の充電々圧は比較器10″によ
り3相交流入力のW―U相間電圧に比例する電圧
を全波整流した正弦波形状電圧と比較され、比較
器10″はこれら双方の電圧が等しくなつた時点
t9でオフ信号iを駆動ラツチ回路4″に与える。
これに伴い回路4″は駆動信号S3の供給を停止し、
変換部G3はそのスイツチングトランジスタの蓄
積時間の経過ターンオフする(信号j)。整流器
9,9′,9″のいずれもが非導通の区間ではイン
ダクタL2に蓄えられたエネルギがダイオードD10
を介して通流する。この様に各部が動作して1周
期Tが終了する。尚、第3図において15は各全
波整流器11,11′,11″の順方向ドロツプに
よる悪影響を打消すための補償用ダイオードであ
る。以上の動作説明を要約すれば、各変換部にお
けるスイツチングトランジスタは時分割、つまり
多相交流入力電圧の1周期よりも充分に小さい各
周期内で順次スイツチング動作し、しかもオンし
ているスイツチングトランジスタのターンオフに
伴い次のスイツチングトランジスタがオンする様
になつており、更に各変換部におけるスイツチン
グトランジスタは出力電圧検出信号と各相間電圧
に比例する正弦波形状電圧との積に比例するパル
ス幅で制御され、且つ各スイツチング素子は各相
間電圧の整流された正弦波状電圧を開閉してい
る。従つて各変換部のスイツチングトランジスタ
は、多相交流の周期よりも充分に短い周期毎に多
相交流の各相より出力側に取り出されるエネルギ
が多相交流の瞬時電圧値の2乗に比例する値
(Ksin2θt:Kは定数)と制御量との積に比例する
様に、スイツチング制御されるのが分る。 更にこの制御方法を分り易くするために第5図
によつてU相を中心にした180゜区間における変換
部の3相交流入力波形を説明する。第5図Aにお
いてV1はU―V相間電圧波形、V2はV―W相間
電圧波形、V3はW―U相間電圧波形を示し、同
図BにおいてU1,U2,U3は3相交流入力波形の
30゜間隔に相当する時刻t0〜t5から始まる夫々の周
期における整流器D9,D9′,D9″の出力波形を拡
大して夫々示している。各変換部G1〜G3は、
例えば20KHzの変換周波数で動作し、各変換部G
1〜G3が3相交流入力の対応する相間電圧を
20KHzの変換周波数で開閉する。第5図において
鎖線で示す様に、U―V相間電圧V1が零値であ
る時刻t0から始まる1周期における各出力電圧波
形は、前記実施例で詳述した様に出力電圧検出信
号Sdに依存するキヤパシタ7の充電々圧と相当す
る各相間電圧の瞬時値との比較によつて決定され
るパルス幅で各変換部G1〜G3のスイツチング
トランジスタが制御され、且つこれらのスイツチ
ングトランジスタが相当する各相間電圧を全波整
流した正弦波状電圧を開閉することを考え併せれ
ば、時刻t0における入力V1に対応する出力U1
パルス幅及び振幅ともに非常に小さく、入力V2
に対応する出力U2及び入力V3に対応する出力U3
は双方共にほぼ等しく、かつ出力U1に比べてパ
ルス幅と振幅の双方とも充分に大きくなることが
容易に理解される。 次に図示の関係上、相交流入力のU相の30゜に
相当する時刻t1(勿論時刻t0〜t1の間でも20KHzの
変換周波数で各変換部は動作している)で始まる
周期について説明すると、出力U1は入力V1が正
弦波形で上昇するに伴いパルス幅及び振幅ともに
増大し、出力U2は入力V2が最大振幅になるに伴
いそのパルス幅及び振幅ともに最大になる。また
出力U3は時刻t1で入力V3がV1にほぼ等しくなる
に伴い、パルス幅及び振幅ともに出力U1にほぼ
等しくなる。以下時刻t2,t3……t5から始まる各
周期についても同様に説明される。 つまりこの実施例では多相交流入力の周波数を
50Hzとすると、その各周期を20KHzの変換周波数
で400等分し、この400等分した各変換周期におい
て変換部G1〜G3を前述の通りの制御方法で時
分割制御している。400等分された各変換周期に
おける出力電圧U1〜U3の総和は出力電圧検出
信号Vdと基準値との差である誤差信号に対応し
て制御されるので、この検出信号Vdが一定であ
れば、上記式(3)により各周期における出力電圧U
1〜U3の総和が互いにすべて等くなることが分
かる。この様子は第5図Bにおいて、出力電圧U
1,U2,U3を時間の経過にそつて一列に並べ
て変換周波数を充分高くして考えてみれば、その
包絡線は限りなく直流に近づくことで分かる。 従つて前述の(3)式より入力側の瞬時電力Piは一
定であるので、出力側に得られる瞬時電力が一定
となり、前述のパルス幅制御が入力周波数に対し
て十分に高い変換周波数であれば、当然に入力側
では高周波成分を除くだけで正弦波形状の電流が
流れる。この実施例でも多相交流入力の周波数よ
りも充分に高い20KHzの変換周波数による各周期
の出力U1〜U3の総和がほぼ一定なので、リツプ
ルの小さい直流出力電圧を得ることが出来、入力
側には高調波成分の極めて少ない正弦波形状の電
流が流れることが容易に理解できる。 またこのAC―DC変換によれば、前述からも分
る様に変換部G1のスイツチングトランジスタの
オフに伴い変換部G2のスイツチングトランジス
タがターンオンし、そのターンオフに伴い変換部
G3のスイツチングトランジスタがターンオンす
る様に制御し得るので、オン―オン型のコンバー
タを利用して出力側を並列接続でき、かつ低電圧
大電流において高調波化し易く、しかも実施例に
用いたコンバータの最大デユーテイである1/2ま
で利用率を高めることが出来る。この様な追従制
御を可能とするためには、各変換部におけるスイ
ツチングトランジスタのキヤリア蓄積時間の影響
を除くためにほぼ等しい時間だけ遅延してオン信
号が与えられる様にすると共に、パルス幅におけ
る入力電圧との比例精度を向上させるため、コン
デンサ7の充電はこの遅延時間が始まる前より行
われ始めることが望ましい。 次に斯かるAC―DC変換により得られた具体的
な特性例を述べる。但し高調波は2次から45次ま
での範囲である。 入力が3相交流(50Hz)の200V、出力が
DC48V、30Aの場合: 入力電圧の高調波分―U―V:1.67%、V―
W:1.41%、W―U:2.22% 入力電流の高調波分―U:5.02%、V:4.07
%、W:4.75% 力率―0.982、効率―88.3% となる。 前述の様な制御方法は第6図に示す構成の整流
装置にも適用でき、この整流装置において整流器
D9,D9′及びD9″の出力はダイオードD11,D11′及
びD11″などを介して直列接続される。 次に第7図は変換部G1〜G3がスイツチング
素子によりブリツジ構成され、セツタタツプの両
波整流回路が直列接続されている場合を示す。 この整流装置においても基本的な制御方法は前
に述べた実施例の方法と全く同じであるので詳述
しない。 次に第8図に示す整流装置は出力側の整流回路
を全波整流ブリツジD9,D9′,D9″とし、夫々の
一方の整流アームd1,d1′,d1″を並列接続して第
1のインダクタL2に直列し、他方の整流アーム
d2,d2′,d2″を並列接続して別の第2のインダク
タL2″に直列している。この装置の基本的な制御
方法も最初の実施例と同じであるが、各変換部が
1個のインダクタL2又はL2′に供給する電圧の波
形の最大デユーテイは1に制限されるから、正、
負のサイクルに分けて各変換部の出力電圧波形の
最大デユーテイの1/2まで利用できるよう、別々
のインダクタL2,L2′から電流を取り出す様にし
たことを特徴とし、スイツチング素子の利用率を
向上させることが出来る。 次に第9図は6個の双方向性スイツチング素子
S1〜S6を3相全波整流構成に接続した基本的
なオン―オン型の3相整流装置を示し、平滑用イ
ンダクタL2はこれを流れる電流が変換周期で一
定になる程度に大きなインダクタンスを有する。 基本的な制御技術は第2図に関連して述べた制
御方法と同じなので詳述しないが、下記表にU―
V相間電圧の0゜から2πまでの期間におけるスイツ
チング素子S1〜S6のスイツチング動作のシー
ケンスの一例を示す。
[Industrial Field of Application] The present invention provides an energy source that depends on a predetermined relationship between a value proportional to the square of the instantaneous voltage value of polyphase AC and a control amount at intervals sufficiently shorter than the cycle of polyphase AC input. Concerning AC-DC conversion to obtain output. [Prior Art] When it is desired to obtain a desired value of DC voltage from a multiphase AC input, for example, a commercial three-phase AC input, a conventional typical switching mode rectifier is shown in Fig. 1. There is. This conventional rectifier has an inductor connected in series to each three-phase AC input terminal.
L u , L v , L w A three-phase full-wave rectifier circuit Rec that consists of six rectifiers D 1 to D 6 and performs full-wave rectification of three-phase AC input.
1. Inductor L 1 and capacitor C 1 that constitute a smoothing circuit that smoothes the output of this three-phase full-wave rectifier circuit,
Switching transistors Q 1 and Q 1 ' are connected in series with each other via the primary winding N 1 of the transformer T, and are conductive during the off period of these switching transistors to transfer the energy in the transformer to the capacitor C 1
diodes D 7 and D 8 , a rectifier D 9 that rectifies the voltage of the secondary winding N 2 of the transformer T, a flywheel diode D 10 , an inductor L 2 and a capacitor C 2 that form the output filter circuit, and the output terminal O ,
It consists of a control circuit C po that controls the pulse width of switching transistors Q 1 and Q 1 ' so as to keep the DC output voltage between O' and output terminals O and O' constant. [Problems to be Solved by the Invention] In such a conventional rectifier, the three-phase AC input is rectified by the three-phase full-wave rectifier circuit Rec1, and then the inductor L1
Since the DC current is smoothed by a smoothing circuit consisting of a capacitor and a capacitor C1 , a pulsed current flows through each phase via the diode of the phase with the highest voltage, so it contains many harmonic components. . Even with the inductors L u , L v , and L w provided in the rectifier circuit Rec1, at least low-order harmonic components cannot be removed. These harmonic components not only cause inductive disturbances in communication circuits and cause them to malfunction, but they also have an adverse effect on peripheral devices connected to the same power supply, and cause power loss in multiphase AC power supplies. Increasing the capacity of the generator and combining it with a generator results in an increase in capacity due to an increase in the power loss of the generator. Another disadvantage is that a smoothing inductor L 1 and a capacitor C 1 are required. [Means for Solving the Problems] The present invention eliminates such conventional drawbacks, and provides a symmetrical polyphase AC and two-phase three-wire system input side and its DC output side with a constant load. Based on the knowledge that the instantaneous value of the energy flow is constant, the multiphase AC input current is controlled in a specific manner by controlling the conduction period of each switching element so that the input current flows in a sinusoidal waveform. It is characterized by being able to reduce harmonic components of the current and obtain a constant DC output with a small ripple component. Symmetrical n-phase AC device with symmetrical loads (n≧3)
In this case, the instantaneous voltage V j on the input side is expressed as V j =√2V n sin {ωt−2π(j−1)/n} (1). However, j=1, 2, 3, . . . n, V n is the effective value of the input voltage V j . Here, the load connected between each phase has a resistance value R
In the case of a resistive load with a resistive load, the instantaneous power P i delivered to the input is P i = oj=1 V j 2 /R = 2V n 2 /R oj=1 sin 2 {ωt− 2π(j-1)/n} ...(2), and oj=1 sin 2 (ωt−2π(j-1)/n} is n/
2, so the instantaneous power P i of the input section becomes P i =n·V n 2 /R (3). This equation (3) shows that the energy flowing in the symmetrical n-phase AC device is constant. Therefore, if the load on the AC input is linear and the DC output side is controlled to obtain constant energy, a sinusoidal multi-phase AC input current will flow on the input side, so harmonics will be sufficiently suppressed. Components can be reduced. Furthermore, in order to extract a certain amount of energy to the DC output side, it can be seen from equation (2) above that it is sufficient to extract energy that is proportional to the square of the instantaneous voltage value of each phase at each point in time of the multiphase AC input. In order to obtain this instantaneous voltage value more precisely, it is desirable to compare the conversion frequency with the frequency of the polyphase AC input and select a value as high as possible. The present invention is based on the above-mentioned findings.
It provides AC-DC conversion. [Embodiments] Each embodiment of the AC-DC conversion according to the present invention will be described in detail below with reference to the drawings. First, one embodiment of the present invention will be explained with reference to FIGS. 2 to 5. The main circuit of the rectifier shown in Fig. 2 consists of inductors L u , L v , L w connected in series to the lines of each phase U, V, and W of the three-phase AC input, and capacitors C u and L w connected between the phases. L v , C w single-phase full-wave rectifier D and capacitor
Rectifier circuits with the same configuration consisting of C 1 ′ Rec1, Rec
2, Rec3, a pair of switching transistors Q 1 and Q 1 ' that perform switching operations at the same time, primary winding
A transformer T having a secondary winding N 1 and a secondary winding N 2 and switching transistors Q 1 and Q 1 ′ conduct when they are off, and the excitation energy stored in the transformer T is fed back to the capacitor C 1 ′. Conversion sections G1, G2, G3 with the same configuration consisting of diodes D 7 and D 8 to
D 9 , D 9 ′, D 9 ″, a flywheeling diode D 10 , inductors L 2 , L 2 ′ forming a smoothing circuit, capacitors C 2 , C 2 ′, and capacitor C 3 ,
A load F is connected to its output end. One of the structural features of the rectifier in this embodiment is that there is no need to provide a smoothing circuit for the input frequency between the rectifier circuit that rectifies each phase voltage and the conversion section, and this is a completely new control system that will be described later. By switching the switching transistors Q 1 and Q 1 ′ to open and close the rectified sinusoidal voltage, harmonic components of the input current can be significantly reduced, and the ripple component can be extremely low in stability. This is to obtain a DC output of 100%. Fig. 3 shows an example of the block configuration of a control circuit that performs this control method, Fig. 4 shows signals indicating the operation timing of each part, and Fig. 5 A and B
2A and 2B are diagrams for explaining input and output waveforms of the conversion section, respectively. In FIG. 3, a reference signal oscillator 1 generates a reference pulse signal at a frequency sufficiently higher than the frequency of the polyphase AC input, for example 20 KHz. This reference pulse signal is shown in FIG. 4 as signal a generated at time t1 . At the rise of this signal a, the reset pulse forming circuit 2 generates a predetermined pulse width, for example, 1μ.
Generates a reset pulse with a pulse width of seconds. This reset pulse is used for reset via OR circuit 5.
It is applied to the gate of FET 6, turns on FET 6 by the width of the pulse, and discharges the charge in capacitor 7 to almost zero. The delay circuit 3 drives the on signal b at a time delayed by a time approximately equal to the carrier accumulation time of the switching transistors Q 1 and Q 1 ' from the fall of the reset pulse, that is, at a time t 2 delayed from the signal a by a time τ. applied to the latch circuit 4. Accordingly, the drive latch circuit 4 applies a drive signal S 1 to the bases of the switching transistors Q 1 and Q 1 ' of the first conversion section G1 to turn them on as shown by the signal d. A capacitor 7 connected in parallel to the FET 6 is charged by a constant current from a controllable constant current source 9 whose constant current value is controlled by an error signal from an error amplifier 8. The error signal output by the error amplifier 8 is a detection signal proportional to the DC output voltage in the rectifier.
Depends on the difference between S d and the reference value. Therefore, after the charging voltage of the capacitor 7 drops to almost zero value by the reset pulse based on the reference signal a, the control amount, in this embodiment, the magnitude of the difference between the output voltage detection signal S d and the reference value It increases with a proportionate rate of increase. The charge voltage of the capacitor 7 is determined by each comparator 10,
10', 10''. Full-wave rectifiers 11, 11', 1 are applied to the negative terminals of these comparators, respectively.
The DC side terminal 1'' of the full-wave rectifier 11 is connected to the resistors 12, 12', and 12'', respectively, and the AC side terminal 1 of the full-wave rectifier 11
A voltage proportional to the U-V inter-phase voltage of the three-phase AC input is applied between 3 and 14, and a voltage proportional to the V-W inter-phase voltage is applied between the AC side terminals 13' and 14' of the full-wave rectifier 11'. Also, the AC side terminal 13'' of the full wave rectifier 11'',
Since a voltage proportional to the voltage between the W and U phases is applied between 14" and 14", a sinusoidal voltage obtained by full-wave rectification of the alternating current voltage between the U and W phases appears at the negative terminal of the comparator 10. , Similarly, the negative terminals of the comparators 10' and 10'' are supplied with the AC voltage between the V and W phases, and the AC voltage between the V and W phases.
A sinusoidal voltage obtained by rectifying the alternating current voltage between the phases is applied. Respective comparators 10, 10', 1
0'' compares the aforementioned voltages applied to the positive and negative terminals, and outputs an off signal when the voltage at the positive terminal becomes equal to the voltage at the negative terminal.The off signal c of the comparator 10 is output at time t. 3 is input to the drive latch circuit 4,
Accordingly, the drive latch circuit 4 stops supplying the base drive signal S 1 to the switching transistors Q 1 and Q 1 ' in the conversion section G1. Therefore, transistors Q 1 and Q 1 ' are turned off at time t 4 after the accumulation time has elapsed, as shown by signal d in FIG. Next, the output signal c from the comparator 10 is input to a reset pulse forming circuit 2' having the same configuration as the circuit 2. Accordingly, the circuit 2' applies a reset pulse similar to the reset pulse generated by the circuit 2 to the gate of the FET 6 via the OR circuit 5, turns it on, and discharges the charge in the capacitor 7. Further, a delay circuit 3' having the same configuration as circuit 3 receives the reset pulse and supplies an on signal e to the drive latch circuit 4' at time t5 delayed by a time τ approximately equal to the carrier accumulation time from the signal c. Accordingly, circuit 4' sends a drive signal to the switching transistor of converter G2.
Apply S 2 to turn it on (signal g).
The capacitor 7 is again charged by a constant current that depends on the magnitude of the output voltage detection signal S d during the on-operation period of the converter G2. This charge voltage is comparator 1
0', the voltage proportional to the V-W phase voltage is compared with the full-wave rectified sinusoidal voltage as described above, and at the time t6 when both voltages become equal, the signal f
is applied to the drive latch circuit 4' and also to the reset pulse forming circuit 2''. When the drive latch circuit 4' receives the signal f, it immediately stops sending out the base drive signal S2 , and accordingly, the converter G2 changes its switch. The reset pulse forming circuit 2'' is turned off at time t7 after the accumulation time of the switching transistor has elapsed.
0', a reset pulse is applied to the gate of FET 6 via OR circuit 5, and this is turned on to instantly discharge the charge in capacitor 7. The third delay circuit 3'' receives the reset pulse from the circuit 2'' and drives the on-signal h to the latch circuit 4'' at time t8 delayed by the time τ from the signal f.
give to Accordingly, the circuit 4'' applies the drive signal S3 to the switching transistor of the converter G3 to turn it on (signal j).The capacitor 7 is once discharged by turning on the FET 6, and the output voltage detection signal is output again. It is charged with a constant current proportional to S d.The charging voltage of the capacitor 7 is compared with the sinusoidal voltage obtained by full-wave rectification of the voltage proportional to the W-U phase voltage of the three-phase AC input by the comparator 10''. , the comparator 10'' detects when these two voltages become equal.
At t9 , an off signal i is applied to the drive latch circuit 4''.
Accordingly, the circuit 4'' stops supplying the drive signal S3 ,
The converter G3 turns off when the storage time of its switching transistor has elapsed (signal j). In the section where all of the rectifiers 9, 9', and 9'' are non-conducting, the energy stored in the inductor L2 is transferred to the diode D10.
Flow through. Each part operates in this way, and one cycle T ends. In FIG. 3, reference numeral 15 indicates a compensation diode for canceling the adverse effect of forward drop in each full-wave rectifier 11, 11', 11''.To summarize the above operation, the switch in each conversion section The switching transistors operate in a time-division manner, that is, they perform switching operations sequentially within each cycle that is sufficiently smaller than one cycle of the multiphase AC input voltage, and moreover, as the switching transistor that is on is turned off, the next switching transistor is turned on. Furthermore, the switching transistor in each conversion section is controlled with a pulse width proportional to the product of the output voltage detection signal and a sinusoidal voltage proportional to each phase voltage, and each switching element is controlled by a pulse width proportional to the product of the output voltage detection signal and a sinusoidal voltage proportional to each phase voltage. The rectified sinusoidal voltage is opened and closed.Therefore, the switching transistors in each converter switch the energy taken out from each phase of the polyphase AC to the output side at a cycle sufficiently shorter than the cycle of the polyphase AC. It can be seen that switching control is performed so that it is proportional to the product of the control amount and a value proportional to the square of the instantaneous voltage value of the polyphase AC (Ksin 2 θt: K is a constant).Furthermore, understand this control method. For the sake of simplicity, the three-phase AC input waveform of the converter in a 180° interval centered on the U phase will be explained with reference to Fig. 5. In Fig. 5A, V 1 is the voltage waveform between UV and V phases, and V 2 is In the V-W phase voltage waveform, V 3 indicates the W-U phase voltage waveform, and in the same figure B, U 1 , U 2 , and U 3 indicate the three-phase AC input waveform.
The output waveforms of the rectifiers D 9 , D 9 ′, and D 9 ″ in each period starting from time t 0 to t 5 corresponding to an interval of 30° are shown enlarged. Each converter G1 to G3 is
For example, each converter G operates at a conversion frequency of 20KHz.
1 to G3 are the corresponding phase-to-phase voltages of the three-phase AC input.
Opens and closes at a conversion frequency of 20KHz. As shown by the chain line in FIG. 5, each output voltage waveform in one cycle starting from time t 0 when the UV phase-to-phase voltage V 1 has a zero value is determined by the output voltage detection signal S as described in detail in the previous embodiment. The switching transistors of each conversion unit G1 to G3 are controlled with a pulse width determined by comparing the charging voltage of the capacitor 7, which depends on d , with the corresponding instantaneous value of the voltage between each phase, and these switching Considering that the transistor opens and closes a sinusoidal voltage obtained by full-wave rectification of the corresponding voltage between each phase, the output U 1 corresponding to the input V 1 at time t 0 has a very small pulse width and amplitude, and the input V 2
Output U 2 corresponding to and output U 3 corresponding to input V 3
It is easily understood that both are approximately equal, and both the pulse width and amplitude are sufficiently large compared to the output U1 . Next, for the sake of illustration, there is a period starting at time t 1 corresponding to 30° of the U phase of the phase AC input (of course, each conversion section is operating at a conversion frequency of 20 KHz even between times t 0 and t 1 ). To explain, the output U 1 increases in both pulse width and amplitude as the input V 1 rises in a sinusoidal waveform, and the output U 2 becomes maximum in both pulse width and amplitude as the input V 2 reaches its maximum amplitude. . Further, as the input V 3 becomes approximately equal to V 1 at time t 1 , the output U 3 becomes approximately equal to the output U 1 in both pulse width and amplitude. Below, each cycle starting from time t 2 , t 3 , . . . t 5 will be similarly explained. In other words, in this example, the frequency of the polyphase AC input is
Assuming 50 Hz, each period is divided into 400 equal parts with a conversion frequency of 20 KHz, and in each of these 400 equal parts, the conversion units G1 to G3 are time-divisionally controlled using the control method described above. The sum of the output voltages U1 to U3 in each of the 400 equally divided conversion cycles is controlled according to the error signal that is the difference between the output voltage detection signal V d and the reference value, so this detection signal V d is constant. If so, the output voltage U in each period is determined by the above equation (3).
It can be seen that the sums of 1 to U3 are all equal to each other. This situation can be seen in Figure 5B, where the output voltage U
If we consider that 1, U2, and U3 are arranged in a line over time and the conversion frequency is made high enough, we can see that the envelope will approach DC as much as possible. Therefore, from equation (3) above, since the instantaneous power P i on the input side is constant, the instantaneous power obtained on the output side is constant, and the pulse width control described above can be performed at a conversion frequency that is sufficiently high relative to the input frequency. If so, a sinusoidal current will naturally flow on the input side simply by removing the high frequency component. In this embodiment as well, the sum of the outputs U 1 to U 3 in each cycle due to the conversion frequency of 20 KHz, which is sufficiently higher than the frequency of the multiphase AC input, is almost constant, so it is possible to obtain a DC output voltage with small ripples, and the input side It can be easily understood that a sinusoidal current with extremely few harmonic components flows through the . Furthermore, according to this AC-DC conversion, as can be seen from the above, when the switching transistor of the converting section G1 is turned off, the switching transistor of the converting section G2 is turned on, and as the switching transistor of the converting section G2 is turned off, the switching transistor of the converting section G3 is turned on. Since it can be controlled so that it turns on, the output side can be connected in parallel using an on-on type converter, and it is easy to generate harmonics at low voltage and large current, and the maximum duty of the converter used in the example is It is possible to increase the utilization rate by up to 1/2. In order to enable this kind of follow-up control, in order to eliminate the influence of the carrier accumulation time of the switching transistor in each conversion section, the on-signal is delayed by approximately the same amount of time, and the pulse width is In order to improve the proportional accuracy with the input voltage, it is desirable to start charging the capacitor 7 before this delay time starts. Next, we will discuss specific examples of characteristics obtained by such AC-DC conversion. However, harmonics range from the 2nd to the 45th order. Input is 3-phase AC (50Hz) 200V, output is
For DC48V, 30A: Harmonics of input voltage - U - V: 1.67%, V -
W: 1.41%, W-U: 2.22% Harmonic component of input current-U: 5.02%, V: 4.07
%, W: 4.75% Power factor - 0.982, efficiency - 88.3%. The control method as described above can also be applied to the rectifier having the configuration shown in FIG.
The outputs of D 9 , D 9 ′, and D 9 ″ are connected in series via diodes D 11 , D 11 ′, D 11 ″, and the like. Next, FIG. 7 shows a case in which the converters G1 to G3 are configured as a bridge by switching elements, and setter-tap double-wave rectifier circuits are connected in series. The basic control method in this rectifier is exactly the same as the method in the previous embodiment, so it will not be described in detail. Next, in the rectifier shown in Fig. 8, the rectifier circuit on the output side is a full-wave rectifier bridge D 9 , D 9 ′, D 9 ″, and one rectifier arm d 1 , d 1 ′, d 1 ″ is connected in parallel. Connect the first inductor L in series with 2 and the other rectifier arm
d 2 , d 2 ′, and d 2 ″ are connected in parallel and connected in series with another second inductor L 2 ″. The basic control method for this device is also the same as in the first embodiment, but the maximum duty of the voltage waveform that each converter supplies to one inductor L 2 or L 2 ' is limited to 1. Positive,
The feature is that the current is taken out from separate inductors L 2 and L 2 ' so that it can be divided into negative cycles and used up to 1/2 of the maximum duty of the output voltage waveform of each conversion section. It is possible to improve the rate. Next, Fig. 9 shows a basic on-on type three-phase rectifier in which six bidirectional switching elements S1 to S6 are connected in a three-phase full-wave rectification configuration, and the smoothing inductor L2 is connected to this. The inductance is large enough to keep the flowing current constant during the conversion period. The basic control technology is the same as the control method described in relation to Figure 2, so it will not be described in detail, but the table below shows
An example of a sequence of switching operations of switching elements S1 to S6 during a period from 0° to 2π of the V-phase voltage is shown.

〔発明の効果〕〔Effect of the invention〕

以上述べた様に本発明によれば、スイツチング
素子を多相交流の周波数よりかなり高い変換周波
数でスイツチングさせ、その変換周波数による周
期毎に各相より出力側に取り出すエネルギが多相
交流の2乗と制御量との積に比例すると共に、各
相から取り出すエネルギの総和が前記制御量に比
例する様に制御しているので、高調波成分の非常
に小さい入力電流を流すことが出来るために通信
回路などにおける高調波成分による誘導障害を防
ぐことが出来、また高周波リツプルの小さい一定
の出力電圧を得ることが出来る。更にこの発明に
よれば、入力側の整流回路と変換部との間に平滑
回路を設ける必要がないので装置を小型化でき
る。 尚、スイツチング素子としてトランジスタの他
にサイリスタなどを用いることが出来るのは当然
であり、以上の実施例では対称3相交流入力につ
いて述べたが、他の多相入力又は2相3線式でも
同様であり、入力波形が多少変形している場合で
も帰還ループでもつて入力におけるエネルギの流
れを一定に制御することにより出力におけるリツ
プルの低減を行える。
As described above, according to the present invention, the switching element is switched at a conversion frequency considerably higher than the frequency of the multiphase AC, and the energy taken out from each phase to the output side for each period according to the conversion frequency is the square of the multiphase AC. Since it is controlled so that the total energy extracted from each phase is proportional to the product of the control amount and the control amount, it is possible to flow an input current with very small harmonic components. Inductive disturbances due to harmonic components in circuits can be prevented, and a constant output voltage with small high frequency ripples can be obtained. Further, according to the present invention, there is no need to provide a smoothing circuit between the rectifier circuit on the input side and the converter, so the device can be made smaller. It goes without saying that a thyristor or the like can be used in addition to a transistor as a switching element, and although the above embodiment describes a symmetrical three-phase AC input, the same applies to other polyphase inputs or two-phase three-wire systems. Even if the input waveform is slightly deformed, ripples at the output can be reduced by controlling the energy flow at the input to be constant in the feedback loop.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の整流装置の制御方法を説明する
ための図、第2図は本発明の一実施例を実施する
ための整流装置の一例を示す図、第3図はその制
御回路のブロツク構成を示す図、第4図は各部の
動作のタイミングを示す信号を表わした図、第5
図は入、出力側の波形を説明するための図、第6
図乃至第8図及び第9図乃至第11図は夫々本発
明に係る整流制御の制御方法を実施例するための
整流装置の異なる例を示す図である。 Rec1〜Rec3……整流回路、G1〜G3……
変換部、F……負荷、Cpo……制御回路、1……
基準信号発生器、2,2′,2″……リセツトパル
ス形成回路、3,3′,3″……遅延回路、4,
4′,4″……駆動ラツチ回路、5……OR回路、
8……誤差増幅器、9……可制御定電流源、1
0,10′,10″……比較器。
Fig. 1 is a diagram for explaining a conventional method of controlling a rectifier, Fig. 2 is a diagram showing an example of a rectifier for carrying out an embodiment of the present invention, and Fig. 3 is a block diagram of the control circuit. Figure 4 is a diagram showing the configuration, Figure 4 is a diagram showing signals indicating the operation timing of each part, and Figure 5 is a diagram showing the operation timing of each part.
The figure is a diagram to explain the input and output side waveforms.
FIGS. 8 to 8 and 9 to 11 are diagrams showing different examples of rectifiers for implementing the rectification control method according to the present invention, respectively. Rec1~Rec3... Rectifier circuit, G1~G3...
Conversion section, F...Load, C po ...Control circuit, 1...
Reference signal generator, 2, 2', 2''...Reset pulse forming circuit, 3, 3', 3''...Delay circuit, 4,
4', 4''...drive latch circuit, 5...OR circuit,
8...Error amplifier, 9...Controllable constant current source, 1
0, 10', 10''... Comparator.

Claims (1)

【特許請求の範囲】 1 多相交流を入力とし、スイツチング素子のオ
ン時に該スツチング素子を介して出力にエネルギ
を送出して出力電圧を得る整流装置の制御方法に
おいて、前記各相のスイツチング素子を多相交流
の周波数より高い変換周波数で、且つこの変換周
波数で決まる各周期においてオンしている相のス
イツチング素子のオフに伴い他の相のスイツチン
グ素子がオンするごとくして上記各相のスイツチ
ング素子が順次一通りスイツチング動作を行う様
に制御すると共に、前記変換周波数で決まる各周
期において多相交流の各相より出力側に取り出れ
る電力が多相交流の瞬時電圧の2乗に比例する値
と検出信号に応じた制御量とに依存する様に制御
することを特徴とする整流装置の制御方法。 2 各相の前記スイツチング素子が予め決められ
たシーケンスでスイツチング動作を行うことを特
徴とする特許請求の範囲1に記載した整流装置の
制御方法。 3 各相の前記スイツチング素子が多相交流入力
の各相における検出された電圧値の大きい又は小
さい相の順序でスイツチング動作を行うことを特
徴とする特許請求の範囲1に記載した整流装置の
制御方法。
[Scope of Claims] 1. A method for controlling a rectifier which receives multiphase alternating current as input and obtains an output voltage by sending energy to an output through the switching element when the switching element is turned on, wherein the switching element of each phase is At a conversion frequency higher than the frequency of the multiphase alternating current, and in each period determined by this conversion frequency, the switching elements of each phase are turned on as the switching elements of the other phases are turned on as the switching elements of the phases are turned off. control so that the switching operation is performed in sequence, and the power that can be extracted from each phase of the multiphase AC to the output side in each cycle determined by the conversion frequency is proportional to the square of the instantaneous voltage of the multiphase AC. 1. A method for controlling a rectifier, characterized in that control is performed in a manner dependent on a control amount according to a detection signal and a control amount according to a detection signal. 2. The method of controlling a rectifier according to claim 1, wherein the switching elements of each phase perform switching operations in a predetermined sequence. 3. Control of the rectifier according to claim 1, wherein the switching elements of each phase perform switching operations in the order of the phases in which the detected voltage value in each phase of the multiphase AC input is larger or smaller. Method.
JP57173646A 1982-10-01 1982-10-01 Controlling method for rectifier Granted JPS5963976A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP57173646A JPS5963976A (en) 1982-10-01 1982-10-01 Controlling method for rectifier
JP1030640A JPH01252174A (en) 1982-10-01 1989-02-09 Rectifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57173646A JPS5963976A (en) 1982-10-01 1982-10-01 Controlling method for rectifier

Publications (2)

Publication Number Publication Date
JPS5963976A JPS5963976A (en) 1984-04-11
JPS642033B2 true JPS642033B2 (en) 1989-01-13

Family

ID=15964467

Family Applications (2)

Application Number Title Priority Date Filing Date
JP57173646A Granted JPS5963976A (en) 1982-10-01 1982-10-01 Controlling method for rectifier
JP1030640A Pending JPH01252174A (en) 1982-10-01 1989-02-09 Rectifier

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP1030640A Pending JPH01252174A (en) 1982-10-01 1989-02-09 Rectifier

Country Status (1)

Country Link
JP (2) JPS5963976A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0523983U (en) * 1991-05-10 1993-03-30 東京ユタカ電子株式会社 Pseudo incense holder

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06101932B2 (en) * 1986-01-11 1994-12-12 株式会社日立製作所 Control device for PWM converter
DE3603071A1 (en) * 1986-02-01 1987-08-06 Leybold Heraeus Gmbh & Co Kg DC-AC CONVERTER WITH ASYMMETRIC SEMI-BRIDGE CIRCUIT
JP2566579B2 (en) * 1987-06-25 1996-12-25 三菱電機株式会社 Power converter
JPH05336752A (en) * 1992-05-27 1993-12-17 Hitachi Ltd Switching regulator
JP2005223978A (en) * 2004-02-04 2005-08-18 Fuji Electric Fa Components & Systems Co Ltd Motor drive device
US8687388B2 (en) * 2012-01-31 2014-04-01 Delta Electronics, Inc. Three-phase soft-switched PFC rectifiers

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58133170A (en) * 1982-01-29 1983-08-08 Matsushita Electric Works Ltd Dc power source device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0523983U (en) * 1991-05-10 1993-03-30 東京ユタカ電子株式会社 Pseudo incense holder

Also Published As

Publication number Publication date
JPS5963976A (en) 1984-04-11
JPH01252174A (en) 1989-10-06

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