JPS642271B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state image sensor with a blooming function that can provide a good image output signal even with particularly excessive incident light.

Solid-state image sensors, typified by charge transfer devices, are replacing image pickup tubes because they have features such as small size, light weight, low power consumption, and high reliability. In such a solid-state image sensor, when the intensity of incident light is extremely high, image blurring called blooming occurs, so a blooming prevention function is provided in order to obtain a good image output signal.

1 and 2 show the structure of an interline charge transfer area image sensor, which is an example of a conventional solid-state image sensor, and is equipped with the above-mentioned blooming prevention function. Figure 2 is a sectional view taken along line A-A'.
In the figure, 1 is, for example, a P-type semiconductor substrate. On the surface area of this substrate 1, a plurality of N-type semiconductor regions 2a, 2b, 2a, 2b, 2a, 2b, 2a, 2b, 2a, 2b, 2a, 2b, 2a, 2b, 2b, 2b, which together with this substrate constitute a photodiode (photosensitive pixel), are formed in a surface area of the substrate 1.
...and 3a, 3b, ... are formed. Further, the N-type semiconductor regions 2a, 2b, ... and 3
A, 3b, . . . On one side along each array, a plurality of transfer gate electrodes 4a, 4b, .
a, 5b, . . . are formed. Further, the N-type semiconductor regions 2a, 2b, . . . and 3a, 3b, .
On the other side along each array are control gate electrodes 6 and 7 to which a positive DC voltage is always supplied.
is formed. The surface area of the substrate 1 adjacent to each of the control gate electrodes 6 and 7 is provided with an N-type electrode which is constantly supplied with a positive DC voltage higher than the DC voltage supplied to the control gate electrodes 6 and 7. Each drain region 8,9 is formed. In the figure, 10 is a light-transmitting insulating film, 11 is a light shielding film, 12 is an N-type buried channel region, 13 is a semiconductor region for forming a transfer barrier, 14, 1
5 are P-type channel blocking semiconductor regions, respectively.

In such a configuration, first the optical shield film 1 is
When light is irradiated to the opening of 1, the substrate 1 and each of the N-type semiconductor regions 2a, 2b, . . . and 3a, 3
A signal charge corresponding to the intensity of the incident light is generated in the photodiode composed of the photodiodes b, . Next, a voltage for reading signal charges is applied to each transfer gate electrode 4a, 4.
b,... and 5a, 5b,..., these respective transfer gate electrodes 4a, 4b,... and 5
a, 5b, . . . A deep potential well is induced inside the substrate 1 below, and the signal charge moves into this potential well. Furthermore, when a clock pulse is supplied to each transfer gate electrode 4a, 4b, . . . and 5a, 5b, . Furthermore, it is output as a serial image signal via a shift register (not shown) arranged two-dimensionally.

By the way, in the above conventional device, a positive DC voltage is supplied to each control gate electrode 6, 7,
Further, since a DC voltage of higher positive polarity than this is supplied to each drain region 8, 9, a potential barrier is formed inside the substrate 1 under each control gate electrode 6, 7. Therefore, if the intensity of the incident light is extremely strong and the signal charges generated in the photodiode become excessive and exceed the potential barrier, the excess signal charges will flow into each of the drain regions 8 and 9. Therefore, the above conventional device can prevent blooming from occurring. However, the drain regions 8, 9 and each N-type semiconductor region 2
It is necessary to form control gate electrodes 6, 7 between the gate electrodes a, 2b, . . . and 3a, 3b, . . . , which makes high integration difficult. In addition, in order to achieve particularly high integration, it is necessary to adopt a multilayer electrode structure.
As a result, the number of manufacturing steps increases and the manufacturing yield decreases. Furthermore, conventionally, a power source for supplying DC voltage to the control gate electrodes 6 and 7 is also required.

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to enable high integration and to reduce the number of types of DC power supplies required.
An object of the present invention is to provide a solid-state image sensor with a blooming prevention function.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. 3 and 4 show the structure of a solid-state image sensor according to the present invention applied to an interline charge transfer area image sensor in the same way as in the prior art; FIG. 3 is a plan view, and FIG. The figure is a sectional view taken along line B-B'. In addition,
The same reference numerals are given to the parts corresponding to the conventional one, and the explanation thereof will be omitted, and only the different parts will be extracted and explained. That is, in this embodiment device, the control gate electrodes 6 and 7 are removed, and instead of each drain region 8 and 9, a plurality of N-type semiconductor regions 2a, 2b, . . . and 3a, 3 are arranged.
N-type semiconductor regions 21 and 22 (only region 21 is shown) are formed in the surface region of the substrate 1 between b, .
Furthermore, P-type semiconductor regions 23 and 24 (only region 23 is shown) are formed in the surface regions of these N-type semiconductor regions 21 and 22, respectively.

FIG. 5a is a distribution characteristic diagram showing the distribution state of the depletion layer in a part of the embodiment device shown in FIG. 3 above.
Since a high positive voltage is supplied to the drain region 8, carriers (electrons) are almost depleted in the N-type semiconductor region 21, and a depletion layer spreads throughout the region. Moreover, as a result, a depletion layer 2 is also formed in the portion of the substrate 1 that is in contact with the N-type semiconductor region 21.
5 expands, the depletion layer 26 also expands in the P-type semiconductor region 23. However, most regions of the substrate 1 and the vicinity of the surface of the P-type semiconductor region 23 are filled with carriers (holes).

FIG. 5b is a distribution characteristic diagram showing the potential distribution along line C-C' in FIG. 5a. As the depletion layer spreads as described above, a potential peak V _M is generated near the boundary between the substrate 1 and the N-type semiconductor region 21. This potential V _M is a constant potential independent of the voltage supplied to the drain region 8 as long as the potential in the drain region 8 is equal to or higher than V _M . Therefore, it is essential that the impurity concentration and thickness (depth) of the N-type semiconductor regions 21 and 22 and the P-type semiconductor regions 23 and 24 are set so that the constant potential V _M is generated. ing. Since the practically desirable value of V _M is about 0.3 (V) to 5 (V), for example, if the impurity concentration of substrate 1 is
×10 ¹⁴ to 2 × 10 ¹⁵ (atoms/cm ³ ), and the impurity concentration of the N-type semiconductor regions 21 and 22 to 5 × 10 ¹⁵ to 4 × 10 ¹⁶
(atoms/cm ³ ), the impurity concentration of the P-type semiconductor regions 23 and 24 is 2×10 ¹⁶ to 2×10 ¹⁷ (atoms/cm ³ ), and the thickness of the N-type semiconductor regions 21 and 22 is 0.4 to 1 (μm). ,
The thickness of the P-type semiconductor regions 23 and 24 is set to 0.1 to 0.4 (μ
m), the value of V _M is set to 0.3 (V) above.
~5(V) can be kept constant. Furthermore, this
The value of V _M is maintained constant without being affected even when wiring is formed on the N-type semiconductor regions 21 and 22 and the P-type semiconductor regions 23 and 24 via the insulating film 10. The impurity concentration and thickness of each region are set.

FIG. 6 shows the potential distribution in the cross-sectional view shown in FIG. 4 above. The overall operation of this embodiment apparatus will be explained below using FIG. 6.
First, in order to supply a high voltage V _D to the drain region 8, a barrier with a constant potential V _M is formed inside the substrate 1 under the N-type semiconductor region 21 as described above.
On the other hand, when the low level voltage V _L for signal charge transfer is supplied to the transfer gate electrode 4c, the potential distribution becomes as shown by the solid line in FIG. 6, and the high level voltage V _M for signal charge transfer is supplied to this electrode. When this happens, the potential distribution becomes as shown by the broken line in FIG. 6, and when the voltage V _T for signal reading is further supplied, the potential distribution becomes as shown by the dashed line.

Now, when the voltage V _T for reading signal charges is supplied to the transfer gate electrode 4c, the signal charges _Q1 previously accumulated in the N-type semiconductor region 2c move below the transfer gate electrode 4c, and the clock pulse By sequentially supplying the charges Q 1 , this charge Q ₁ is transferred under the other transfer gate electrodes. On the other hand, during the period when signal charges are being transferred by the transfer gate electrode, signal charges are generated in the photodiode consisting of the N-type semiconductor region 2c and the substrate 1 according to the intensity of the incident light, and these charges always remain in the region 2c. The remaining charge _Q2 is added to the N-type semiconductor region 2.
It is accumulated in c. At this time, when the intensity of the incident light is strong and the charges accumulated in the region 2c reach V _M , the excess charges are discharged to the drain region 8 over the potential barrier of V _M , so that the N-type semiconductor region 2c
The signal charge accumulated in c never exceeds a predetermined amount. Therefore, blooming can be prevented against excessive incident light intensity.

In this way, in the above embodiment, the drain region 8 or 9 is used instead of the conventional control gate electrode.
and each N-type semiconductor region 2a, 2b,... or 3
Since the N-type semiconductor region 21 or 22 and the P-type semiconductor region 23 or 24 are provided between the electrodes a, 3b, . is possible, and the number of manufacturing steps is also reduced, making it possible to obtain a high yield. Furthermore, no DC power source is required to prevent blooming other than the voltage V _D supplied to the drain regions 8 and 9.

FIG. 7 is a sectional view showing another embodiment of the present invention, and shows another example of a photosensitive pixel. In the above embodiment, the photosensitive pixel is a photodiode composed of a P-type substrate and an N-type semiconductor region formed on the surface area of this substrate. It may be constructed from a photodiode consisting of a substrate 1 and an N-type half region 2c, and a MOS diode including a pair of storage gate electrodes 31 and 32 formed on both sides of the photodiode.

FIG. 8 is a sectional view showing still another embodiment of the present invention, and shows another example of a photosensitive pixel. In this embodiment, the photosensitive pixel is constituted by a MOS type diode consisting of a transparent electrode 41 formed in an insulating film 10 and a substrate 1.

FIG. 9 is a sectional view showing another embodiment of the present invention. In the embodiment described above, a voltage for reading signal charges is supplied to each transfer gate electrode 4a, 4b, . . . and 5a, 5b, .
The case where signal charge reading and transfer are performed in each case has been described, but in this case, as shown in FIG. 9, a gate electrode 51 exclusively for signal charge reading is newly formed, and a voltage for signal charge reading is supplied to this gate electrode. You can do it like this.

Furthermore, the present invention is not limited to the above embodiments. For example, in the above embodiment, the case where the conductivity type of the substrate 1 is P type has been described, but it goes without saying that it may be of N type. Furthermore, in the above embodiment, the case where the present invention is applied to an interline type charge transfer area image sensor is explained, but this can also be easily applied to other X-Y address type solid-state image sensors, charge transfer linear image sensors, etc. It is.

As described above, according to the present invention, it is possible to provide a solid-state image sensor that is highly integrated, requires fewer types of DC power supplies, and has a blooming prevention function.

[Brief explanation of drawings]

Figures 1 and 2 show the configuration of a conventional solid-state image sensor, respectively. Figure 1 is a plan view, Figure 2 is a sectional view taken along line A-A',
4 and 4 respectively show the structure of an embodiment of the present invention, FIG. 3 is a plan view, FIG. 4 is a sectional view taken along the line B-B', and FIGS. In order to explain the above embodiment, the distribution characteristic diagram, No. 6
The figure is a distribution characteristic diagram for explaining the above embodiment, and FIGS. 7 to 9 are sectional views showing the configuration of other embodiments of the present invention. 1...P-type semiconductor substrate, 2a, 2b,..., 3
a, 3b,...N-type semiconductor region, 4a, 4b,
..., 5a, 5b, ... transfer gate electrode, 8, 9...
...Drain region, 10...Insulating film, 11...Light shield film, 21...N-type semiconductor region, 23...P
type semiconductor region, 31, 32...storage gate electrode,
41...Transparent electrode, 51...Gate electrode exclusively for reading signal charges.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate of one conductivity type, a plurality of arranged photosensitive pixels that generate signal charges according to the intensity of incident light and accumulate the signal charges inside the substrate;
means for reading signal charges accumulated in each of the plurality of photosensitive pixels; a drain region of the other conductivity type provided on the surface region of the substrate along the arrangement direction of the plurality of photosensitive pixels; a first region of the other conductivity type provided in the surface region of the substrate between the pixels; and a second region of the one conductivity type provided in the surface region of the first region; A solid-state image sensor characterized in that a potential barrier is induced, and excess signal charges generated in each of the plurality of photosensitive pixels are discharged to the drain region beyond the induced barrier. 2. The solid-state image sensor according to claim 1, wherein the photosensitive pixel is a MOS diode configured by providing a light-transmitting electrode on the surface of the substrate via an insulating layer. 3. The solid-state image sensor according to claim 1, wherein the photosensitive pixel is a photodiode formed by providing a semiconductor region of a conductivity type different from that of the substrate in a surface region of the substrate.