JPS642982B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a replacement memory control method, and more specifically, in a storage device having an original memory and a replacement memory used as a replacement for the original memory, the present invention relates to a replacement memory control method. This relates to conditions for using alternate memory when switching to memory.

Technological advances in semiconductor memory have been extremely remarkable in recent years, and as large-capacity memory cells are built into chips, the transistors that make up the memory cells and the conductor patterns for interconnecting these cells are becoming smaller. .

However, as transistors and conductive wires become finer, in addition to hard errors caused by material defects caused by the destruction of the material that makes up the memory cells, there are also hard errors caused by the "1" or "1" held in the memory cells. A soft error in which the information of "0" is reversed becomes a problem.

Here, a soft error is a single-bit error that occurs randomly in a memory device and does not repeat, and this error is not permanent. Therefore, the bit in which a soft error has occurred will be completely recovered in the next write cycle for that bit.

Soft errors that occur in dynamic memory systems that use memory elements that hold binary information depending on whether or not there is decimal carrier charge in so-called storage capacitors such as MOS dynamic RAM and CCD are caused by system noise, voltage margin limits, In addition to the sense amplifier or pattern sensitivity, a new mechanism for soft errors is that strong ionizing radiation (mainly alpha radiation) from package materials temporarily reverses the dynamic node. It has become clear that soft errors are caused by

Soft errors caused by α rays and the like are largely related to the amount of accumulated charge. In other words, when we associate the state where charges are accumulated with information “1” and the state where charges are discharged and are empty with information “0”, “1” and “0”
If the critical charge, which is the boundary charge of

However, in general, as memory devices become more highly integrated, the transistors forming the cells become smaller and the critical charge also becomes smaller, as described above. This results in an increase in the frequency of soft errors caused by alpha rays and the like.

When configuring high-reliability storage, typically 1
An error correction mechanism (SEC-DED) for bit error correction and 2-bit error detection is provided.
If soft errors like the one above occur frequently, this
Even with the SEC-DED code, sufficient device reliability cannot be obtained. In other words, there are cases where soft 1-bit errors overlap, resulting in 2-bit or more errors, or cases where there is a 1-bit error due to a fixed hardware failure, and then a soft 1-bit error overlaps, resulting in 2-bit or more errors. This is because

As a means of erasing soft errors themselves, for example, as shown in Japanese Patent Publication No. 51-28484, apart from writing or reading operations from an external central processing unit or channel control unit to the memory, there is a method to periodically erase the memory. Read out and if there is an error,
It is conceivable to provide scanning means for correcting the error and rewriting the corrected data into the memory.

However, it is impossible to correct the hardware failure itself by such periodic scanning means.

On the other hand, there is a method of separately providing alternative memory (replacement memory) in case of memory failure.

Figure 1 is an example of a replacement memory, together with the first memory of A word n bits used normally,
A second memory with a smaller capacity of A words and m bits is prepared as a replacement memory. And, for example,
The k-th bit (A word x 1 bit) of the first memory where the hardware failure occurred is replaced with 1 bit (A word x 1 bit) of the second memory. However, even if such a spare memory is prepared, switching to the spare memory every time an error occurs, especially in devices where soft errors such as those described above frequently occur, will result in insufficient spare memory no matter how much spare memory there is. It ends up.

An object of the present invention is to solve the above-mentioned drawbacks and realize a highly reliable storage device without increasing the capacity of spare memory even in devices where soft errors occur frequently. A storage device having a first memory for storing processing programs and data, etc., and a second memory used as a substitute for the error location in the first memory when an error occurs in the first memory. In this method, when an error occurs in the read operation of the first memory, means is provided for determining whether or not the data error is a recoverable error by rewriting, and the error is classified as an error other than a recoverable error. Only when it is determined, the second memory is used as a substitute for the error bit position in the first memory.

The present invention will be explained below with reference to the drawings.

FIG. 2 shows an example of the configuration of a storage device according to an embodiment of the present invention. In Figure 2, A is the central processing unit
It is an external device such as a CPU, and B is a storage device.
The memory M consists of an information bit storage section MD and a check bit storage section MC, and MA is a replacement memory.

WS is data written to memory from an external device
This is a write data selection circuit that switches between _l1 and the output _l9 of the read data correction circuit DC. Output of this WS
_l2 is sent to MD and check bit generation circuit CG, and further to write data selection circuit MPX for spare memory. In CG, check bits used to correct error data in information bits are generated based on _l2 . Generated check bit l ₃
becomes the MC's write data and is sent to the MC as well as to the MPX.

When the alternate memory is not used, the respective read data _l4 and _l5 of MD and MC are not switched with the read data _l15 of the alternate memory MA in the read data selection circuit RS, and are read data as _l6 . It is sent to the correction circuit DC and also to the syndrome calculation circuit SG. The syndrome is calculated in SG, and if an error is detected, the error syndrome signal _l7 is used as the first
to the decoder DEC. The DEC identifies the error bit position and sends an error bit indication signal.
_l8 is sent to the DC, the data at the error bit position of _l6 is corrected by the DC, and the corrected data is transferred to the external device. The error syndrome that is the output of SG is stored in the syndrome memory circuit SM
The error syndrome is also stored.
This SM has a circuit that compares the error syndrome generated in the next read operation with the previously stored error syndrome, and a circuit that stores the syndrome as a replacement syndrome when both syndromes match. There is. The replacement syndrome _l16 is sent to the next second decoder DEC, and the replacement bit position is pointed out. The replacement bit position indication signal _l17 , which is the output of the DEC, is sent to the MPX and RS. At this time, MPX uses the information in _l17 to determine which data in _l2 and _l3 to use as data to be written in the spare memory. Then, the output _l14 of MPX becomes the write data of MA. Similarly,
In RS, which data of _l4 or _l5 is to be switched to _l15 is determined based on the information of _l17 .

l ₂₀ is a signal that notifies the alternating operation control circuit PC whether there is an error in the read data;
When the PC receives the signal _l20 , it holds the address _l10 for memory M.

AS is an address selection circuit which switches between the memory address _l10 from an external device and the replacement address signal _l18 held by the PC to obtain the address _l12 of M and MA. GS is a start signal switching circuit for switching between the memory start signal _l11 sent from an external device and the memory start signal _l19 from the PC.
In the GS, a memory activation clock _l13 is created by the selected activation signal. l ₁₃ is M and MA
sent to.

If we now detect an error in SG, by signal l ₂₀
The PC sends a busy signal _l25 to the CPU to inhibit CPU access, and also outputs a signal _l23 to
Control is performed to select l ₁₈ in GS and l ₁₉ in GS. Furthermore, the PC instructs the WS to use _l9 instead of _l1 by signal _l24 , and then sends l19 and _l19 .
l By sending ₁₈ to AS and GS, a rewrite operation is performed to the memory. Next, again l ₁₉ and l ₁₈
By sending data to AG and GS, the data is read from memory again, and the syndrome is calculated in SG. If the syndrome is correct, the signal
Since l ₂₀ is sent, the PC considers the memory error to be a soft error, turns off signals l ₂₃ and l ₂₅ , and entrusts subsequent access to the CPU. On the other hand, if the syndrome is mistaken, the error syndrome is
The information is sent to the SM, where it is compared with previously stored error syndromes. If they match, the PC is notified of this using a signal _l21 , and the PC determines whether or not to perform a replacement, and notifies the SM of the replacement instruction using a signal _l22 .

In the case of a hard error, the error is detected at the same bit position of all data read from M. Therefore, the PC performs control such that the data of the bit where the error is detected is written to the MA for all address data of M.

Writing is performed as follows.

The PC has an address counter equal to the number of addresses of MA, inhibits CPU access by sending a signal _l25 to the CPU, specifies an address for M using the counter, and reads data. The syndrome of the read data is calculated by SG, and DEC
identifies the erroneous bit position, and the DC corrects the error using the information from the DEC. The corrected data is sent to MPX via WS. MPX is DEC
Based on the information (narrative bit position similar to DEC), data containing only error bits is written to MA.
When the above procedure is completed, add 1 to the counter, and
Read and modify data at all addresses.
Write to MA.

When writing of MA is completed, the PC releases the signal _l25 and further causes WS, AS, and GS to select _l1 , _l10 , and _l11 . Thereafter, when a write is instructed by the CPU, the MPX writes only the bits in which the above-mentioned error is detected to the MA based on the information from the DEC. Also, when read is instructed, RS replaces only the bit where the above error is detected based on the information from DEC in the data read from MD and MC.
Transfer to CPU, etc.

In this example, to simplify the explanation, M and MA
have the same address length. In reality, M is usually much larger than MA. In this case, among the addresses held in the PC at the time of error occurrence, only the addresses that exceed MA are stored in another register, and by comparing and checking with this register in subsequent accesses, if they match, It is only necessary to control the write operation to the MA and the conversion operation to the RS.

Incidentally, the concrete circuit of the above MPX may be a simple n-choice circuit when MA is 1 bit x A word (that is, m in FIG. 1 is 1). Also, RS is also a two-choice circuit (M
(choice between each bit from MA and 1 bit from MA)
It is sufficient to provide n sets of . These can be easily realized by combining AND and OR gates. Further, when m is 2 or more, some additional circuitry is required, but it can basically be realized by applying the above-mentioned configuration.

As described above, in the SM, there is a circuit that compares the error syndrome generated in the next read operation with the previously stored error syndrome, and a circuit that stores the syndrome as a replacement syndrome when both syndromes match. have,
Although fixed hardware failures are identified, there are two hardware failure identification methods shown below depending on the type of error syndrome to be compared.

A first method for identifying a hardware failure in the embodiment is to perform a read operation on address _A0 of a memory consisting of, for example, M words and N bits (number of information digits);
If an error is detected, the error bit position is memorized, the error data is corrected, and the corrected data is written to address _A0 of the memory;
After that, execute the read operation for address A ₀ again,
In this method, when an error is detected, it is checked whether the error bit position matches the previously stored error bit position, and if they match, the error bit position is switched to a replacement memory.

The second method for identifying hardware failures is that when a data error occurs in a read operation at address _A0 , the error bit position is memorized, and the next read operation is performed on at least one address other than address _A0 , for example, address _A1 . Execute and check whether there is an error. If an error occurs, detect whether the error bit position matches the error bit position with the previously stored address _A0 . If so, this error is determined to be a hardware failure over multiple addresses, and the error bit position is replaced by a spare memory.

FIG. 3 is an operation flow diagram showing the operation in the first method, and FIG. 4 is an operation flow diagram showing the operation in the second method. Since the operational flow diagrams in FIGS. 3 and 4 are thought to be easily understood, detailed explanations will be omitted.

As described above, according to the present invention, the soft error itself is relieved by the periodic scanning means, and in order to save a failure in which a soft 1-bit error overlaps with a hard failure, resulting in an error of 2 bits or more, the hard failure is Since we can identify whether it is an error and switch to replacement memory if it is a hardware failure, we can now use replacement memory only for hardware failures, making it possible to use high-reliability storage devices without increasing the replacement memory capacity. It can be realized.

[Brief explanation of drawings]

FIG. 1 is an example of a spare memory, FIG. 2 is an example of the configuration of a storage device according to an embodiment of the present invention, FIG. 3 is an operation flow diagram showing a first method of identifying hardware failures in the embodiment, and FIG. 4 is an example of a replacement memory. FIG. 7 is an operation flow diagram showing a second method for identifying hardware failures in the embodiment. Second
In the figure, A is an external device, B is a storage device, M is a memory, MD is an information bit storage section, MC is a check bit storage section, MA is a replacement memory, WS is a write data selection circuit, DC is a read data correction circuit,
CG is a check bit generation circuit, MPX is a write data selection circuit for alternating memory, RS is a read data selection circuit, SG is a syndrome calculation circuit, SM is a syndrome storage circuit, PC is an alternation operation control circuit,
AS is an address selection circuit, and GS is a start signal switching circuit.

Claims (1)

[Scope of Claims] 1. A first memory for storing processing programs, data, etc. used in an information processing device, and used as a substitute for the error location of the first memory when an error occurs in the first memory. A storage device having a second memory in which an error has occurred is provided with an error occurrence bit position storage means for storing an error occurrence bit position, and when a correctable 1-bit error occurs in the read data in the read operation of the first memory, The error occurrence bit position is compared with the error occurrence bit position of the previous data error that has already occurred in the error occurrence bit position storage means, and if the positions are the same, the corresponding address in the first memory is A replacement memory control method characterized in that the second memory is used as a storage means for the bit position in all data of a plurality of addresses including. 2. When a correctable 1-bit error occurs in the read operation for the address _A0 of the first memory, the data bit position at the address _A0 is stored, the error data is corrected, and the corrected data is stored. Write to the address A ₀ , and then,
If an error occurs again at the same bit position by executing the read operation for the _A0 address again, the second memory is used as a substitute for the error bit position in the first memory. A replacement memory control method according to claim 1.