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JPS643058B2 - - Google Patents
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JPS643058B2 - - Google Patents

Info

Publication number
JPS643058B2
JPS643058B2 JP58060536A JP6053683A JPS643058B2 JP S643058 B2 JPS643058 B2 JP S643058B2 JP 58060536 A JP58060536 A JP 58060536A JP 6053683 A JP6053683 A JP 6053683A JP S643058 B2 JPS643058 B2 JP S643058B2
Authority
JP
Japan
Prior art keywords
bump
bumps
bonding
external
lead wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58060536A
Other languages
Japanese (ja)
Other versions
JPS59186347A (en
Inventor
Minoru Masakado
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP58060536A priority Critical patent/JPS59186347A/en
Publication of JPS59186347A publication Critical patent/JPS59186347A/en
Publication of JPS643058B2 publication Critical patent/JPS643058B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07553—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To realize simultaneous probing to all bumps by providing two or more bumps which are electrically and physically connected to the inside and outside of IC at the time of providing the bumps to IC, and respectively using the external bump for bonding and internal bump for wiring connections. CONSTITUTION:In the case of forming the bump for bonding at the surface of IC element 1, the bump 2a located at the external side of element 1 surface and the bump 2b located at the internal side of element 1 are provided and these are connected by the wirings 2c of the same substance. Thus, such an element 1 is fixed on the substrate 5, the bonding area 3b of external terminal 4 provided to the substrate 5 and the bonding area 3a of bump 2a are connected using the lead wire 3 and the bump 2b is placed in contact with a probe. Thereby, if sink 6 is generated at the bump 2a, the surface heights of bumps 2b are aligned with each other and simultaneous probing can be realized.

Description

【発明の詳細な説明】 (1) 発明の属する技術分野の説明 本発明は集積回路の配線用入出力端子の物理的
構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to the physical structure of wiring input/output terminals of integrated circuits.

(2) 従来技術の説明 従来の集積回路（以下ICと呼ぶ）の配線用入
出力端子（以下バンプと呼ぶ）は単一バンプのた
め、熱圧着（以下ボンデイングと呼ぶ）によるリ
ード線圧着後、バンプ形状が変化し、リード線の
ボンデイング後は同時に全バンプをプロービング
することが困難であつた。(2) Description of conventional technology Since the wiring input/output terminals (hereinafter referred to as bumps) of conventional integrated circuits (hereinafter referred to as ICs) are single bumps, after lead wire crimping by thermocompression bonding (hereinafter referred to as bonding), The shape of the bumps changed and it was difficult to probe all the bumps at the same time after bonding the lead wires.

(3) 発明の目的の説明 本発明の目的は、リード線ボンデイング用と、
プロービング用とのバンプを別個に設けることに
より前記の欠点を除去したバンプ方式を提供する
ことにある。(3) Description of the purpose of the invention The purpose of the present invention is to provide lead wire bonding;
The object of the present invention is to provide a bump system that eliminates the above-mentioned drawbacks by separately providing bumps for probing and bumps.

(4) 発明の構成 すなわち、本発明は、ICのバンプ構造におい
て、電気的、物理的に接続されている２つ以上の
バンプをIC上の内外に設け、外側のバンプを熱
圧着（ボンデイング）用として、他のバンプを再
プロービング、再配線用としたことを特徴とす
る。(4) Structure of the Invention In other words, the present invention provides an IC bump structure in which two or more bumps that are electrically and physically connected are provided on the inside and outside of the IC, and the outer bumps are bonded by thermocompression (bonding). The other bumps are used for reprobing and rewiring.

(5) この発明の実施例の説明 次に本発明の実施例について図面を参照して詳
細に説明する。図において、IC１は基板５に固
定されており、IC１の上面には入出力信号及び
電源等外部引出しのためのバンプ２ａ，２ｂを設
け、一方のバンプ２ａをIC１の外縁に、他方の
バンプ２ｂを内側に形成する。バンプ２ａと２ｂ
とはIC１を製造する段階で同一物質の配線２ｃ
で物理的に接続されている。バンプ２ａはリード
線３により外部端子４に接続されるものである。
すなわち、バンプ２ａと外部端子４とはリード線
３ａ，３ｂの位置をボンデイングすることにより
接続される。このとき、ボンデイングされるリー
ド線３ａとバンプ２ａとはボンデイングにより沈
み込む。この沈み込み量６とボンデイング位置と
の関係は各々の端子により異なるため、全バンプ
を同時にプロービングすることはできないが内側
のバンプ２ｂはバンプが形成されたままの状態
（無傷、同一高さの状態）であることから、何ら
の影響を受けることなくプロービングあるいは他
の外部配線に再配線が可能となる。(5) Description of embodiments of the present invention Next, embodiments of the present invention will be described in detail with reference to the drawings. In the figure, IC1 is fixed to a substrate 5, and bumps 2a and 2b are provided on the top surface of IC1 for external extraction of input/output signals and power supply, etc. One bump 2a is placed on the outer edge of IC1, and the other bump 2b is provided on the top surface of IC1. is formed inside. Bumps 2a and 2b
is the wiring 2c made of the same material at the stage of manufacturing IC1.
physically connected. The bump 2a is connected to an external terminal 4 via a lead wire 3.
That is, the bump 2a and the external terminal 4 are connected by bonding the positions of the lead wires 3a and 3b. At this time, the lead wire 3a and bump 2a to be bonded sink down due to bonding. Since the relationship between the amount of depression 6 and the bonding position differs depending on each terminal, it is not possible to probe all the bumps at the same time, but the inner bump 2b is in the state where the bump is still formed (in the state where it is intact and at the same height). ), it is possible to perform probing or rewiring to other external wiring without any influence.

(6) 発明の効果の説明 以上のようなバンプ構造にしておくことによ
り、直接IC１を全バンプ同時にプロービングで
きる効果があり、特にIC１を外部回路から切離
し（リード線を切断）した後でもIC１をプロー
ビング、あるいは外部回路に再配線できる利点が
ある。(6) Explanation of the effects of the invention By having the bump structure as described above, it is possible to directly probe all the bumps of IC1 at the same time, and in particular, it is possible to probe IC1 directly even after disconnecting IC1 from the external circuit (cutting the lead wire). It has the advantage of being able to be probed or rewired to external circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の一実施例を示す半導体集積回路の
断面図である。 １……IC、２ａ，２ｂ……バンプ、３……リ
ード線、３ａ，３ｂ……ボンデイング位置、４…
…外部端子、５……基板。 The figure is a sectional view of a semiconductor integrated circuit showing an embodiment of the present invention. 1...IC, 2a, 2b...bump, 3...lead wire, 3a, 3b...bonding position, 4...
...External terminal, 5... Board.

Claims (1)

【特許請求の範囲】[Claims] １ 集積回路の配線用入出力端子、電源端子の構
造において、電気的物理的に接続された２つ以上
の端子を集積回路上の内外に設け、外側の端子を
熱圧着用とし、他の内側の端子を再プロービン
グ、再配線用としたことを特徴とする集積回路の
端子構造。1. In the structure of integrated circuit wiring input/output terminals and power supply terminals, two or more electrically and physically connected terminals are provided inside and outside the integrated circuit, the outer terminal is for thermocompression, and the other inner An integrated circuit terminal structure characterized in that the terminals are used for reprobing and rewiring.
JP58060536A 1983-04-06 1983-04-06 Terminal structure of integrated circuit Granted JPS59186347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58060536A JPS59186347A (en) 1983-04-06 1983-04-06 Terminal structure of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58060536A JPS59186347A (en) 1983-04-06 1983-04-06 Terminal structure of integrated circuit

Publications (2)

Publication Number Publication Date
JPS59186347A JPS59186347A (en) 1984-10-23
JPS643058B2 true JPS643058B2 (en) 1989-01-19

Family

ID=13145118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58060536A Granted JPS59186347A (en) 1983-04-06 1983-04-06 Terminal structure of integrated circuit

Country Status (1)

Country Link
JP (1) JPS59186347A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57133651A (en) * 1981-02-12 1982-08-18 Nec Corp Semiconductor integrated circuit device

Also Published As

Publication number Publication date
JPS59186347A (en) 1984-10-23

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