JPS644163B2 - - Google Patents
Info
- Publication number
- JPS644163B2 JPS644163B2 JP54148108A JP14810879A JPS644163B2 JP S644163 B2 JPS644163 B2 JP S644163B2 JP 54148108 A JP54148108 A JP 54148108A JP 14810879 A JP14810879 A JP 14810879A JP S644163 B2 JPS644163 B2 JP S644163B2
- Authority
- JP
- Japan
- Prior art keywords
- liquid crystal
- data
- phototransistor
- electrode
- high resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004973 liquid crystal related substance Substances 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 description 9
- 239000010408 film Substances 0.000 description 8
- 210000004027 cell Anatomy 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 210000002858 crystal cell Anatomy 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
Landscapes
- Physics & Mathematics (AREA)
- Liquid Crystal (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal Display Device Control (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【発明の詳細な説明】
本発明は半導体基板あるいはガラス、石英等の
絶縁物基板上に構成した半導体装置を一方電極と
する液晶パネルに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a liquid crystal panel in which one electrode is a semiconductor device formed on a semiconductor substrate or an insulating substrate such as glass or quartz.
従来液晶パネル等を用いた表示装置においては
パネルの大型化、表示内容の複雑さが要求されて
いる。例えばインテリジエントターミナルをポー
タブル化するためには、その表示装置として小型
薄型で低消費電力の少なくとも文字が40文字×８
行程度を表示できることが必要である。液晶は小
型薄型、低消費電力ではあるがダイナミツクドラ
イブには余り容易でなく従つて多くの文字数を表
示するのは困難である。そこで、液晶で表示でき
る文字数を増加させる一手段として液晶の電極の
一方を半導体基板を用いて、そこに記憶回路を設
け、その記憶回路に表示データを記憶させること
によりスタテイツク駆動に近い方式がある。第１
図はこの方式による表示１ドツトのセルを示す。
セル１はトランジスタ２とキヤパシタ３により構
成され、表示されるデータがデータ線Ｄに入力さ
れ次にアドレス線ADRが選択され、トランジス
タ２がONすることによりデータ線Ｄのデータが
キヤパシタ３にたくわえられる。このキヤパシタ
３の電極部は液晶の駆動電極を兼ねており、もう
一方の電極にはVCが印加されて、この両電極に
はさまれた液晶トツドセル４を駆動することにな
る。この方式では各ドツトセルがスタテイツクに
近い駆動方式となるため、文字数は半導体基板の
許容する大きさまでいくらでも増加可能である
が、この方式の欠点としてキヤパシタ３に蓄えた
電荷がトランジスタ２のリーク電流や、液晶その
もののリークにより放電してゆくので常にリフレ
ツシユを要することである。このリフレツシユサ
イクルは温度がやや高くなると１ｍsec以内にし
ないと表示がおかしくなる。このため、リフレツ
シユ周波数をあげると低電力性が失なわれる。又
このリークの大小のバラツキが半導体基板の出来
に左右されてひどい場合は、不良ドツトとなり歩
留りを低下させる。特にキヤラクタデイスプレイ
においては同一表示データを長期間続ける場合が
多く、従つてデータの書換えは割合は少ないの
で、リフレツシユ動作は無駄なことである。 2. Description of the Related Art Conventional display devices using liquid crystal panels and the like are required to have larger panels and more complex display contents. For example, in order to make an intelligent terminal portable, the display device must be small, thin, low power consumption, and have at least 40 characters x 8 characters.
It is necessary to be able to display lines. Although liquid crystals are small and thin and have low power consumption, they are not easily compatible with dynamic drives, and therefore it is difficult to display a large number of characters. Therefore, one way to increase the number of characters that can be displayed on a liquid crystal is to use a semiconductor substrate for one of the electrodes of the liquid crystal, provide a memory circuit there, and store display data in the memory circuit, which is a method similar to static drive. . 1st
The figure shows a one-dot cell displayed using this method.
Cell 1 is composed of transistor 2 and capacitor 3. Data to be displayed is input to data line D, then address line ADR is selected, and when transistor 2 is turned on, data on data line D is stored in capacitor 3. . The electrode portion of this capacitor 3 also serves as a driving electrode for the liquid crystal, and VC is applied to the other electrode to drive the liquid crystal toad cell 4 sandwiched between these two electrodes. In this method, each dot cell is driven in a nearly static manner, so the number of characters can be increased as much as the semiconductor substrate allows. Since the liquid crystal itself discharges due to leakage, it requires constant refreshing. When the temperature becomes a little high, this refresh cycle must be kept within 1 msec or the display will become strange. Therefore, when the refresh frequency is increased, the low power property is lost. Furthermore, if the variation in the size of this leak is severe because it is affected by the quality of the semiconductor substrate, defective dots may be formed and the yield will be reduced. Particularly in character displays, the same display data is often continued for a long period of time, and therefore the data is rarely rewritten, so the refresh operation is wasteful.
従つて本発明の目的はこのリフレツシユ動作を
排除して、消費電力を低下させると共に、リーク
の多少があつてパネルの歩留りを低下させない方
式を提案することにある。 Therefore, an object of the present invention is to propose a system that eliminates this refresh operation to reduce power consumption and does not reduce the yield of panels due to some leakage.
第２図が本発明の原理を示す。光感応素子より
なる検出回路１０を備えた駆動セル７の出力５は
液晶体６の一電極８になつておりもう一方の電極
９は共通電圧VCが印加されている。もし液晶が
点灯していると光は遮断されて出力５は液晶が点
灯されるレベルとなり従つて正帰還がかかつて液
晶は点灯されたままとなる。又液晶が非点灯であ
れは出力５はやはり非点灯レベルとなり、この状
態をずつと維持する、いわばスタテイツクメモリ
ーとなつている。 FIG. 2 illustrates the principle of the invention. The output 5 of the drive cell 7 equipped with the detection circuit 10 made of a photosensitive element serves as one electrode 8 of the liquid crystal 6, and the other electrode 9 is applied with a common voltage VC. If the liquid crystal is lit, the light is cut off and the output 5 becomes the level at which the liquid crystal is lit, so that positive feedback occurs and the liquid crystal remains lit. Furthermore, if the liquid crystal is not lit, the output 5 is still at the non-lit level, and this state is maintained gradually, serving as a so-called static memory.
第３図は第２図の具体例を示している。フオト
トランジスタ１１は液晶セル１２の点灯、非点灯
を検出する。もしVCがＬレベルとすると液晶セ
ルが点灯の時フオトトランジスタ１１は光が遮断
されているのでOFFとなり出力１４はVD即ちＨ
レベルとなり液晶１２を点灯させる。従つて一度
点灯するとこの状態を永久に保持することにな
る。又非点灯の時は光がフオトトランジスタ１１
に入射し、ONさせ出力１４をＬレベルとして非
点灯状態をやはり保持する。 FIG. 3 shows a specific example of FIG. The phototransistor 11 detects whether the liquid crystal cell 12 is lit or not. If VC is at the L level, when the liquid crystal cell is lit, the phototransistor 11 will be OFF because the light is blocked, and the output 14 will be VD, that is, H.
The level is reached and the liquid crystal 12 lights up. Therefore, once the light is turned on, this state will be maintained forever. Also, when the light is not lit, the light is transmitted through the phototransistor 11.
The light enters the lamp, turns it on, sets the output 14 to L level, and maintains the non-lighting state.
第４図は第１図に示す書込回路と第３図の保持
回路を同一化した回路例である。アドレス線によ
り選択されたセルの内容がデータ線Ｄのデータに
従つてトランジスタ１５を介して保持回路に書込
まれる。保持回路はフオトトランジスタ１７、抵
抗１６、液晶セル１８からなる。アドレス線
ADRに抵抗１６の一端が接続される。アドレス
線ADRは通常は一定電位となつており電源の役
目を果たす。書き込む時はキヤパシタ２０に瞬間
的にデータが保持されるので、アドレス線のデー
タが変化してもデータはそのままスタテイツクの
保持回路によつてうけつがれる。抵抗１６は非常
に高抵抗であるが、かつフオトトランジスタ１７
の略電流では電圧降下を起こさない程度には小さ
い。この時約100MΩ〜1000MΩ位となる。デー
タの書込みはこの方式以外にもレーザでパネルに
直接光書込みする方式もある。この場合は書込み
用トランジスタ１５とデータ線Ｄとアドレス線
ADRは不要である。 FIG. 4 is an example of a circuit in which the write circuit shown in FIG. 1 and the holding circuit shown in FIG. 3 are made the same. The contents of the cell selected by the address line are written into the holding circuit via the transistor 15 in accordance with the data on the data line D. The holding circuit consists of a phototransistor 17, a resistor 16, and a liquid crystal cell 18. address line
One end of a resistor 16 is connected to ADR. The address line ADR is normally at a constant potential and serves as a power source. When writing, data is momentarily held in the capacitor 20, so even if the data on the address line changes, the data is transferred as is to the static holding circuit. The resistor 16 has a very high resistance, and the phototransistor 17
The current is small enough not to cause a voltage drop. At this time, it will be about 100MΩ to 1000MΩ. In addition to this method, there is also a method for writing data directly onto the panel using a laser. In this case, write transistor 15, data line D and address line
ADR is not required.
第５図は本発明の応用例としてはバルクSi基板
を用いたパネル断面図である。Si基板２５にトラ
ンジスタのソースドレイン用のＰ拡散２９，３
０、及びエミツタフオロワトランジスタのベース
域のＰ拡散３１を行ない、その後エミツタ３２を
形成する。その後フイールド酸化膜３５とチヤネ
ルを形成するためのゲート絶縁膜３３を形成しそ
の上に多結晶シリコン層３７をデポジツトし、高
抵抗を形成する部分３８を除いてP+、及びN+拡
散を施こす。この後SiO2層３４をデポジツトし
コンタクトホール３９を開孔してAlを蒸着しエ
ツチングしてパネルの下電極となる電極層３６を
形成する。この時開孔部４０はフオトトランジス
タに光を供給するウインドウとなる。この上部に
液晶体２６が配置され、この液晶体の点灯、非点
灯を検出する訳であるが、この開孔部４０の電極
はSiO2層３４を介したエミツタ層３２が等価的
にその役割を果たす。さらに液晶体２６をネサ電
極２７のついたガラス板２８ではさみ、パネルが
完成する。 FIG. 5 is a sectional view of a panel using a bulk Si substrate as an application example of the present invention. P diffusion 29, 3 for the source and drain of the transistor in the Si substrate 25
P diffusion 31 is performed in the base region of the 0 and emitter follower transistors, and then the emitter 32 is formed. Thereafter, a field oxide film 35 and a gate insulating film 33 for forming a channel are formed, a polycrystalline silicon layer 37 is deposited thereon, and P + and N + diffusion is performed except for a portion 38 where high resistance is to be formed. Rub. Thereafter, a SiO 2 layer 34 is deposited, a contact hole 39 is opened, and Al is deposited and etched to form an electrode layer 36 that will become the lower electrode of the panel. At this time, the opening 40 becomes a window that supplies light to the phototransistor. A liquid crystal element 26 is arranged above this, and it detects whether the liquid crystal element is turned on or off.The emitter layer 32 via the SiO 2 layer 34 plays the equivalent role of the electrode of this opening 40. fulfill. Further, the liquid crystal body 26 is sandwiched between glass plates 28 having Nesa electrodes 27, and the panel is completed.
第６図は基板にガラスや石英等の絶縁物上にポ
リシリコン等の半導体薄膜をつけた薄膜トランジ
スタを用いた応用例である。絶縁性基板４２に半
導体膜を形成し、レーザアニール等の処理をした
後に必要部分を残してエツチングする。その後拡
散層を形成する。ソース・ドレインを形成する
P+拡散４３，４４、チヤネルを形成する低濃度
部４５、フオトダイオートを形成するP+部４６、
N+部４７、及び高抵抗を形成する低濃度部４８
ができる。その後半導体膜の表面にゲート膜４９
を形成しゲート電極６７を形成しその後絶縁膜５
０を全体にデポジツトする。その後コンタクトホ
ール６５，６６をあけて、Al蒸着、エツチング
して下方電極６０ができる。その後ネサ膜６２を
上方電極として蒸着したガラス６３により液晶６
１をサンドイツチしてできあがる。この時光の入
射は逆バイアスされたダイオードの接合上に行な
われ、光が入射されると電子正孔ペアが生じ見か
け上ダイオードが導通することにより液晶の点灯
−非点灯を検出することになる。 FIG. 6 shows an application example using a thin film transistor in which a semiconductor thin film such as polysilicon is formed on an insulating material such as glass or quartz as a substrate. A semiconductor film is formed on the insulating substrate 42, and after processing such as laser annealing, it is etched leaving only the necessary portions. After that, a diffusion layer is formed. Form source and drain
P + diffusions 43 and 44, a low concentration part 45 forming a channel, a P + part 46 forming a photodiode,
N + part 47 and low concentration part 48 forming high resistance
I can do it. After that, a gate film 49 is formed on the surface of the semiconductor film.
, a gate electrode 67 is formed, and then an insulating film 5 is formed.
Deposit 0 all over. Thereafter, contact holes 65 and 66 are opened, and Al is deposited and etched to form the lower electrode 60. After that, the liquid crystal 6 is made of glass 63 which is vapor-deposited using the Nesa film 62 as an upper electrode.
Sandwich 1 into a sandwich and it's done. At this time, light is incident on the junction of the reverse biased diode, and when the light is incident, electron-hole pairs are generated and the diode is apparently conductive, thereby detecting whether the liquid crystal is on or off.
従来の第１図の構造に基づく320文字のドツト
マトリクスパネルにおいては消費電力は15ｍＷ程
度であつたが、第６図においては１ｍＷにするこ
と可能となつた。 In the conventional dot matrix panel with 320 characters based on the structure shown in FIG. 1, the power consumption was about 15 mW, but in FIG. 6 it has become possible to reduce the power consumption to 1 mW.
上述の如く本発明は、一対の基板上に液晶が封
入され、該一方の基板上に液晶駆動電極、データ
信号を供給するデータ線、タイミング信号を供給
するアドレス線が配列されてなる液晶表示装置に
おいて、該基板上には、該データ線からのデータ
信号を該液晶駆動電極に供給するスイツチングト
ランジスタ、該基板に入射する光を検知するフオ
トトランジスタ及び高抵抗が形成され、該フオト
トランジスタの一端及び該高抵抗の一端は該スイ
ツチングトランジスタのドレインに接続され、該
高抵抗の他端はアドレス線に接続され、該フオト
トランジスタと該高抵抗とによりデータ保持回路
が形成されたから、データの書き換えのない限り
リフレツシユする必要はないので、消費電力を大
幅に低減することができる。又、スイツチングト
ランジスタの構造上若干のリークがあつたとして
も駆動電極は常時データ信号を保持することがで
きるので、パネルの歩留りを向上することができ
る。 As described above, the present invention provides a liquid crystal display device in which liquid crystal is sealed on a pair of substrates, and liquid crystal drive electrodes, data lines for supplying data signals, and address lines for supplying timing signals are arranged on one of the substrates. A switching transistor for supplying a data signal from the data line to the liquid crystal driving electrode, a phototransistor for detecting light incident on the substrate, and a high resistor are formed on the substrate, and one end of the phototransistor is formed on the substrate. One end of the high resistance is connected to the drain of the switching transistor, and the other end of the high resistance is connected to the address line. Since a data holding circuit is formed by the phototransistor and the high resistance, data cannot be rewritten. Since there is no need to refresh unless there is a problem, power consumption can be significantly reduced. Further, even if there is some leakage due to the structure of the switching transistor, the drive electrode can always hold the data signal, so the yield of the panel can be improved.
第１図は従来の半導体基板を用いた液晶パネル
のドツトセルの回路、第２図は本発明の原理図、
第３図、第４図は本発明の回路例、第５図、第６
図は本発明の構造例。
４，１２，１８……液晶セル、１１，１７……
フオト・トランジスタ、１０……光検出回路、２
６，６１……液晶体、３３……ゲート、３８，４
８……高抵抗部分、３４……絶縁膜、３６，６０
……Al、４５……チヤネル部、２７，６２……
上方電極、２８，６３……ガラス、４２……絶縁
性基板。
Figure 1 shows the circuit of a dot cell of a liquid crystal panel using a conventional semiconductor substrate, and Figure 2 shows the principle of the present invention.
Figures 3 and 4 are circuit examples of the present invention, Figures 5 and 6 are examples of circuits according to the present invention.
The figure shows a structural example of the present invention. 4,12,18...Liquid crystal cell, 11,17...
Photo transistor, 10...Photo detection circuit, 2
6,61...Liquid crystal, 33...Gate, 38,4
8... High resistance part, 34... Insulating film, 36, 60
...Al, 45...Channel section, 27,62...
Upper electrode, 28, 63...Glass, 42...Insulating substrate.
Claims (1)
板上に液晶駆動電極、データ信号を供給するデー
タ線、タイミング信号を供給するアドレス線が配
列されてなる液晶パネルにおいて、該基板上に
は、該データ線からのデータ信号を該液晶駆動電
極に供給するスイツチングトランジスタ、該基板
に入射する光を検知するフオトトランジスタ及び
高抵抗が形成され、該フオトトランジスタの一端
及び該高抵抗の一端は該スイツチングトランジス
タのドレインに接続され、該高抵抗の他端はアド
レス線に接続され、該フオトトランジスタと該高
抵抗とによりデータ保持回路が形成されてなるこ
とを特徴とする液晶パネル。1. In a liquid crystal panel in which liquid crystal is sealed on a pair of substrates, and liquid crystal drive electrodes, data lines for supplying data signals, and address lines for supplying timing signals are arranged on one of the substrates, , a switching transistor that supplies a data signal from the data line to the liquid crystal drive electrode, a phototransistor that detects light incident on the substrate, and a high resistor, one end of the phototransistor and one end of the high resistor are formed. A liquid crystal panel characterized in that the phototransistor is connected to the drain of the switching transistor, the other end of the high resistance is connected to an address line, and a data holding circuit is formed by the phototransistor and the high resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14810879A JPS5670530A (en) | 1979-11-15 | 1979-11-15 | Liquid crystal panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14810879A JPS5670530A (en) | 1979-11-15 | 1979-11-15 | Liquid crystal panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5670530A JPS5670530A (en) | 1981-06-12 |
| JPS644163B2 true JPS644163B2 (en) | 1989-01-24 |
Family
ID=15445421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14810879A Granted JPS5670530A (en) | 1979-11-15 | 1979-11-15 | Liquid crystal panel |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5670530A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59158553A (en) * | 1983-02-28 | 1984-09-08 | Toshiba Corp | Optical solid device |
| US4917474A (en) * | 1984-09-10 | 1990-04-17 | Semiconductor Energy Laboratory Co., Ltd. | Optoelectronic panel and method of making the same |
| JPS6283728A (en) * | 1985-10-09 | 1987-04-17 | Hitachi Ltd | Time-division drive optical switch array |
| US5051570A (en) * | 1989-01-20 | 1991-09-24 | Nec Corporation | Liquid crystal light valve showing an improved display contrast |
-
1979
- 1979-11-15 JP JP14810879A patent/JPS5670530A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5670530A (en) | 1981-06-12 |
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