JPS644202B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to digitalization of a servo system used in the rotary head of a magnetic recording/reproducing device (VTR), and is particularly applicable to a VTR with a relatively simple servo system such as for home use. The present invention provides a digital servo device that has a small number of elements and is suitable for integration into an integrated circuit (IC).

A conventional VTR servo system is an analog type, and FIG. 1 shows an example of its configuration, and FIG. 2 shows an example of its operating waveforms.

In FIGS. 1 and 2, 1 is a rotating disk that is directly connected or connected to a controlled rotating body (cylinder, capstan, etc.), 2 and 3 are first and second markers, and 4 is a circle of the markers 2 and 3. Waveform A in FIG. 2 shows both positive and negative pulse signals _S1 as an example of a detection signal from a rotation detection device consisting of detection heads 1 to 4, which are provided oppositely on the circumferential surface. 5 is the pulse signal S ₁
6 is a flip-flop (waveform B) that converts the output of the amplifier circuit 5 into a square wave signal _S2 , and 7 is a trapezoid for speed comparison. A first trapezoidal wave generating circuit (waveform C) forms the wave signal _S3 , and 8 is a speed reference forming circuit (waveform D) forming the speed reference signal _S4 of the rotating body 1, and the time serving as the speed reference is A monostable multivibrator is usually used to form the width τ _s . Reference numeral 9 denotes a first pulse generation circuit that forms pulses for sampling the trapezoidal wave signal _S3 in the first sample and hold circuit 10 at the next stage. The output S ₆ of the first sample and hold circuit 10 is a DC voltage e _s proportional to the speed error, and this is passed through the drive amplifier circuit 11 to the DC motor 1 for driving the rotating body.
2, and controls the rotational speed of the rotating body 1 to match the reference speed.

Note that the VTR servo system further needs to synchronize the rotational phase of the rotating body with an external reference signal (for example, a vertical synchronization signal in a video signal), and is equipped with a phase control system. 13 is an external reference signal input terminal;
Waveform G indicates an external reference signal _S7 , which is input to the second trapezoidal wave generating circuit 14 to generate a trapezoidal wave signal _S8 for phase comparison.
(Waveform H). On the other hand, a sampling pulse _S9 is formed by the rise (or fall) of the square wave signal _S2 through the second pulse generation circuit 15, and the trapezoidal wave signal _S8 is sampled and held in the second sample hold circuit 16 at the next stage. As a result, an output _S10 , which is a DC voltage e _p proportional to the phase error, is obtained. The output S ₁₀
is passed through the gain adjuster 17 to the reference generation circuit 8.
Construct a negative feedback loop to control.

In the conventional VTR servo system shown above, all control information is handled as analog quantities, so it is susceptible to operating point fluctuations and gain fluctuations due to fluctuations in power supply voltage and temperature, and unnecessary signal superposition due to incomplete sample and hold. This has hindered high reliability and miniaturization, such as the need for large-capacity capacitors, which can easily cause disturbances in control due to the noise, and the need for external components cannot be completely eliminated even when integrated circuits are used. Furthermore, even in the case of large-scale integration (LSI), simply replacing conventional servo circuits with digital circuits cannot be expected to reduce power consumption or reduce IC chip area in consideration of yield.

Now, when digitizing the servo circuit illustrated in FIG.
are configured with respective counters and gate circuits, the speed reference generation circuit 8 is configured with a counter and a gate circuit for setting numbers for speed modulation, the first and second sample and hold circuits 10 and 16 are each configured with registers, and the first The output of the sample-and-hold circuit 10 is used to drive and control the rotating body as required, through a DA converter when controlling a DC motor, or through a digital frequency modulator using a counter when controlling a synchronous motor. There is a need to. That is, if the configuration illustrated in FIG. 1 is replaced as is with a digital circuit, a plurality of counters will be required, resulting in a large number of constituent elements, which is not suitable for IC implementation.

In order to solve this type of conventional problem, the present invention not only replaces the servo circuit with a digital circuit, but also simplifies the configuration, reduces the number of elements, and creates a digital circuit that is highly reliable and suitable for IC implementation. The present invention provides a servo device.

The present invention provides a servo system having at least a speed control system (velocity system) and a phase control system (phase system), which conventionally required multiple counters, but is configured with a single counter that can be shared by multiple control systems. It is characterized by:

That is, the present invention provides a digital servo system for a rotary body having at least a speed control system and a phase control system, which includes a single binary counter that counts clock pulses as input, and first and second counters that take out the counting output of the binary counter. A digital error output of the speed control system is obtained by the count output stored in the first register, a digital error output of the phase control system is obtained by the count output stored in the second register, and a digital error output of the phase control system is obtained by the count output stored in the second register. This is a digital servo system for a rotating body configured to control the rotating body using error output.

The present invention will be explained below based on the drawings.

3 is a block diagram showing the basic configuration of the present invention, FIG. 4 is an example of the circuit configuration of the main part in FIG. 3, FIG. 5 is a waveform diagram of each part in FIGS. 3 and 4, and FIG. FIG. 8 is an example of a rotational pulse processing circuit, and FIGS. 7 and 9 are waveform diagrams of each part thereof.

In FIG. 3, 101 is a clock signal input terminal, 102 is a rotation pulse signal input terminal, 103 is an external reference signal input terminal, 104 is a digital error output terminal, 105 is a clock gate circuit, and 106 is a clock signal input terminal.
is a binary counter, 107 is a rotation pulse processing circuit,
108 and 109 are first and second gate circuits, 11
0 and 111 are first and second registers, and 112 is an adder. The input clock signal S _a from the terminal 101 is input to the binary counter 106 through the clock gate circuit 105.
6 can be counted. On the other hand, a rotational pulse signal S _b (corresponding to S ₁ in FIG. 2) is inputted to the terminal 102 and separated into negative and positive pulses through the rotational pulse processing circuit 107, and the first and second rotational pulses S _b1 , Make it S _b2 . The second rotation pulse S _b2 is sent to the first register 11
Used as a zero sampling pulse. The binary counter 106 starts counting in synchronization with the application of the first rotation pulse S _b1 , and when the counter 106 finishes counting a predetermined count value, the clock gate signal S _c from the first gate circuit 108 causes the clock gate circuit to start counting. 105 is controlled to close. This clock gate circuit 105 can also be used by directly controlling the JK input terminal of the JK flip-flop constituting the counter 106 with the clock gate signal _Sc . In this case, the clock gate circuit 105 can be removed and the clock signal S _a can be continuously input to the counter 106. The counting output of the counter 106 is obtained as a digital error output (binarized error output) for the velocity system and the phase system through separate gate circuits 108 and 109 and separate registers 110 and 111, and an adder 112 converts the error between the two. The digital error output obtained by adding (or subtracting) the outputs is connected to terminal 10.
Configure it to get 4. Here is the gate circuit 10
Reference numeral 8,109 consists of a saturation characteristic imparting gate for establishing one stable point of the speed system and the phase system, and a gate controlled by the gate output and passing the count output of the counter 106. Also, the register 111 has terminal 1.
03, the external reference signal S _f is input as a sampling pulse.

With the above configuration, the necessary counters can be shared between the velocity system and the phase system, and a single counter is sufficient, thereby simplifying the configuration.

FIG. 4 shows an example of the circuit configuration of the main part of the present invention, and the same numbers and symbols correspond to those in FIG. 3.

107a is the first input terminal of the rotation pulse processing circuit 107, and the first rotation pulse S _b1 counter 10
6 as a reset signal. Although a 6-bit synchronous counter is shown as an example of the counter 106, it may also be an asynchronous counter.
In this case, the gates G ₁ to _{G 4} required for the synchronous type can be removed.

The first gate circuit 108 is composed of an AND gate consisting of G ₅ to _{G 8} , a NOR gate consisting of G ₉ to G ₁₂ , and an AND gate G ₁₃ for providing saturation characteristics, and the counting output of the counter 106 is sent to the first register 110. I am trying to communicate this to If I explain its operation now,
S _d1 and S _d2 are gate signals imparting saturation characteristics _;
When S _d2 are both "L", the gate output unconditionally outputs "H", and when S _d1 is "H" and S _d2 is "L", the output of the counter 106 is passed, and S _d2 becomes "H". At this time, the gate output outputs "L" unconditionally. This makes it possible to impart saturation characteristics, and since it operates in synchronization with the first rotation pulse S _b1 , it is possible to determine one stable point in the speed system. Next, the second gate circuit 109 is an OR gate consisting of _G14 to _G17 .
It is composed of AND gates G ₁₈ to _{G 21} and saturation characteristic imparting gates G ₂₂ to _{G 24} , and transmits the count output of the counter 106 to the second register 111 . In operation, when the output S _e of gate G ₂₃ is "L" and the output S _c of gate G ₂₄ is "H", the counter 10
Through the output of 6, when S _e and S _c are both "H", "H" is output unconditionally, and when S _c is "L", "L" is output unconditionally, By imparting saturation characteristics, the stable point of the phase system is determined to be one.

That is, the above-mentioned signals Sd ₁ , Sd ₂ , Sc, Se are
It is formed by the output of the upper bits e and f of the binary counter 106, and the first and second gates 108,
At 109, the outputs of the lower bits a to d of the binary counter 106 are outputted according to the output values of the upper bits e and f, respectively.

In addition, in FIG. 4, the first and second gates 108, 1
Both 09 have 4 lower bits and 2 upper bits.
Although the configuration is made up of bits, the number of these bits can be easily changed. It goes without saying that the total number of bits in the binary counter 106 is not limited to 6 bits.

In FIG. 5, waveform A is the first rotational pulse S _b1 ,
B is the clock gate circuit 1 of the clock signal S _a
The clock signals S' _a and C that have passed through 05 are the Q outputs of the least significant bit a of the counter 106, D to G are the Q outputs of bits b to e of the counter 106, respectively, and H is the Q output of the most significant bit f. , H and I are the speed system saturation characteristic gate signals S _d1 , S _d2 , J is the waveform when the output of the first gate circuit 108 is DA converted,
K is a clock gate signal S _c , K and L are phase-based saturation characteristic gate signals S _c , S _e , and M are waveforms obtained when the output of the second gate circuit 109 is DA converted. N and are the second rotation pulse S _b2 and the external reference signal S _f , which respectively sample and hold the slope portions of the waveforms J and M when the speed system and the phase system are in normal operation.

Next, a configuration example of the rotational pulse processing circuit 107 shown in FIG. 3 will be explained with reference to FIGS. 6 to 9. Note that the numbers and symbols are shown in correspondence with those in FIG.

Figure 6 shows an example of detecting and using two pulses (in the example shown, one signal with positive and negative pulses) that can determine the position of the rotating body per revolution, and Figure 8 shows one pulse per revolution. An example is shown in which three pulses are detected and used, and FIGS. 7 and 9 are waveform diagrams of each part.

In FIG. 6, the input rotational pulse signal S _b from the terminal 102 is separated and amplified into a positive pulse and a negative pulse by an amplifier 107c, and each output pulse is
Format S′ _b1 and S′ _b2 . Since the output pulses S' _b1 and S' _b2 are wide pulses whose pulse widths are approximately equal to the pulse width of the input rotational pulse signal S _b , they need to be shaped into narrow pulses. First, “OR gate”
G ₂₆ to obtain the composite output S' _b1 + S' _b2 , and the composite output
S' _b1 + S' _b2 to JK flip-flop 107d, 10
7e is used as a reset signal for a binary counter, which counts the input clock signal S _a from the terminal 101 by a predetermined number of 2, and produces a composite output S' _b1
An output pulse S _g with a pulse width equal to the period of the clock signal S _a synchronized with +S' _b2 is generated. The output pulse S _g
In order to separate the pulses S' b1 and S' b2 into the first and second rotational pulses S _b1 and S _b2 , the gates G ₂₇ and G ₂₈ separate the pulses S' _b1 and S' _b2
Take MAND and AND with respectively, and connect terminal 107.
a, 107b. If a narrower pulse is required, the clock signal S _a is input to gates G ₂₇ and G ₂₈ at the same time, but the clock signal S _a
It is also possible to use another clock signal with a higher frequency than that, or to create it through a differentiating circuit. Note that this does not apply to the case where the output pulses S' _b1 and S' _b2 can be used as they are.

In FIG. 7, waveform A is rotation pulse signal S _b , B
and C are the output pulses S' _b1 , S' _b2 of the amplifier 107c,
D and E are the first and second rotation pulses S _b1 and S _b2 ,
F to I are partially enlarged views, F is the clock signal S _a ,
G is the composite output S' _b1 + S' _b2 , H and I are 107d,1
07e are each Q output of the counter.

In FIG. 8, an input rotational pulse signal S _b from a terminal 102 is amplified by an amplifier 107c and shaped into an output pulse S' _b . In order to shape the output _pulse into a narrow pulse as shown in _FIG . is counted by a predetermined number of 4, thereby producing first and second rotational pulses S _b1 and S _b2 having a pulse width equal to the period of the clock signal S _a synchronized with the output pulse S' _b . terminal 107
At the terminal a, the output of the JK flip-flop 107h is obtained as the first rotation pulse S _b1 , and at the terminal 107b, the Q output of 107f is obtained as the second rotation pulse S _b2 . Here, the first rotation pulse S _b1 is a pulse slightly delayed compared to the second rotation pulse S _b2 , and after sampling with the second rotation pulse S _b2 , the first rotation pulse
The counter 106 is configured to be reset at S _b1 . Note that _G28 is a gate for stopping the counter consisting of 107f to 107i after a predetermined count of 4.

In Fig. 9, waveform A is rotation pulse signal S _b , B
is the output pulse S' _b of the amplifier 107c, C and D are the second and first rotating pulses S _b2 and S _b1 , E to J are partially enlarged views, E is the clock signal S _a , and F is the output pulse S ' _b , G to J are the Q outputs of the counters 107f to 107i.

Single counter 106 for speed system and phase system
Although the present invention has been described in which the first gate circuit 108 of the speed system is shared, at least a portion of the first gate circuit 108 of the speed system may be shared and used for the phase system for further simplification. However, in this case, the speed reference time τ _s (corresponding to the "L" period of waveform H in FIG. 5 and the conventional waveform D in FIG. 2) required for the speed system becomes a dead time element of the phase system. In addition, in the above explanation, an example was explained in which one or two pulses are used for one rotation of the rotating body, but this applies when the frequency of the external reference signal S _f of the phase system is equal to the rotational frequency of the rotating body. If the frequency of the external reference signal S _f is n times higher than the rotational frequency of the rotating body, it is necessary to increase the number of pulses per revolution by n times. In addition,
This does not apply if it is acceptable to divide S _f into an appropriate frequency, but the sampling frequencies of the velocity system and the phase system must be equal.

By controlling the rotating body driving motor using the digital error output obtained at the output terminal 104 with the above configuration, a digital servo system can be constructed. If a synchronous motor is used as the drive motor, it is necessary to further control a digital frequency converter using the digital error output, and control the modulator output by passing it through the drive circuit; if a DC motor is used, is the digital error output
It must be connected to a DA converter, converted to analog output, and then controlled through a drive amplifier circuit. In addition,
When using a DC motor, the adder 112 may be removed, the outputs of the first and second registers 110 and 111 may be subjected to DA conversion, and the added or subtracted outputs may be used. Also, since servo systems generally require a compensation filter, instead of using a digital filter that requires a complicated circuit configuration, an analog filter configured using L, C, and R elements after DA conversion may be used. . In this case, in order to control the synchronous motor, it is necessary to perform AD conversion again for this purpose. However, this does not apply when using a digital filter.

As described above, in the present invention, the control information in the conventional servo system, which is completely handled as an analog quantity, is treated as a binary digital quantity. signal (e.g. color subcarrier signal 3.58MHz
Since it is possible to use the servo system (such as the servo system), it is possible to eliminate drift, and the sample and hold is perfect, so there is no need to worry about superimposing unnecessary signals, and a stable servo system can be constructed. In addition, since it is possible to configure a servo system using a single counter that has the characteristics of a digital circuit, it is possible to reduce costs by reducing the number of elements, improve reliability, and reduce the size of the chip when converting it into an IC. Therefore, it has features that can eliminate conventional problems, such as improved yield, lower power consumption, and no need for external parts.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional VTR servo system, Figure 2
The figure is a waveform diagram of each part of Fig. 1, Fig. 3 is a block diagram showing the basic configuration of the present invention, Fig. 4 is an example of the circuit configuration of the main part of Fig. 3, and Fig. 5 is the same as Fig. 3 and Fig. 4. FIGS. 6 and 8 are examples of rotational pulse processing circuits, and FIGS. 7 and 9 are waveform diagrams of various parts thereof. 105... Clock gate circuit, 106... Binary counter, 107... Rotation pulse processing circuit, 108...
First gate circuit, 109...Second gate circuit, 11
0...First register, 111...Second register, 11
2... Adder.

Claims (1)

[Claims] 1. A rotation pulse processing means that forms first and second rotation pulses from rotation pulse signals obtained by detecting the rotation of a rotating body, and a single binary counter that counts clock pulses in synchronization with the first rotation pulse. a clock gate means for stopping the counting operation of the binary counter when the binary counter reaches a predetermined count value; and a first saturation characteristic imparting gate signal comprising at least one upper bit output of the binary counter. and a second saturation characteristic imparted gate signal obtained by performing a logical operation on the first saturation characteristic imparted gate signal and the lower bit output of the binary counter, and these first and second saturation characteristic imparted gate signals are obtained. a first gate means for gate-outputting a lower bit output immediately before reaching a predetermined count value of the binary counter in synchronization with the first rotation pulse based on the first rotation pulse, and having a saturation characteristic; a second gate means for extracting a lower bit output with saturation characteristics based on a predetermined upper bit count value within a counting period; and a second gate means for storing the output of the first gate means by the second rotation pulse. 1 register, and a second register that stores the output of the second gate means using an external reference signal;
A digital device for a rotating body, comprising an adder for adding or subtracting the output of the first register and the output of the second register, and controlling the rotating body based on the output of the adder. Servo device.