JPS644351B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a bipolar semiconductor integrated circuit device.

Reducing the element area in the manufacture of semiconductor integrated circuit devices not only improves the integration density, but also
Enables high-speed operation by reducing parasitic capacitance.

FIG. 1 shows an example of a method of manufacturing a conventional bipolar semiconductor integrated circuit device, which is currently the most practical method for improving the integration density.

First, as shown in FIG. 1A, an N ⁺ buried layer 2 is formed on a P-type silicon substrate 1, and then an N-type epitaxial layer 3 is formed on the silicon substrate 1.

Next, a thermally grown silicon oxide film 4 and a silicon nitride film 5 are deposited on selected surfaces of the epitaxial layer 3.
A mask layer 6 for selective oxidation is formed. Then, the epitaxial layer 3 without the silicon nitride film 5 on its surface is etched to form a groove 7. Here, the depth of the groove 7 is set so that even if an oxide film with increased volume is formed in the groove portion in the next oxidation step, the substrate surface remains substantially flat.

When the substrate shown in FIG. 1A is oxidized, an isolation oxide film 8 is formed as shown in FIG. 1B, and a mask layer 6 is formed.
Underneath, a collector region 3', 3'' consisting of an epitaxial layer 3 is formed.

Next, as shown in FIG. 1C, after removing the mask layer 6, an N ⁺ region (deep collector region) 9 for reducing collector resistance is formed in the collector region 3'' and bonded to the buried layer 2. Furthermore, a P ⁺ region (side base region) 10 for reducing base resistance is formed in the collector region 3'.

Next, as shown in FIG. 1D, a P-type main base region 11 is formed in the collector region 3'.

Next, as shown in FIG. 1E, openings 12 and 13 for collector and emitter contacts are formed by a well-known etching method, and then an N ⁺ emitter region 14 is formed in the main base region 11.

Then, as shown in FIG. 1F, after forming a contact hole in the base, electrodes 15, 16, and 17 made of wiring metal are formed.

In such a bipolar semiconductor integrated circuit device, the base regions 10 and 11 and the emitter region 14 are reduced in size by creating an opening for making ohmic contact between the side base region 10 and the electrode 15, and by making an ohmic contact between the emitter region 14 and the electrode 16. Silicon oxide film 18 existing between the openings to be contacted
limited by the dimensions of This silicon oxide film 1
8 is determined by the distance b between the electrodes 15 and 16 shown in FIG.
It is determined by the sum of the dimension a extending by the mask alignment error margin for electrode pattern formation, that is, 2a+b.

However, in the conventional method shown in FIG. 1, the extraction electrodes 15 and 16 are formed directly above the side base region 10 and emitter region 14;
It is difficult to reduce the dimensions of the base regions 10, 11 and the emitter region 14, and therefore there is a drawback that there is a limit to the reduction of the areas of the base regions 10, 11 and the emitter region 14.

This invention has been made in view of the above points, and provides a method for manufacturing a semiconductor integrated circuit device that can significantly reduce the base and emitter regions, as well as the entire device, and that enables high integration and high-speed operation. The purpose is to provide.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a diagram showing an embodiment of the present invention.
In this embodiment, the same steps as in the conventional method are followed until the N ⁺ region (deep collector region) is formed. Therefore, explanation up to the step of forming the deep collector region will be omitted, and FIG. 3A shows the state after the step of forming the deep collector region is completed. Third
In Figure A, 21 is a P-type silicon substrate, 22
is an N ⁺ buried layer, 23 is a collector region (first region) made of an N type epitaxial layer, 24 is an element isolation oxide film, and 25 is an N ⁺ deep collector region.

After forming the N ⁺ deep collector region 25, next, a first polycrystalline silicon layer 26 is grown to a thickness of 2000 to 5000 Å on the entire surface of the silicon substrate 21, and then the first polycrystalline silicon layer 26 is grown to a thickness of 2000 to 5000 Å. Mask layers 27 1 and 27 _{2 for selective oxidation are formed on predetermined portions of the first polycrystalline silicon layer 26 on the surface of the first polycrystalline silicon layer 26, that is, on the emitter formation region and the emitter extraction portion, and on the deep collector region 25 .} . These mask layers 27 ₁ , 27 ₂ have a thin silicon oxide film below and a silicon nitride film above.
Consists of layers. (See FIG. 3B) Next, selective oxidation of the first polycrystalline silicon layer 26 is performed using mask layers 27 ₁ and 27 ₂ . When this selective oxidation is performed, the first layer immediately below the mask layers 27 ₁ and 27 ₂
The first polycrystalline silicon layer 26 still remains as polycrystalline silicon layers 26 ₁ and 26 ₂ , but the first polycrystalline silicon layer 26 having no mask layer on its surface becomes a thermally grown silicon oxide film 28 . (See FIG. 3C) Subsequently, after removing the mask layers 27 ₁ and 27 ₂ ,
P-type impurity such as boron is introduced into the polycrystalline silicon layers 26 ₁ and 26 ₂ in an amount of approximately 10 ¹⁴ cm ^-2 by means such as ion implantation. Thereafter, heat treatment is performed to form a P-type main base region (second region) 29 in the collector region 23 directly under the polycrystalline silicon layer 26 ₁ . At this time, boron is also diffused into the deep collector region 25 at the same time, but the deep collector region 25 already has a high concentration.
Since the N ⁺ type impurity is diffused, no P type region is generated. Next, again, the polycrystalline silicon layer 26 ₁ ,
In _26.2 , an N-type impurity such as arsenic is introduced at approximately 10 ¹⁶ cm ^-2 by means such as ion implantation, and a polycrystalline silicon layer is formed by heat treatment at a temperature of about 900°C to 1000°C for a short time. 26 ₁ ,
26 Aim to make N-type impurities such as arsenic uniform in ₂ .
At this time, the N-type impurity is hardly diffused into the main base region 29 because the diffusion rate in single crystal silicon is significantly slower than in polycrystalline silicon. (See FIG. 3D) Next, after removing the entire silicon oxide film 28,
Oxidation treatment is performed at a low temperature of approximately 700℃ or less. As a result, the polycrystalline silicon layer 2 containing high concentration of impurities
Thick silicon oxide films 30 ₁ and 6 ₁ and 26 ₂ have thick silicon oxide films on their surfaces.
_On the other hand, a thin silicon oxide film 31 is grown on the single crystal silicon surface including the collector region 23 surface. (See Figure 3E) Next, the thin silicon oxide film 31 is immersed in a silicon oxide film etching solution.
While removing the thick silicon oxide films 30 ₁ , 3
0 ₂ is left in a state where the film thickness is slightly reduced. Thereafter, a second polycrystalline silicon layer 32 is grown to a thickness of about 2000 to 5000 Å on the entire surface of the silicon substrate 21, that is, on the surfaces of the silicon oxide films 30 ₁ and 30 ₂ , the collector region 23 and the isolation oxide film 24 . (See FIG. 3F) Thereafter, a P-type impurity, such as boron, is introduced into the second polycrystalline silicon layer 32 at a high concentration of about 10 ¹⁵ to ^{10 16} cm ^-2 by means such as ion implantation. After introducing impurities, the second polycrystalline silicon layer 32 is selectively removed.
polycrystalline silicon layer 32, silicon oxide film 30
It is left only in necessary parts such as the surfaces of ₁ and the collector region 23 and a part that becomes a resistor (not shown).
The state after this selective removal is shown in FIG. 3G, where the silicon oxide film 30 ₁
And the second polycrystalline silicon layer 32 left on the surface of the collector region 23 is a polycrystalline silicon layer 32 ₁
It is shown as.

Thereafter, an insulating film 33 such as a silicon oxide film is grown on the entire surface of the silicon substrate 21, such as the surface of the polycrystalline silicon layer 32 ₁ . After forming the insulating film 33, heat treatment is performed to form P ⁺ side base regions (fourth regions) 34 ₁ , ₃₄ extending from the main base region 29 in the collector region 23 directly under the polycrystalline silicon layer 32 1 . Form ₂ . At this time,
At the same time, N-type impurities are diffused from the polycrystalline silicon layer 26 ₁ into the main base region 29 , so that the main base region 2 directly under the polycrystalline silicon layer 26 ₁
An emitter region (third region) 35 is formed at 9 . (See FIG. 3H.) Thereafter, contact holes are opened by conventional means (not shown) and metal wiring is formed, thereby completing the bipolar semiconductor integrated circuit device.

FIG. 4 is a plan view of the main part of the semiconductor integrated circuit device completed in this way, and shows a polycrystalline silicon layer 26 ₁ for forming an emitter contact.
is drawn outside the active device area.

According to the embodiments described above, the following effects can be obtained.

By self-alignment, the spacing between the electrode lead-out portions of the emitter region 35 and the base regions 29, 34 ₁ , 34 ₂ is set to submicron, that is, as shown in FIG. 3H.
The wiring can be reduced to the thickness of _the silicon oxide film 30 ₁ shown in FIG. Emitter area 3 without reducing alignment margin
5 and the base regions 29, 34 ₁ , 34 ₂ , and by extension the entire device, can be miniaturized to the maximum and highly integrated, and furthermore, a polycrystalline silicon resistor with almost no parasitic capacitance can be simultaneously formed, which also increases speed. In addition, lower power consumption can be achieved.

Since the metal wiring can be formed directly above the side base regions 34 ₁ and 34 ₂ , there is no increase in the base series resistance. Furthermore, since the base terminal can be taken out from any point on the polycrystalline silicon layer 32 ₁ , the degree of freedom in designing the integrated circuit increases.

In the conventional method, three masking steps are required to form the main base region, side base region, and emitter region, but according to the embodiment, selective oxidation of the first polycrystalline silicon layer 26 and second masking step are required to form the main base region, side base region, and emitter region. Only two masking steps are required to selectively remove the polycrystalline silicon layer 32, which simplifies the process.

According to the embodiment described using FIGS. 3 and 4, the above effects can be obtained.

In the above embodiment, oxide film isolation was used for element isolation, but it is also possible to use an isolation method such as PN isolation or a combination of PN isolation and oxide film isolation.

Further, a second polycrystalline silicon layer 32 is formed using non-doped polycrystalline silicon, and thereafter, a second polycrystalline silicon layer 32 is formed using non-doped polycrystalline silicon.
However, the second polycrystalline silicon layer 32 is formed using polycrystalline silicon containing a high concentration of P-type impurity, for example, boron. Good too.
Furthermore, the selective removal of the second polycrystalline silicon layer 32 can be replaced by selective oxidation, in which case,
A process of introducing impurities after selective oxidation is desirable.

Further, the formation of the insulating film 33 and the subsequent heat treatment process can be replaced by thermal oxidation treatment.

Further, in the embodiment, the side base regions 34 ₁ ,
Although the emitter region 34 ₂ is arranged in the collector region 23, it is also possible to make the emitter region 35 close to the isolation oxide film 24 and eliminate one of the side base regions 34 ₁ and 34 ₂ . In this way, the surface area of the base emitter region can be further reduced significantly.

Furthermore, by providing a plurality of adjacent polycrystalline silicon layers 26 ₁ , a multi-emitter transistor can be manufactured. When a multi-emitter transistor is manufactured, the side base regions on both sides of all emitter regions are connected to each other by the polycrystalline silicon layer ₃₂₁ at the shortest distance, so the base series resistance is small regardless of the emitter position. There will be almost no difference. In particular, this effect is even more remarkable if the entire surface of the polycrystalline silicon layer 32 ₁ is opened to take out the metal wiring.

As is clear from the above description, in the method for manufacturing a semiconductor integrated circuit device of the present invention, a first polycrystalline silicon substrate is formed on a silicon substrate of an opposite conductivity type, which has a first region of one conductivity type that serves as a collector on the surface. After forming a layer and selectively oxidizing it, a second polycrystalline silicon layer of an opposite conductivity type is formed as a base in the first region through a process of introducing an impurity of an opposite conductivity type into the first polycrystalline silicon layer.
After forming a region and introducing an impurity of one conductivity type into the first polycrystalline silicon layer again, the silicon oxide film formed by the selective oxidation is removed, and then the first polycrystalline silicon layer is removed.
An oxide film is formed on the surface of the polycrystalline silicon layer, and a second polycrystalline silicon layer is formed on the entire surface, and then an impurity of the opposite conductivity type is introduced into the second polycrystalline silicon layer. By heat treatment, a third region of one conductivity type serving as an emitter is formed in the second region, and a fourth region of the opposite conductivity type serving as a side base is simultaneously formed in the first region. Furthermore, instead of introducing impurities into the second polycrystalline silicon layer after forming the second polycrystalline silicon layer, a second polycrystalline silicon layer containing impurities of the opposite conductivity type is formed over the entire surface. Therefore, the base and emitter regions, as well as the entire device, can be significantly reduced, allowing for higher integration, improved characteristics such as high-speed operation, and lower power consumption. Furthermore,
The degree of freedom in design can be increased, and the process can be greatly simplified. The manufacturing method of the present invention having such effects is called ECL,
It can be widely used in manufacturing methods for high-density, high-speed bipolar type semiconductor integrated circuit devices using STTL, IIL, etc., or a mixture thereof.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing an example of a conventional method for manufacturing a bipolar semiconductor integrated circuit device, and FIG. 2 is a cross-sectional view showing a part of the device manufactured by the conventional method.
FIG. 3 is a sectional view showing an embodiment of the method for manufacturing a semiconductor integrated circuit device of the present invention, and FIG. 4 is a plan view showing the main parts of the device obtained by the embodiment. 21... P-type silicon substrate, 23... Collector region, 26... First polycrystalline silicon layer, 26 ₁ ... Polycrystalline silicon layer, 27 ₁ ... Mask layer, 28... Thermally grown silicon oxide film, 29... P-type main base region, 30 ₁ ... thick silicon oxide film, 31... thin silicon oxide film, 32... second polycrystalline silicon layer,
32 ₁ ... polycrystalline silicon layer, 34 ₁ , 34 ₂ ... P ⁺ side base region, 35 ... emitter region.

Claims (1)

[Claims] 1. A step of preparing a silicon substrate of an opposite conductivity type having a first region of one conductivity type serving as a collector on the surface thereof, and a step of forming a first polycrystalline silicon layer on the surface of this silicon substrate. a step of forming a mask layer for selective oxidation on a selected surface of the first polycrystalline silicon layer; and a step of forming a mask layer for selective oxidation on a selected surface of the first polycrystalline silicon layer, which does not have a mask layer on the surface. a step of converting the mask layer into an oxide film; a step of introducing an impurity of an opposite conductivity type into the first polycrystalline silicon layer after removing the mask layer; A step of forming a second region of the opposite conductivity type to serve as a base in the polycrystalline silicon layer, a step of introducing high concentration impurities of one conductivity type into the first polycrystalline silicon layer, and a step of removing the silicon oxide film at a low temperature. forming a thin silicon oxide film and a thick silicon oxide film on the surface of the first region and the first polycrystalline silicon layer by oxidation, and removing the thin silicon oxide film; forming a second polycrystalline silicon layer on the surface and the surface of the thick silicon oxide film; introducing impurities of opposite conductivity type into the surface of the second polycrystalline silicon layer; and heat treating the silicon substrate. Accordingly, a third region of one conductivity type serving as an emitter is placed in the second region directly under the first polycrystalline silicon layer, and a third region of one conductivity type is placed in the first region directly under the second polycrystalline silicon layer. A method for manufacturing a semiconductor integrated circuit device, comprising the step of simultaneously forming a fourth region of an opposite conductivity type that becomes a side base extending from the base. 2. A step of preparing a silicon substrate of an opposite conductivity type having a first region of one conductivity type serving as a collector on the surface, a step of forming a first polycrystalline silicon layer on the surface of this silicon substrate, and a step of forming a first polycrystalline silicon layer on the surface of this silicon substrate. A step of forming a mask layer for selective oxidation on a selected surface of the polycrystalline silicon layer, and a step of converting the first polycrystalline silicon layer, which does not have a mask layer on the surface, into a silicon oxide film by selective oxidation. and, after removing the mask layer, introducing an impurity of a reverse conductivity type into the first polycrystalline silicon layer, and a step of introducing an impurity of a reverse conductivity type into the first region directly under the first polycrystalline silicon layer to become a base. a step of forming a second conductivity type region; a step of introducing a high concentration of one conductivity type impurity into the first polycrystalline silicon layer; and after removing the silicon oxide film, the first conductivity type region is formed by low-temperature oxidation. forming a thin silicon oxide film and a thick silicon oxide film on each of the region surface and the first polycrystalline silicon layer surface; and after removing the thin silicon oxide film, forming the first region surface and the thick silicon oxide film; By forming a second polycrystalline silicon layer containing impurities of one conductivity type on the film surface and heat-treating the silicon substrate, emitters are formed in the second region directly under the first polycrystalline silicon layer. simultaneously forming a third region of one conductivity type and a fourth region of the opposite conductivity type extending from the second region and serving as a side base in the first region directly under the second polycrystalline silicon layer; A method of manufacturing a semiconductor integrated circuit device, comprising: