JPS644627B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital audible tone generator test method.

Digital audible tone generators are used to generate audible tones in time-division switches, particularly in PCM-based time-division switches. This type of digital audible signal tone generator is equipped with a read-only memory that stores digital codes corresponding to sample values obtained by sampling an audible signal tone at a constant cycle, and sequentially stores the digital codes at a constant cycle. The sequential reading generates a digital audible signal tone.

FIG. 1 is a connection diagram showing the configuration of this type of digital audible signal tone generator. In the figure, U/DC
is an up-down counter, and ROM is a read-only memory. As an example, a case will be explained in which a 100 Hz sine wave audible signal tone is generated.

FIG. 2 shows a digital signal corresponding to the waveform of an audible signal tone (100 Hz) obtained from the digital audible signal tone generator. In the figure,
S is the waveform of one period of 100Hz sine wave, and t ₀ ,
t ₁ , ~t ₂₀ ~ _{t 40} ~t ₆₀ ~t ₈₀ indicate some of the points in time when the waveform S is sampled at a constant cycle. If this sampling frequency is 8KHz, one cycle of a 100Hz sine wave will be sampled 80 times, and therefore can be represented by 80 sample values.

The read-only memory ROM in Figure 1 is 0 to 20.
It has 21 addresses, and each address has a second address.
Digital codes corresponding to sampling values at sampling times _t0 to _t20 in the figure are written. This digital code consists of 8 bits, one of which is a sign bit indicating positive or negative (for example, 0
(indicates positive, 1 indicates negative), and the other seven indicate absolute values.

Up-down counter U/DC has a frequency of 8KHz
It receives the clock _fs from 0 and counts it additively from 0 to 20, and when it counts up to 20, it counts subtractively from 20 to 0, and this process is repeated. The count output is given to the read-only memory ROM, and the read-only memory ROM uses this as an address to read out the memory contents at that address and output terminal 1.
Output to ~8. However, the sign bit appearing at the output terminal 1 is always "0", and if necessary, the inverter INV is applied to set it to "1" to indicate positive or negative.

Now, assume that inverter INV has no effect. Assuming that the up-down counter U/DC is sending out 0 as a count output at time t ₀ in FIG. 2, the read-only memory ROM stores the sample value at address 0 at time t ₀ (in this case, (equivalent to ) is sent out.

At time _t1 , the up-down counter U/
The DC receives the clock _fs , counts by 1, and when the count output becomes 1, it sends out a digital code corresponding to the sample value at time _t1 at address 1 of the read-only memory ROM.

The above operation is repeated every time the clock _fs is received, and at times _t2 to _t20 , digital codes corresponding to the sample values corresponding to those times are sent out. In this case, the absolute value of the transmitted digital code gradually increases.

The output of up-down counter U/DC is branched,
Input to maximum value detection circuit TD and minimum value detection circuit HD. When the count output of the up-down counter U/DC reaches its maximum value, that is, 20, this is detected by the maximum value detection circuit TD, which sends a control signal to the up-down counter U/DC.
From then on, control is performed to perform subtraction counting.

When the up-down counter U/DC receives the clock _fs at time _t21 , it performs a subtraction count (20-1=).
Outputs 19. Therefore read-only memory ROM
outputs the contents of address 19. The above operation is repeated and the digital code is sent out in the same manner as above, but the order of sending out the digital code is reversed to the above, so the digital code is sent out as shown at t ₂₁ to _{t 40} in FIG. The absolute value gradually decreases. In this way, the positive half-wave of the 100Hz audible signal tone is transmitted.

At time _t40 , the up-down counter U/
DC outputs 0 as its counting output. this is,
It is also detected in the minimum value detection circuit HD, and thereby controls the up-down counter U/DC to perform additional counting from now on, and also controls the switching circuit T.
It also sends a signal to generate an output, which controls the operation of the inverter INV.

Up-down counter U/DC at time t ₄₁
outputs 1, so read-only memory
The ROM outputs the same digital code as at time _t1 , but the sign bit at output 1 is ``0''.
is converted to "1" by the inverter INV, and becomes a digital code indicating a negative value. In this way, from time _t41 to _t80 , a digital code is sent out which is a negative version of the digital code at time _t1 to _t40 ,
A negative half wave is sent here. In this way
One period of the digitized signal corresponding to a 100Hz sine wave is transmitted.

Note that at time _t80 , that is, at the completion of sending one period of a 100Hz sine wave, the count output of the up-down counter U/DC becomes 0, which is detected by the minimum value detection circuit HD, and the output is changed to the switching circuit. When the signal is sent to T, the switching circuit T switches its output and controls the inverter INV from operating. In this way, the digital audible tone generator returns to its initial state and further clocks.
When f _s is received, the above operation is repeated and the digitalized 100Hz signal tone continues to be transmitted.

FIG. 3a shows the temporal relationship among the count output of the up-down counter U/DC, the output of the minimum value detection circuit HD, the output of the maximum value detection circuit TD, and the output of the switching circuit T. And U/DC in the figure,
HD, TD, and T indicate the output waveforms of compatible devices.

In the above, the frequency of the audible signal sound to be transmitted was set to 100Hz, but by changing the number of addresses in the read-only memory ROM, the memory content of each address, and the counting range of the up-down counter U/DC, what kind of effects can be achieved? Even an audible signal tone of the frequency can be transmitted digitally.

Conventionally, the digital audible signal tone generator shown in FIG. 1 has been tested using a parity check circuit P as shown in FIG. That is, in addition to the above-mentioned digital code, one bit for parity check is stored in each address of the read-only memory ROM, and this bit is read out to the output terminal p. The outputs from output terminals 1 to 8 are led to a parity check circuit P, and a parity check is performed.
Tested.

In this conventional test method, errors in the contents (digital codes) stored in the read-only memory can be detected by the parity check described above, but errors in the contents (digital codes) stored in the read-only memory can be detected by the above-mentioned parity check. Errors in the signal output control device cannot be detected. Therefore, this conventional test method cannot perform a sufficient test, and in order to perform a complete test, a special tester with the same configuration and operation as a multifrequency signal receiver must be prepared. Even with such a tester, it is not possible to test an operating digital audible signal tone generator during actual operation.

The present invention eliminates the shortcomings of the conventional testing method for digital audible signal tone generators, and uses a simple test device to detect errors in the contents of read-only memory, as well as up-down counters, maximum value detection circuits, minimum value detection circuits, etc. It is an object of the present invention to provide a test method that can simultaneously detect errors in a digital signal transmission control device and also enable testing during actual operation of a digital audible signal tone generator.

The invention will now be explained in detail with reference to the drawings.

FIG. 4 is a block diagram showing the connection configuration of one embodiment of the present invention. In the figure, a digital audible tone generator or test apparatus implementing the invention is shown. In the figure, the symbols for the digital audible signal tone generator are the same as those in FIG.

The digital audible signal tone generator has exactly the same structure as the one shown in FIG. 1, and performs the same operation, except that no parity bit is stored in each address of the read-only memory ROM.

In the part of the test equipment constructed according to the present invention, TIM is a timing circuit, COUNT is a normal counter, REG is a register, COMP is a comparison circuit, AG ₁ and AG ₂ are AND gates, and FF is an alarm flip-flop. shows.

The principle of the present invention is to calculate the number of "1"s or "0s" in the digital code read from the read-only memory ROM at the basic cycle of sequentially reading out all the stored contents of the read-only memory. The digital audible signal tone generator of _FIG . ₁ or FIG. ” is determined to be normal, and when they do not match, it is determined to be abnormal.

Next, the operation of the embodiment of the present invention shown in FIG. 4 will be explained. In FIG. 4, the digital audible signal tone generator operates exactly the same as that in FIG. 1, so a description thereof will be omitted.

In the figure, the timing circuit TIM receives the outputs of the minimum value detection circuit HD, the maximum value detection circuit TD, and the switching circuit T, and sends the signals G, R, and A shown in FIG. 3b to its output terminals G, R, and A. This is a logic circuit that outputs.

As already explained, at time t ₀ shown in FIG. 2, the minimum value detection circuit is activated as shown in FIG. 3 a.
HD output is high level (“1”) maximum value detection circuit
The output of TD and switching circuit T is low level (“0”)
Therefore, the timing circuit TIM receives these signals and sends a reset signal to its output terminal R to reset the counter COUNT, switches the output of the output terminal G to "1", and makes the AND gate _AG1 conductive. state.

At time t ₀ to t ₂₀ , read-only memory
The digital code read from the ROM is converted from parallel to serial in the parallel-to-serial conversion circuit PS, and is input to the counter COUNT via the AND gate _AG1 , and the counter COUNT calculates the number of "1" bits in the input signal. Count.

At time _t20 , when the maximum value detection circuit TD detects the maximum value 20 of the count output of the up-down counter U/DC, it sends out a high level output "1", which causes the address 20 accessed at time _t20 to be output.
After the memory contents of are read out and input to the counter COUNT, the timing circuit TIM switches the signal at its output terminal G to "0", makes the AND gate _AG1 non-conductive, and stops counting thereafter.

In this way, the signal sent from the output terminal G causes
A basic cycle is set in which all of the storage contents of the read-only memory ROM are sequentially retrieved, and all of the storage contents are retrieved during this period.

This counted value is compared with the number set in the register REG and actually stored in the read-only memory ROM in the comparator circuit COMP, and when they match, that is, when it is normal, no output is sent and they do not match. In other words, when there is an abnormality, an output is sent.

After the signal from the output terminal G of the timing circuit TIM is switched to "0" and the counting of the counter COUNT is stopped, a signal is sent from the output terminal A of the timing circuit TIM to make the AND gate _AG2 conductive. At this time, if the comparator circuit COMP has an output “1”,
In other words, when there is an abnormality, this output is an AND gate.
Passes through AG ₂ and sets alarm flip-flop FF to indicate abnormality. If normal, no signal is given to the alarm flip-flop FF,
Therefore, since it is not set, no abnormality is displayed.

As can be easily understood from the above explanation, the total number of bits “1” stored in each address of the read-only memory ROM is the counter.
Since it is input to COUNT, if it is normal, the register
Matches the number set in REG. However, due to errors in the contents of the read-only memory ROM, failures during reading, failures in the up-down counter U/DC, and failures in control circuits such as the minimum value detection circuit HD, maximum value detection circuit TD, and switching circuit T, the above Since the two values do not match, a fault in this digital audible tone generator can be indicated by the alarm flip-flop FF.

After the basic cycle for counting bits "1" is over, even if a signal is sent from the minimum value detection circuit HD at time _t40 , the state of the input signal to the timing circuit TIM is Since this is different from the time _t0 , no output is generated at the output terminals G, R, and A, and the above operation is not performed. At time _t80 , the state of the input to the timing circuit TIM is
It is the same as at time _t0 , and the above operation is performed again.

Note that in order to check the match between the predetermined value set in the register REG and the count value of the counter COUNT, it is not necessarily necessary to match all digits.
It is sufficient to verify a small number of digits below that, for example about 4 digits. In this way, the counter COUNT can be constructed as a binary counter with decimal digits, for example, four digits, and in this case, the upper digits are overflowed and discarded.

By doing this, the counter
COUNT, comparison circuit COMP and register REG
The amount of hardware can be reduced.

If you want to count and compare the number of "0"s read from the read-only memory ROM, insert an inverter into the output terminal of the parallel-to-serial converter PS, and connect it to the register.
The total number of "0"s to be stored in the read-only memory ROM is set in REG.

The present invention is not limited to the embodiments described above, and various modifications can be made within the technical scope thereof.

Since the present invention is configured as described above,
It has the effect of simultaneously testing the contents of the read-only memory of the digital audible signal tone generator having the above configuration and the read-out address control device (up-down counter, minimum value detection circuit, maximum value detection circuit, etc.) of the read-only memory. . In addition, the output signal of the digital audible signal tone generator mentioned above is inputted into the parallel-to-serial conversion circuit PS (Fig. 4) in a parallel format, and branched off from the output of the parallel-to-serial conversion circuit PS (see FIG. 4) in a serial format. Therefore, the above test also has the advantage that it can be tested without affecting anything else even when the digital audible signal tone generator is actually operating. Furthermore, the test method according to the present invention requires a simple hardware configuration and a small amount of hardware.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a digital audible signal tone generator to be tested in the present invention and an example of a conventional test method, and FIG. 2 is a diagram showing the lead of the digital audible tone generator shown in FIGS. 1 and 4. A diagram showing the information stored in the only memory and its readout timing, FIG. 3a is a time chart of the signal sent out from the digital signal transmission control device of the digital audible sound generator, and FIG. 3b is a diagram showing the timing of reading the same. FIG. 4 is a time chart of signals sent from the timing circuit of the embodiment of the present invention shown in FIG. 4. FIG. 4 is a block diagram showing the configuration of one embodiment of the present invention. U/DC……up/down counter, ROM……
Read-only memory, HD...minimum value detection circuit,
TD...Maximum value detection circuit, T...Switching circuit, INV
...Inverter, P...Parity check circuit,
TIM...timing circuit, AG ₁ , AG ₂ ...and gate, COUNT...counter, COMP...
Comparison circuit, REG...Register, FF...Alarm flip-flop, PS...Parallel-serial conversion circuit.

Claims (1)

[Claims] 1. It has a read-only memory that stores digital codes corresponding to sample values obtained by sampling an audible signal tone at a fixed period, and reads out the digital codes sequentially at a fixed period to generate a digital audible signal tone. In a testing method for a digital audible signal tone generator which generates “1”
(or "0"), a register that sets the number of "1" (or "0") that should actually be stored in the memory, and the counting results of the counter during the basic cycle. A comparison circuit is provided to compare the set value of the register, the counting result is compared with the set value, and whether the digital audible signal tone generator is normal or abnormal is detected based on whether they match or do not match. Digital audible signal tone generator test method.