JPS644665B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a high voltage semiconductor device and a method for manufacturing the same.
In particular, it relates to highly reliable passivation structures using polycrystalline silicon films.

There is a passivation method that uses a polycrystalline silicon film as a surface protection film for a pn junction of a silicon semiconductor device. A semi-insulating polycrystalline silicon film that is doped with oxygen or nitrogen to increase its resistivity produces less distortion, has a low surface state density, and is highly reliable by shielding the effects of external charges. and
It is suitable for mass production and can be applied to various semiconductor devices.
However, the passivation method using a polycrystalline silicon film has problems in that selective etching is difficult in terms of process and in terms of device characteristics, the current amplification factor h _FE of the transistor decreases. That is, selective etching is required to form contact holes after the passivation process of the polycrystalline silicon film, but since the polycrystalline silicon film requires the same etchant as the silicon single crystal substrate (semiconductor element), it is difficult to etch the polycrystalline silicon film. It is difficult to stop etching at the border. Too much or too little etching amount will cause electrode contact failure. For this reason, both the composition of the polycrystalline silicon film and the etching method have been studied, but it is extremely difficult to find a selective etching method for a polycrystalline silicon film with a low dopant concentration that is most effective in terms of device characteristics. On the other hand, the decrease in the current amplification factor _hFE of the transistor is caused by the large leakage current in the passivation film on the surface of the emitter junction. As a countermeasure to this problem, methods have been proposed for passivation of the emitter junction, such as using a thermal oxide film or removing the polycrystalline silicon film and then destroying the silicon oxide film using a gas phase reaction.
The process becomes complicated due to the problem of selective etching of the polycrystalline silicon film mentioned above.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high voltage semiconductor device passivated with a polycrystalline silicon film, which is characterized by high voltage resistance and high reliability, has a high current amplification factor, and is easy to manufacture, and a method for manufacturing the same.

The present invention is characterized in that, in a high-voltage semiconductor device comprising a silicon single crystal substrate with a plurality of rectifying junctions exposed on one main surface, a main rectifying junction that maintains a main breakdown voltage among the plurality of rectifying junctions; A passivation film with a two-layer structure consisting of a polycrystalline silicon film and a silicon oxide film stacked in sequence is formed on the exposed portion, and the rectifying junctions other than the main rectifying junction among the plurality of rectifying junctions are exposed. A passivation film with a three-layer structure consisting of a silicon oxide film, a polycrystalline silicon film, and a silicon oxide film, which are laminated in sequence, is formed on the passivation film, and an electrode extraction port is formed in a predetermined portion of the passivation film with the three-layer structure. It's at the point where it opens.

The present invention will be described in detail below based on drawings showing embodiments.

FIG. 1a is a schematic cross-sectional view of a state in which the diffusion process for obtaining an npn planar transistor with a breakdown voltage of 1600V has been completed. A silicon single crystal substrate 10 with a resistivity of 90 to 100 Ωcm and a thickness of 280 μm, a phosphorus diffusion layer 11 for a highly concentrated collector, a boron diffusion layer 12 for a base with a depth of 35 μm, and a phosphorus diffusion layer 12 for an emitter with a depth of 10 μm. A layer 13 is formed. Around the base layer 12 is a main rectifier junction J _C that maintains withstand voltage.
to reduce the electric field strength during reverse bias of
A p ⁺ guard ring layer 14 is formed. A silicon oxide film 15 is formed on the surface of the silicon single crystal substrate 10 by diffusion heat treatment.

In FIG. 1b, the silicon oxide film 15 in the area where the main rectifying junction J _C is exposed to the surface is removed by etching with a mixed solution of ammonium fluoride and fluoride, and the strained layer on the surface of the silicon single crystal substrate 10 is further removed. Shows the state etched with an acid-nitric acid mixture. Here, the area where the silicon oxide film 15 is removed is the main rectifying junction J _C
This is the region where the end of the region where the depletion layer expands during reverse bias is exposed to the surface.

FIG. 1c shows a polycrystalline silicon film 16 and a silicon oxide film 1 on the surface of the silicon single crystal substrate 10.
7 is sequentially formed and baked. Here, the polycrystalline silicon film 16 is formed by a gas phase reaction using monosilane and nitrous oxide at 630 to 640°C, and 20% oxygen
(atomic ratio), and the thickness is approximately 0.5 μm. The silicon oxide film 17 is formed by a gas phase reaction using monosilane and oxygen at 380 to 410° C., and has a thickness of about 0.2 μm. Polycrystalline silicon 16 and silicon oxide film 17 can be successively formed in the same gas phase reactor. Baking was performed at 950°C for 30 minutes in a nitrogen stream.

FIG. 1d shows a state in which three layers, silicon oxide film 17, polycrystalline silicon film 16 and silicon oxide film 15, are photoetched to form contact holes 18 and 19 for emitter and base electrodes.
First, the silicon oxide film 17 was coated with a mixed solution of hydrofluoric acid and ammonium fluoride (volume ratio of 1:6), and then the polycrystalline silicon film was coated with a mixed solution of hydrofluoric acid, nitric acid, and acetic acid (1:6).
The silicon oxide film 15 was etched once again with the above solution at a capacitance ratio of 2:6. With this method, the etching of the polycrystalline silicon film 16 by the hydrofluoric acid/nitric acid/acetic acid mixture can be stopped at the underlying silicon oxide film 15, without damaging the silicon single crystal substrate 10, especially the high concentration diffusion layers 12 and 13. I was able to open contact holes 18 and 19.

Figure 1e shows the base electrode 20 formed by the lift-off method.
and shows a state in which an emitter electrode 21 is formed. The electrode materials were chromium, nickel, and silver deposited in sequence, followed by heat treatment at 475°C in a nitrogen stream for sintering and lift-off.

From then on, pelletizing is carried out in the same way as the conventional assembly process.
The transistor is completed after mounting on a heat sink, soldering the emitter and base electrodes, and packaging.

FIG. 2 shows the relationship between the collector current I _C and the current amplification factor h _FE of the above transistor. Curve A is based on the present invention, and curve B is based on the conventional method in which the entire surface of the semiconductor substrate, that is, the emitter junction is also passivated with a polycrystalline silicon film. In the conventional method, h _FE
However, in the semiconductor device according to the present invention, h _FE similar to that of the thermal oxide film-phosphorus glass film passivation was obtained. In addition, the transistor according to the present invention has a collector-emitter breakdown voltage.
BV _CEO is 1850V at a temperature of 150℃ and a leakage current of 0.1mA.
Even in a blocking test of 1600V DC at 150℃ for 1000 hours, there was no change in leakage current.

FIG. 3 shows a schematic cross-sectional view of a planar thyristor 30 having a breakdown voltage of 600V according to the present invention. Completes the same diffusion process as conventional planar thyristors,
After forming the P emitter layer 31, the N base layer 32, the P base layer 33, and the N emitter layer 34, a part of the thermal oxide film 35 formed in the diffusion process is removed, and a polycrystalline silicon film 36, silicon oxide film 37
was formed. Here, the main rectifying junctions are 38 and 39 that maintain voltage resistance in both the reverse direction and the forward direction,
A polycrystalline silicon film 36 is placed directly on the exposed surface of the region where the depletion layer expands during reverse bias of this junction.
is estimated. On the other hand, the surface of the junction 40 between the n emitter layer 34 and the p base layer 33 includes a silicon oxide film 35, a polycrystalline silicon film 36, and a silicon oxide film 3.
It has a three-layer structure. Cathode and gate electrode 4
In No. 1, 42, a three-layer passivation film was photoetched, and then an aluminum vapor-deposited film was formed by a lift-off method.

FIG. 4 shows the distribution of gate trigger current of the planar thyristor shown in FIG. The graph of group a is based on the present invention, and has high sensitivity and small variation. For comparison, the graph of group b is a graph in which the entire surface of a silicon single crystal substrate was directly passivated with a polycrystalline silicon film according to the conventional method. Thyristor gate sensitivity is poor and variation is large. This is because sensitivity deteriorates due to leakage current in the passivation film, and because the end point cannot be clearly determined when etching the polycrystalline silicon film to form contact holes, variations occur in the etching of the surface of the p base layer.

As described above, according to the present invention, a semiconductor device with high breakdown voltage, high reliability, and high current amplification factor can be manufactured by an extremely simple passivation process.

Incidentally, in the present invention, the same effect can be obtained even if the conductivity type of each layer of the transistor and thyristor shown in FIGS. 1 and 3 is reversed.

[Brief explanation of the drawing]

1A to 1E are schematic cross-sectional views showing each manufacturing process of a high voltage semiconductor device according to an embodiment of the present invention;
The figure is a comparison diagram of the characteristics of the high voltage semiconductor device shown in Figure 1 and the characteristics of a conventional semiconductor device. Figure 3 is a schematic sectional view showing a high voltage semiconductor device according to another embodiment of the present invention. FIG. 4 is a comparison diagram of the characteristics of the high voltage semiconductor device shown in FIG. 3 and the conventional semiconductor device. DESCRIPTION OF SYMBOLS 10... Silicon single crystal substrate, 11... Phosphorus diffusion layer for high concentration collector, 12... Boron diffusion layer for base, 13... Phosphorus diffusion layer for emitter, 14...
... p ⁺ guard ring layer, 15 ... silicon oxide film,
16... Polycrystalline silicon film, 17... Silicon oxide film, 18, 19... Contact hole, 20...
...base electrode, 21...emitter electrode, J _C ...main rectifier junction.

Claims (1)

[Scope of Claims] 1. In a high-voltage semiconductor device in which a plurality of rectifying junctions are composed of a silicon single crystal substrate exposed on one main surface, an exposed portion of a main rectifying junction that maintains a main breakdown voltage among the plurality of rectifying junctions; On top, there is a 2 layer consisting of a polycrystalline silicon film and a silicon oxide film stacked in sequence.
A passivation film having a layered structure is formed, and a silicon oxide film, a polycrystalline silicon film, and a silicon oxide film are sequentially stacked on exposed parts of the rectifying junctions other than the main rectifying junction among the plurality of rectifying junctions. A high breakdown voltage semiconductor device, comprising: a three-layered passivation film formed therein; and an electrode outlet opening formed in a predetermined portion of the three-layered passivation film.