JPS646581B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal detection circuit that corrects DC fluctuations in the output signal of a frequency detector that receives a received signal and identifies the signal. Specifically, in time division multiplex communication (TDMA), the present invention provides a signal detection circuit that corrects direct current fluctuations between when burst signals are received and when they are not received, and identifies signals, and a received electric field in a receiver. The present invention relates to a signal detection circuit that corrects DC fluctuations based on level fluctuations and identifies signals.

First, in the time division multiplex communication system, the DC level of the frequency detector output differs between when a burst signal is being received and when it is not, which is a factor that degrades the error rate. This phenomenon will be explained using FIG. 1, which shows a conventional circuit for suppressing direct current fluctuations in the output of a frequency detector.

In Figure 1, 1 is a frequency detector that receives the received signal x ₀ , and its output x ₁ contains an uncertain DC component due to the offset of the received wave, so the DC component is cut off by capacitor 2. has been done. Furthermore, the signal on the output side of capacitor 2
x ₂ is input to comparator 3 to obtain a digital signal. In addition, in Fig. 1, Vref is the reference voltage,
4 is resistance.

Referring to FIG. 2, the waveforms of x ₀ , x ₁ , and x ₂ of FIG. 1 are shown. D in the received signal x ₀ is data. Here, the waveforms of x ₁ and x ₂ show a DC response as shown in FIG. In other words, when a burst signal is received, the waveform becomes a data signal component with respect to the DC voltage corresponding to the center of the received intermediate frequency, but when the burst signal is not received, the input side of the frequency detector is in a noise state. Therefore, as a result of frequency detection, x ₁ in Figure 2
The DC level will shift to another location.

In the conventional example shown in FIG. 1, fluctuations in the DC level can be suppressed to some extent by reducing the constant of the capacitor 2. However, this method
If the value of capacitor 2 is made small for a signal containing a large amount of DC component energy, such as an NRZ signal, intersymbol interference will occur, which will eventually worsen the error rate.

On the other hand, in an FM receiver, when the received electric field level is significantly reduced due to fading or the like, the DC level of the frequency detector output also fluctuates greatly, resulting in a phenomenon where the error rate increases. Particularly when the signal is multi-valued, the DC level fluctuation has a great effect on the error rate. This phenomenon will be explained again with reference to FIG. The circuit configuration in FIG. 1 is as already described. The waveforms of the received electric field levels x ₁ and x ₂ in the circuit of FIG. 1 are shown in FIG. Here, the waveforms of x ₁ and x ₂ show a DC response as shown in FIG. In other words, when the electric field is high enough, the waveform will have a data signal component with respect to the DC voltage corresponding to the center of the received intermediate frequency, but if the electric field is insufficient due to fading, the input side of the frequency detector will be exposed to noise. As a result of frequency detection, the DC level shifts to another location as shown in x ₁ in Figure 3.

In the conventional example shown in FIG. 1, as described above, by reducing the constant of the capacitor 2, fluctuations in the DC level can be suppressed to some extent. However, as mentioned above, with this method, when the value of capacitor 2 is made small for signals that contain a large amount of DC component energy, such as NRZ signals, intersymbol interference occurs, which disturbs the eye pattern in front of comparator 3. This has the disadvantage of deteriorating the reception error rate.

An object of the present invention is to correct the DC fluctuation of the frequency detector output when receiving and not receiving a burst signal, and to perform signal identification even for signals with many DC components such as NRZ signals. An object of the present invention is to provide a signal detection circuit that can reduce deterioration in error rate.

Another object of the present invention is to correct the DC fluctuations in the output of a frequency detector based on the fluctuations in the received electric field level of the receiver, even for signals with many DC components such as NRZ signals, so that the signal can be identified. It is an object of the present invention to provide a signal detection circuit that can reduce the deterioration of error rate.

In the time division multiplex communication system, a time division control circuit constantly monitors which time slot is being used, and controls the transmission or reception of burst signals at its own station. The present invention includes two DC extraction circuits that extract the DC component of the output of the frequency detector when receiving a burst signal in response to a burst signal reception command from the time division control circuit and when not receiving the burst signal. The DC extraction circuit simply consists of an analog switch, a resistor, and an integrating circuit using a capacitor. Then, the difference between the outputs of the two DC extraction circuits is obtained using a subtraction circuit, and the output signal of the frequency detector is corrected using the arithmetic circuit using the signal of the difference. suppress the
This reduces the deterioration of the error rate.

Furthermore, the present invention detects the level of the received electric field using an electric field level detection circuit, and separate circuits are provided for extracting the DC component of the output of the frequency detector when the electric field level is higher than the reference level and when it is lower than the reference level. The DC extraction circuit simply consists of an analog switch, a resistor, and an integrating circuit using a capacitor. Then, the difference between the outputs of the two DC extraction circuits is determined using a subtraction circuit, and the output signal of the frequency detector is corrected using an arithmetic circuit based on the error signal, thereby suppressing DC fluctuations in the output of the frequency detector. However, the deterioration of the error rate is reduced.

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 4, in the first embodiment of the present invention, an input intermediate frequency signal x ₀ is detected by a frequency detector 1 . Reference numeral 5 denotes a time division control circuit which receives the output signal of this signal detection circuit, and issues a burst signal reception command when receiving a burst signal. 7 and 8 are DC extraction circuits. The DC extraction circuits 7 and 8 are analog switches 9 and 12.
and an integrating circuit consisting of resistors 10, 13 and capacitors 11, 14. When a burst signal reception command is generated, the analog switch 9 becomes conductive, and the output of the frequency detector 1 is input to the adder circuit 16 and simultaneously to the DC extraction circuit 7.
The DC voltage e ₁ (see x ₁ in FIG. 2) is stored. When a burst reception command is not issued from the time division control circuit 5, the analog switch 12 is turned on, and the output of the frequency detector 1 is outputted to the DC extraction circuit 8 as a DC voltage e ₂ (see x ₁ in Figure 2). be remembered.
Therefore, when the burst signal is not received, the voltage difference between the voltage stored when the burst signal is received and the voltage e ₀ =
e ₁ - e ₂ (see x ₁ in Figure 2) is obtained by the subtraction circuit 15, and since the analog switch 17 is also conducting at this time, it is added to the output of the frequency detector 1 by the addition circuit 16. . Therefore, the adder circuit 16
When the burst signal is not received, the DC component of the output x ₁₆ is
e ₂ +e ₀ = e ₂ +e ₁ −e ₂ = e ₁ , which is maintained at the same value as when receiving the burst signal. In this way, the DC level of the adder circuit output x ₁₆ when the burst signal is not received is corrected as shown in x ₁₆ in FIG.
Identified by 0. In this way, the adder circuit 16
A portion including the analog switch 17, the capacitor 18, the resistor 19, and the comparator 20 constitutes an identification circuit 30 with a correction function.

As shown in FIG. 4, in addition to adding the signal x ₁₅ of the difference between the outputs of the DC extraction circuits 7 and 8 to the output x ₁ of the frequency detector 1 for correction, the signal x ₁₅ of the difference is also used for identification. The same result can be obtained even if the voltage is subtracted from the reference voltage Vref2 and corrected. Identification circuit with correction function 3 in this case
The 0 part is shown in FIG. In the discrimination circuit ₃₀ with correction function shown in FIG.
1, and an analog switch 22 which receives the difference signal _x15 . And the reference voltage
The output of the analog switch 22 is subtracted from Vref2 by a subtraction circuit 21, and the output of the subtraction circuit 21 is connected to the inverting input terminal of the comparator 20 via a capacitor 24.

By means of the subtraction circuit 21 and the capacitor 24, the difference between the DC voltage Vref2 and the output of the analog switch 22 becomes a reference voltage input to the inverting input terminal of the comparator 20.

Furthermore, as a method for correcting DC fluctuations in the output of the frequency detector 1, there is also a method of lowering the DC level when the burst signal is received to the DC level when the burst signal is not received. To do this, the burst signal reception command signal _x5 must be "Low" when the burst signal is received and "High" when the burst signal is not received. The operation of the circuit is almost the same as in the previous case, and in the above case, the voltage e ₁ when receiving a burst signal
Add the voltage e ₀ , which is the difference between the voltage e ₂ and the voltage e 2 when not receiving, to e ₂ .
I corrected it to keep it the same value as e ₁ , but here e ₁
Corrected by subtracting e ₀ from to keep it at e ₂ .

FIG. 6 shows a signal detection circuit used in the present invention to prevent DC fluctuations from occurring when the electric field is sufficient due to fading or the like. Referring to FIG. 6, the input IF signal x ₀ is input to the frequency detector 1 and also to the electric field level detection circuit 50. In the electric field level detection circuit 50, the electric field level is detected by rectifying and smoothing the IF signal using capacitors 100, 103, resistor 104, and diodes 101, 102, and removing high frequency components using resistor 105 and capacitor 106. The electric field level is a certain reference voltage Vref1
is compared by the comparator 51, and when the electric field _is sufficient, the output
Outputs “High” to the output. As the electric field level detection signal _x5 , noise of the demodulated output of the receiver may be used. In this case, when the electric field level is low,
Since the noise level becomes high, it is necessary to use the comparator 51 with its polarity reversed. It is known that in FM receivers, when the electric field level becomes low, the noise in the demodulated output is not suppressed and increases.

Now, the DC extraction circuits 7 and 8 are composed of analog switches 9 and 12, resistors 10, and
13 and an integrating circuit consisting of capacitors 11 and 14. When the electric field is sufficient, the analog switch 9 becomes conductive, and the output of the frequency detector 1 is input to the comparator 15 and at the same time to the DC extraction circuit 7, resulting in a DC voltage e ₁ (see x ₁ in Figure 3). ) is memorized. When the electric field is insufficient, the analog switch 12 becomes conductive, and the output of the frequency detector 1 becomes a DC voltage e ₂ in the DC extraction circuit 8 (see x ₁ in Figure 3).
is stored as. Therefore, when the received electric field becomes insufficient, the subtraction circuit 15 obtains the voltage e ₀ = e ₁ − e ₂ (see x ₁ in FIG. 3), which is the difference from the voltage stored when the electric field was sufficient. At this time, since the analog switch 17 is also conductive, the adder circuit 16 adds the signal to the output of the frequency detector 1. Therefore, when the electric field is low, the DC component of the output x ₁₆ of the adder circuit 16 becomes e ₂ +e ₀ =e ₂ +e ₁ -e ₂ =e ₁ and is maintained at the same value as when the electric field is sufficient. In this way, the DC level of the adder circuit output x ₁₆ when the electric field is insufficient is:
It is corrected as x ₁₆ in FIG. 3 and identified by comparator 20. In this way, the portion including 16 to 20 constitutes the correction function-equipped identification circuit 30, as in the case of FIG. 4.

As shown in Fig. 6, in addition to correcting the difference signal x ₁₅ of the DC extraction circuits 7 and 8 by adding it to the output x ₁ of the frequency detector 1, the difference signal x ₁₅ is used as a reference voltage for identification. The same result can be obtained by subtracting from Vref2 and correcting it. The configuration of the correction function-equipped identification circuit 30 in this case is also as shown in FIG. 5, and its explanation will be omitted here.

Furthermore, as a method for correcting DC fluctuations in the output of the frequency converter 1, there is a method of lowering the DC level when the electric field level is sufficiently large to the DC level when the electric field level is insufficient. In this case, as shown in FIG. 7, it is sufficient to simply invert the polarity of the comparator 51. The operation of the circuit in FIG. 7 is almost the same as that in FIG. 6, and in FIG. 6, the voltage e ₀ is the difference between the voltage e ₁ when the electric field is sufficient and the voltage e ₂ when the electric field is insufficient. was added to e ₂ to keep it the same value as e ₁ , but here the correction is made by subtracting e ₀ from e ₁ to keep it at e ₂ .

As explained above, the present invention can perform signal identification even for signals with many DC components, such as NRZ signals, by correcting DC fluctuations between when burst signals are received and when burst signals are not received. It is possible to reduce the deterioration of the error rate due to

Furthermore, the present invention can correct the DC fluctuations based on fluctuations in the electric field level of the receiver even for signals that have many DC components, such as NRZ signals, and perform signal identification. Deterioration of error rate can be reduced.

Embodiments of the present invention are listed below.

1. Claim 1, wherein the first and second DC extraction circuits each include an analog switch and an integrating circuit including a resistor and a capacitor.
2. The signal detection circuit according to item 1 or 2.

2. An identification circuit with a correction function synthesizes the difference signal between the output signals of the first and second DC extraction circuits with the output signal of the frequency detector using an adder circuit, and compares this synthesized signal with a reference voltage using a comparator. 3. The signal detection circuit according to claim 1, wherein the signal detection circuit is a circuit for identifying signals by performing the following steps.

3. An identification circuit with a correction function synthesizes the difference signal between the output signals of the first and second DC extraction circuits with the reference voltage of the comparator using a subtraction circuit, and compares the output signal of the frequency detector with the synthesized signal. 3. The signal detection circuit according to claim 1, wherein the signal detection circuit is a circuit for identifying signals by comparing the signals with each other.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a specific example of suppressing DC fluctuations in the output of a conventional frequency detector, and Figure 2 is a circuit diagram of a conventional frequency detector.
A diagram showing specific examples of waveforms of each part in FIG. 4 and FIG. 4,
Fig. 3 is a diagram showing specific examples of waveforms of each part in Figs. FIG. 5 is a circuit diagram showing another embodiment of the discrimination circuit with correction function 30 in FIG. 4. FIG. 6 is a circuit diagram showing an embodiment of the signal detection circuit of the present invention that identifies a signal by correcting it to the DC level of the frequency detector output when the electric field level is sufficient when the electric field level is insufficient; FIG. 7 is a circuit diagram showing an embodiment of the signal detection circuit of the present invention which corrects the DC level of the frequency detector output when the electric field is insufficient and identifies the signal. 1... Frequency detector, 3, 20, 51... Comparator,
5... Time division control circuit, 50... Electric field level detection circuit, 6... Inverter, 7, 8... DC extraction circuit, 9, 12, 17, 22... Analog switch,
15, 21...subtraction circuit, 16...addition circuit, 30...
Identification circuit with correction function, 2, 11, 14, 18, 2
3, 24, 100, 103, 106... Capacitor, 4, 10, 13, 19, 25, 26, 10
4,105...Resistor, 101,102...Diode.

Claims (1)

[Scope of Claims] 1. A frequency detector that receives a received signal, a time division control circuit that generates a burst signal reception command, and a frequency detector that detects the frequency when the time division control circuit generates the burst signal reception command. a first DC extraction circuit that extracts and holds a DC component of an output signal of the frequency detector; and a first DC extraction circuit that extracts and holds a DC component of an output signal of the frequency detector when the time division control circuit is not generating the burst signal reception command. a second DC extraction circuit that outputs a difference between the output signals of the first and second DC extraction circuits; and a subtraction circuit that outputs a difference between the output signals of the first and second DC extraction circuits; The output signal of the subtraction circuit is added to the output signal of the frequency detector when the time division control circuit is not generating the burst signal reception command, and the addition result signal is , the output signal of the subtraction circuit is compared with a reference voltage by an AC-coupled comparator, or the output signal of the subtraction circuit is subtracted from the reference voltage to obtain a subtraction result signal, and the output signal of the frequency detector is compared with the reference voltage. 1. A signal detection circuit comprising: an identification circuit with a correction function that identifies the output signal of the frequency detector by comparing the signal with an AC-coupled comparator. 2. A frequency detector that receives a received signal, an electric field level detection circuit that detects the electric field level of the received signal, and when the electric field level detected by the electric field level detection circuit is equal to or higher than a predetermined value, the output signal of the frequency detector is a first DC extraction circuit that extracts and holds a DC component; and a second DC extraction circuit that extracts and holds a DC component of the output signal of the frequency detector when the electric field level detected by the electric field level detection circuit is below the predetermined value. a subtraction circuit that outputs the difference between the output signals of the first and second DC extraction circuits, and when the electric field level detected by the electric field level detection circuit is above a predetermined value and when it is below a predetermined value. At either one of these times, the output signal of the subtraction circuit is added to the output signal of the frequency detector, and the addition result signal is compared with a reference voltage by an AC-coupled comparator; Alternatively, by subtracting the output signal of the subtraction circuit from a reference voltage to obtain a subtraction result signal, and comparing the output signal of the frequency detector with the subtraction result signal by an AC-coupled comparator,
A signal detection circuit comprising: an identification circuit with a correction function that identifies an output signal of the frequency detector. 3. The signal detection circuit according to claim 2, wherein the electric field level detection circuit is a circuit that detects the electric field level by rectifying and smoothing the level of the intermediate frequency signal of the received signal and further removing high frequency components. . 4. The signal detection circuit according to claim 2, wherein the electric field level detection circuit is a circuit that detects the electric field level by measuring the noise level in the demodulated output of the received signal.