JPS64716B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD OF THE INVENTION This invention relates to smoothing circuits for graphic display devices. [Prior Art] In a raster scan type graphic display device, when diagonal straight lines are displayed, they look like steps, so various methods have been proposed for displaying straight lines smoothly. For example, in the method shown in FIG. 1, end dots indicated by white circles are displayed with lower brightness than other dots. In the method shown in Fig. 1, two electron beams are output simultaneously, two dots are arranged above and below in a multi-stage luminance distribution according to the slope of the straight line, and the sum of the luminances of each two dots is calculated. keep constant. A third method is to increase the resolution of the CRT display device itself. [Problems with Prior Art] However, the first method has a problem in that straight lines appear thick. Furthermore, the second and third methods have the problem of complicating the overall structure and increasing costs. [Object of the invention] This invention was made in view of the above circumstances,
It is an object of the present invention to provide a graphic display device having a smoothing circuit capable of smoothly displaying displayed figures, especially straight lines, with a simple configuration. [Summary of the Invention] A smoothing memory having a one-to-one correspondence with the video memory is provided, and data for controlling the brightness of half-dots at the end of the straight line part of the display figure is calculated and written into the smoothing memory, and the brightness is The purpose is to control the display so that straight lines are displayed smoothly. [Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 2 to 14. FIG. 2 is a block diagram of the graphic display device. 1 in the figure is an input device, and the input data from this input device 1 is sent to the CPU.
(Central processing unit) 2. A main memory device 3 is connected to this CPU 2, and data is exchanged therewith, and a machine clock generated by a clock generator 4 is inputted thereto. Also
Graphics processed and output by the CPU 2 and data for controlling their brightness are written to a video memory 5 and a smoothing memory 6 consisting of RAM (random access memory). The video memory 5 includes memories 5A for each color of red, green, and blue;
It consists of 5B and 5C, and the above graphic data is written therein. Also, the smoothing memory 6 is the video memory 5.
(Memories 5A to 5C) and has a one-to-one correspondence,
Data for brightness control is written. Each memory 5A to 5C and smoothing memory 6
The display data outputted in parallel from the display data is applied to shift registers 7, which are provided in four corresponding series. The data output from the shift register 7 is inputted to a smoothing circuit 8 provided in three series, subjected to smoothing processing, and then given as a signal to a three series DA converter circuit 9.
This DA converter circuit 9 controls the brightness of the input signal and outputs it as a video signal to a raster scan type CRT display device 10 to display a figure. On the other hand, the clock signal output from the clock generator 4 is input to the display address control circuit 11 and the synchronization signal generation circuit 12. Display address control circuit 11 outputs an address control signal to video memory 5 and reads data from video memory 5. Also, the synchronization signal generation circuit 12
outputs horizontal and vertical synchronizing signals to the CRT display device 10. Furthermore, the clock signals output by the clock generator 4 are the load clock and shift clock supplied to the shift register 7. FIG. 3 shows the same smoothing circuit and D-A conversion circuit 9 for the three series mentioned above, and shows the shift registers 7 provided for the memories 5A, 5B, 5C, and 6, respectively.
7B, 7C, and 7D, and each shift register 7
The signals output from A, 7B, 7C, and 7D, respectively,
〓〓 , 〓〓 , 〓〓 , 〓〓 , these signals 〓〓 , 〓〓 , 〓〓 are respectively input to the corresponding series of smoothing circuits 8A, 8B, 8C, and the signal 〓〓 is input to the smoothing circuit 8A, 8
It is commonly input to B and 8C. Furthermore, the signals output from each smoothing circuit 8A, 8B, and 8C, respectively 〓〓 , 〓〓 , 〓〓 , 〓〓 , 〓〓 , 〓
〓 are the corresponding series of D-A converter circuits 9A,
It is input to 9B and 9C. Then, the outputs of the D-A conversion circuits 9A, 9B, and 9C are respectively converted into signals 〓〓,
〓〓 and 〓〓 result in red, green, and blue video signals, respectively. FIG. 4 shows a specific circuit configuration of the smoothing circuit 8A (same as 8B and 8C).
The output of shift register 7A 〓〓 is delay circuit 15
The signal is input to the OR gate 17 via the delay circuit 16, and is also directly input to the OR gate 17. The output of this OR gate 17 is input to the other end of an AND gate 18, which has one end inputted with the output 〓〓 from the shift register 7D. The output of this AND gate 18 is connected to the other end of an open collector OR gate 19, which has one end inputted with the output of the delay circuit 15, and the other end of an AND gate 19, which has the output of the delay circuit 15 inputted to one end via an inverter 20. 21 is input to the other end. Thus, the output of the OR gate 19 is supplied as a signal 〓〓, and the output of the AND gate 21 is supplied as a signal 〓〓 to the D-A converter 9A. FIGS. 5 1 and 2 show two specific examples of the delay circuits 15 and 16. In FIG. 5 1, the output 〓〓 of the shift register 7A is input to the D input terminal of the D-type flip-flop 22. A shift clock from a synchronizing signal generating circuit is applied to the CK (clock) input terminal via an inverter 23.
The set output becomes a delayed signal. On the other hand, the inverter shown in FIG. 52 consists of two inverters 24 and 25 connected in series, and a capacitor 26 whose one end is connected to the connection point between the two and whose other end is grounded. The delay time of both the delay circuits shown in FIGS. 1 and 2 corresponds to half a clock. FIG. 6 shows three systems of D-A converter circuits 9 (e.g. 9
The configuration of A) is shown. The above signal 〓〓 is a resistance
It is connected to the base of the NPN transistor Tr via R _B , and the signal 〓〓 is connected to the input terminal of an open collector OR gate 27 via an inverter 26. On the other hand, voltage +Vcc is applied to switch SW, one end of which is grounded, via resistor R _D. This switch SW is used to adjust brightness for smoothing, and the other end is connected to the input end of the OR gate 27, and is also commonly connected to a video amplifier (not shown) for all three systems. Also, or gate 27
The output of is connected to the base of the transistor Tr via a resistor _R.sub.C. Base of transistor Tr,
A resistor R _A is connected between the collectors, and the emitter is grounded via a resistor _RE . A voltage Vcc is supplied to the collector. The emitter output of the transistor Tr is connected to the CRT via the capacitor C.
It is sent to the display device 9. However, the above resistance R _B ,
The resistance value of R _C is R _B <R _C. Next, the operation of the above embodiment will be explained with reference to FIGS. 7 to 12. Assuming that a straight line is to be drawn on the screen of the CRT display device 10, first, the coordinate data of the starting and ending points of the straight line to be drawn is inputted from the input device 1. The CPU 2 calculates straight line data and brightness control data to be drawn based on the coordinate data using the main memory circuit 3, and calculates the straight line data and brightness control data to be drawn based on the coordinate data.
Display data is written to B and 5C, and brightness control data is written to the smoothing memory 6. For example, if you want to display a straight line in red, the memory for red is 5A.
If you want to display it in green, use green memory 5B.
If you want to display it in white, use 5A, 5B, 5C.
Write linear data to. The display data from the video memory 5 is output word by word to the shift register 7 according to the load clock, and sent bit by bit from the shift register 7 to the smoothing circuit 8 according to the shift clock h. However, if you want to display a yellow diagonal straight line,
Taking the case where 9 bits of a certain raster are written to the video memory 5 as an example, yellow is a composite color of red and green, so if 4 dots out of the 9 dots are to be displayed in yellow, the 7th As shown in the figure, the red and green data are the same, for example "001111000"
becomes. On the other hand, the blue data is data "000000000" with all 9 bits "0". Furthermore, the brightness control data written into the smoothing memory 6 to perform smoothing processing on this straight line is "001000100". Note that a method for creating this brightness control data will be described later. Now, the data written in the video memory 5 and the smoothing memory 6 are supplied to the smoothing circuit 8 via the shift register 7, but in FIG. 4, the red display data is supplied to the red smoothing circuit 8A. and brightness control data
〓〓 is supplied. In the figure, display data 〓
The input terminal to which 〓 is supplied is a, the input terminal to which the brightness control data 〓〓 is supplied is b, the output terminal of the delay circuit 15 is c, the output terminal of the delay circuit 16 is d, the output terminal of the OR gate 17 is e, If the output terminal of the AND gate 18 is f, the signals at each point a to f and the output signals 〓〓, 〓〓 are as shown in the time chart of Fig. 8. In other words, "001111000" of the red display data 〓〓 is delayed by half a clock in the delay circuit 15 and becomes the signal c, and then the red display data 〓〓 becomes the signal c.
The signal d is delayed by half a clock. Furthermore, these signals a and d are passed through the OR gate 17 to e
The signal e and the signal b pass through the AND gate 18 and become the signal f. Therefore, the output signal 〓〓 becomes the OR output of the signal of c and the signal of f, and the output signal 〓〓 becomes the AND output of the inverted signal of the signal of c and the signal of f. The signal 〓〓 is input to the resistor R _B of the DA converter circuit 9A shown in FIG. 6, and the signal 〓〓 is input to the inverter 26. In this D-A conversion circuit 9A, if the output terminal of the OR gate 27 is ○A, and the base of the transistor Tr is ○B, the potentials and output signals of points ○A and ○B with respect to the signals 〓〓, 〓〓 are as shown in the table below. It becomes like this.

【table】

〔Effect of the invention〕

As explained above, the present invention provides a smoothing memory that has a one-to-one correspondence with a video memory, and calculates and writes data for controlling the brightness of the end of a straight line part of a display figure into this smoothing memory. Since the brightness is controlled, smooth straight lines can be displayed without increasing the cost or making the straight lines thicker.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional linear display, FIG. 2 is a system diagram of a graphic display device according to an embodiment of the present invention, and FIG. 3 is a diagram showing a smoothing circuit 8 and D-
A specific connection diagram of the A conversion circuit 9, FIG. 4 is a detailed circuit diagram of the smoothing circuit 8, and FIG. 5 is a detailed circuit diagram of the delay circuit 1.
5 and 16, FIG. 6 is a detailed circuit diagram of the D-A conversion circuit 9, FIG. 7 is a diagram showing an example of specific storage contents of the video memory 5 and the smoothing memory 6, and FIG. 7 is a diagram showing a time chart for explaining the operation of the smoothing circuit 8 in the example, FIG. 9 is a diagram showing a time chart for blue in the same example, and FIG. 10 is a coordinate structure in the video memory 5 and smoothing memory 6. Figure 1 showing
Figure 1 shows video memory 5 and smoothing memory 6.
FIG. 12 is a flowchart for explaining the operation of writing data into the memory, and FIG. 12 is a diagram showing a display example and the storage states of the video memory 5 and the smoothing memory 6 at that time. 1...Input device, 2...CPU, 3...Main storage device, 4...Clock generator, 5 (5A~
5C)...Video memory, 6...Smoothing memory, 7 (7A to 7D)...Shift register, 8
(8A to 8C)...Smoothing circuit, 9 (9A
~9C)...D-A conversion circuit, 10...CRT display device, 11...Display address control circuit, 15,
16...Delay circuit.

Claims (1)

[Claims] 1 In a graphic display device, a smoothing memory having a dot-by-dot correspondence with the video memory, and brightness control data for controlling the brightness of display figures written in the video memory are calculated and used for the smoothing. The brightness of the display figure is controlled in half-dot units according to the calculation means written to the memory and the brightness control data of the smoothing memory written by the calculation means, so that the display figure is displayed smoothly. A graphic display device comprising smoothing means.