JPS64734B2 - - Google Patents
Info
- Publication number
- JPS64734B2 JPS64734B2 JP56058179A JP5817981A JPS64734B2 JP S64734 B2 JPS64734 B2 JP S64734B2 JP 56058179 A JP56058179 A JP 56058179A JP 5817981 A JP5817981 A JP 5817981A JP S64734 B2 JPS64734 B2 JP S64734B2
- Authority
- JP
- Japan
- Prior art keywords
- code
- sel
- ctr
- field
- dedicated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Description
【発明の詳細な説明】
本発明は、情報処理装置の各部の事象を示すデ
ータを収集する方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for collecting data indicating events in each part of an information processing device.
情報処理装置の各部の事象を示すデータ例えば
中央処理装置からメモリへ何回リクエストがあつ
たか、応答、割込みは何回あつたかなどを記録す
る専用機構（パーフオーマンスアナライザ）を情
報処理装置に設けてその専用機構の記録から装置
の性能を知ることが行なわれている。また情報処
理装置の動作中制御用メモリからマイクロ命令が
次々と読出され、実行されて行くが、あるマイク
ロ命令は何回位使用されたかは、プログラムの開
発、改良、エラー検出などに有効である。本発明
は後者のモニタリングが可能になるようにし、そ
して該モニタリングに前記専用機構を兼用してハ
ードウエアの簡素化を図ろうとするものである。
即ち本発明は装置各部の事象を示すデータを複数
個の記録手段に選択収集して監視を行なう専用機
構を備えた情報処理装置のデータ収集方式におい
て、制御用メモリから読出されるマイクロ命令に
該命令監視のための専用制御フイールドを与えて
該フイールドに所定コードを書込んでおき、プロ
グラム実行に際して該フイールドのコードを読出
し、デコードして、そのデコード出力をコード別
に前記専用機構の複数個の記録手段に選択記録す
ることを特徴とするが、次に図面を参照しながら
これを説明する。 Information processing equipment is equipped with a dedicated mechanism (performance analyzer) that records data indicating events in each part of the information processing equipment, such as how many requests were made from the central processing unit to the memory, and how many responses and interrupts were received. The performance of the device is known from the records of its dedicated mechanism. Furthermore, microinstructions are read out one after another from the control memory during the operation of an information processing device and executed, and knowing how many times a certain microinstruction is used is useful for program development, improvement, error detection, etc. . The present invention attempts to make the latter monitoring possible and to simplify the hardware by using the dedicated mechanism for the monitoring.
That is, the present invention relates to a data collection method for an information processing device that is equipped with a dedicated mechanism for selectively collecting and monitoring data indicating events in each part of the device in a plurality of recording means, and is applicable to microinstructions read from a control memory. A dedicated control field for command monitoring is provided, a predetermined code is written in the field, and when the program is executed, the code in the field is read and decoded, and the decoded output is recorded in a plurality of records of the dedicated mechanism for each code. The method is characterized in that selective recording is performed in the means, which will be explained next with reference to the drawings.
図面で１０はパーフオーマンスアナライザで、
複数個のカウンタCTR0，CTR1，CTR2、セレク
タSEL0，SEL1，SEL2、装置各部の事象を表わ
すデータPHDを転送するバスＢ、セレクタの切
換えを行なうレジスタM0，M1，M2を備える。
２０は中央処理装置の制御プログラムのメモリ部
を示し、コントロールスタツクCS、該CSへの書
込みデータのレジスタCSWR、該CSからの読出
しデータのレジスタCSDR、該CSをアクセスす
るアドレスのレジスタCSARを備える。本発明で
はCSに格納されるマイクロプログラム（マイク
ロ命令）にモニタリングのための専用制御フイー
ルドを与え、このフイールドに所定のコードを書
込んでおく。図ではCSの点線領域２２が上記専
用制御フイールドを格納するメモリ領域であり、
それがレジスタCSDRの２８に読出される。該レ
ジスタの部分２４，２６はCSのアドレス制御及
び各部の制御回路に入力される。CSDRに記録さ
れたフイールド２８のコードPAはデコーダDEC
へ入力され、デコード出力はセレクタSEL0〜
SEL2へモニタリングされるべき事象の１つとし
て入力される。本例ではマイクロ命令に含ませる
コードは２値符号２ビツトとしPA＝１ならセレ
クタSEL0へ、PA＝２ならセレクタSEL1へ、PA
＝３ならセレクタSELへ“１”信号を与えるよう
にされる。 In the drawing, 10 is a performance analyzer.
A plurality of counters CTR 0 , CTR 1 , CTR 2 , selectors SEL 0 , SEL 1 , SEL 2 , bus B for transferring data PHD representing events in each part of the device, registers M 0 , M 1 , M for switching selectors Equipped with 2 .
Reference numeral 20 denotes a memory section for the control program of the central processing unit, which includes a control stack CS, a register CSWR for writing data to the CS, a register CSDR for reading data from the CS, and a register CSAR for the address to access the CS. . In the present invention, a dedicated control field for monitoring is provided to the microprogram (microinstruction) stored in the CS, and a predetermined code is written in this field. In the figure, the dotted line area 22 of CS is the memory area that stores the above-mentioned dedicated control field,
It is read into register CSDR 28. Portions 24 and 26 of the register are input to the address control of CS and the control circuit of each part. Code PA in field 28 recorded in CSDR is decoder DEC
The decoded output is input to selector SEL 0 ~
Inputted to SEL 2 as one of the events to be monitored. In this example, the code included in the microinstruction is a 2-bit binary code, and if PA = 1, it goes to selector SEL 0 , if PA = 2, it goes to selector SEL 1 , and PA
If =3, a "1" signal is given to the selector SEL.
バスＢを通して送られる事象データも、当該事
象が発生したら“１”、発生しなければ“０”で
ある。事象は多数あり、従つてバスＢは多数の信
号線からなる。セレクタSEL0はレジスタM0の内
容によりバスＢのデータまたはデコーダ出力のあ
ずれかを選び、選択したものが“１”であればカ
ウンタCTR0へ“１”を入力する。図示しないが
カウンタCTR0へはクロツクが入力され、セレク
タ出力が“１”のときこのクロツクを計数する。
セレクタSEL1，SEL2、カウンタCTR1，CTR2も
同様である。 The event data sent through bus B is also "1" if the event occurs, and "0" if it does not occur. There are many events, so bus B consists of many signal lines. The selector SEL0 selects either the data on the bus B or the decoder output according to the contents of the register M0 , and if the selected one is "1", inputs "1" into the counter CTR0 . Although not shown, a clock is input to the counter CTR 0 , and this clock is counted when the selector output is "1".
The same applies to selectors SEL 1 and SEL 2 and counters CTR 1 and CTR 2 .
この装置でセレクタSEL0は事象データPHDの
うちのａかデコーダDECのPA＝１出力を選択
し、セレクタSEL1はPHDのうちのｂかDECの
PA＝２出力を選択し、セレクタSEL2はPHDの
うちのｃかDECのPA＝３出力を選択するように
設定されたとし、更にSEL0はPA＝１を選択し、
SEL1，SEL2はPHDのｂ，ｃを選択するように
レジスタM0〜M2がデータセツトされたとし、こ
の状態でCPU CSのマイクロ命令が読出され情報
処理が開始されたとすると、該マイクロ命令の専
用制御フイールド２８のコードPAがデコーダ
DECに入力され、デコードされる。該コードPA
が１であればセレクタSEL0を通して“１”信号
がカウンタCTR0へ入力され、該カウンタはクロ
ツクを計数する。フイールド２８のコードPAが
２または３であればセレクタSEL1またはSEL2へ
“１”信号が送られるが、これらのセレクタはデ
コーダ出力を選択しないからカウンタCTR1，
CTR2でPA＝２、PA＝３の計数が行なわれるこ
とはない。コードPAはマイクロ命令の種類を表
わすとすると、PA＝１なる種類のマイクロ命令
が実行されたか、その実行時間はどの位であつた
かがカウンタCTR0の計数値により分る。この間
他方のカウンタCTR1，CTR2は事象データPHD
のうちのｂ，ｃについての計数を行ない、その計
数値はｂ，ｃがあつたか、どれ位続いたかを示
す。こうして本装置によれば装置各部の事象のア
ナライザ１０にマイクロ命令のモニタリングも行
なわせることができ、マイクロ命令のモニタリン
グを別個の機構により行なう場合に比べてハード
ウエアの大幅な簡素化が可能になる。 In this device, selector SEL 0 selects a of the event data PHD or PA = 1 output of the decoder DEC, and selector SEL 1 selects b of the PHD or PA = 1 output of the decoder DEC.
Suppose that PA=2 output is selected, selector SEL 2 is set to select c of PHD or PA=3 output of DEC, and SEL 0 selects PA=1,
SEL 1 and SEL 2 are data set in registers M 0 to M 2 so as to select b and c of the PHD, and if the micro instruction of the CPU CS is read in this state and information processing is started, the micro The code PA in the dedicated control field 28 of the instruction is the decoder.
Input to DEC and decoded. The code PA
If is 1, a "1" signal is input to the counter CTR 0 through the selector SEL 0 , and the counter counts the clocks. If the code PA in the field 28 is 2 or 3, a "1" signal is sent to the selector SEL 1 or SEL 2 , but since these selectors do not select the decoder output, the counters CTR 1 ,
In CTR 2 , counting of PA=2 and PA=3 is never performed. Assuming that the code PA represents the type of microinstruction, the count value of the counter CTR 0 determines whether a microinstruction of the type PA=1 was executed and how long it took to execute. During this time, the other counters CTR 1 and CTR 2 are event data PHD.
Of these, b and c are counted, and the counted values indicate whether b and c were warm and how long they lasted. In this way, according to this device, the event analyzer 10 of each part of the device can also monitor microinstructions, and the hardware can be significantly simplified compared to the case where microinstructions are monitored by a separate mechanism. .
この装置のカウンタなどの個数、マイクロ命令
に含ませるコードのビツト数などは必要に応じて
増減する。また上記の例ではデコーダ出力を選ん
だセレクタSEL0では事象データPHDのａが記録
されないことになるが、これで支障なければこの
ままとし、支障あれば他のセレクタに事象データ
ａを選択させればよい。セレクタがどちらのデー
タを選択したかは適宜記録しておくとよい。 The number of counters in this device, the number of bits of code included in a microinstruction, etc. are increased or decreased as necessary. Also, in the above example, event data PHD a will not be recorded in the selector SEL 0 that selected the decoder output, but if this does not cause any problem, leave it as is, and if there is a problem, let another selector select event data a. good. It is advisable to appropriately record which data the selector has selected.
以上説明したように本発明によればパーフオー
マンスアナライザを利用してマイクロプログラム
のモニタリングを行なうことができ、ハードウエ
ア簡素化、コスト低減に有効である。 As described above, according to the present invention, microprograms can be monitored using a performance analyzer, which is effective in simplifying hardware and reducing costs.
図面は本発明の実施例を示すブロツク図であ
る。
図でPHDは事象データ、CTR0〜CTR2は記録
手段、１０は専用機構、CSは制御用メモリ、２
８は専用制御フイールド、PAは所定コード、
DECはデコーダ、SEL0〜SEL2はセレクタであ
る。
The drawing is a block diagram showing an embodiment of the invention. In the figure, PHD is event data, CTR 0 to CTR 2 are recording means, 10 is a dedicated mechanism, CS is control memory, 2
8 is a dedicated control field, PA is a specified code,
DEC is a decoder, and SEL 0 to SEL 2 are selectors.
Claims (1)
手段に選択収集して監視を行なう専用機構を備え
た情報処理装置のデータ収集方式において、制御
用メモリから読出されるマイクロ命令に該命令監
視のための専用制御フイールドを与えて該フイー
ルドに所定コードを書込んでおき、プログラム実
行に際して該フイールドのコードを読出し、デコ
ードして、そのデコード出力をコード別に前記専
用機構の複数個の記録手段に選択記録することを
特徴とした情報処理装置のデータ収集方式。1. In a data collection method for an information processing device that is equipped with a dedicated mechanism for selectively collecting and monitoring data indicating events in each part of the device in a plurality of recording means, the microinstructions read from the control memory contain instructions for monitoring the instructions. A dedicated control field is provided for the purpose, a predetermined code is written in the field, and when the program is executed, the code in the field is read and decoded, and the decoded output is selected for each code to the plurality of recording means of the dedicated mechanism. A data collection method for an information processing device characterized by recording.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56058179A JPS57172453A (en) | 1981-04-17 | 1981-04-17 | Data collecting system for information processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56058179A JPS57172453A (en) | 1981-04-17 | 1981-04-17 | Data collecting system for information processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57172453A JPS57172453A (en) | 1982-10-23 |
| JPS64734B2 true JPS64734B2 (en) | 1989-01-09 |
Family
ID=13076772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56058179A Granted JPS57172453A (en) | 1981-04-17 | 1981-04-17 | Data collecting system for information processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57172453A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59165159A (en) * | 1983-03-10 | 1984-09-18 | Nippon Telegr & Teleph Corp <Ntt> | Monitoring device for system operation |
| JPH0772875B2 (en) * | 1986-06-11 | 1995-08-02 | 日本電気株式会社 | Micro program evaluation method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49130649A (en) * | 1973-04-13 | 1974-12-14 | ||
| JPS5361940A (en) * | 1976-11-16 | 1978-06-02 | Nippon Telegr & Teleph Corp <Ntt> | Debug system for microprogram |
| JPS5531152U (en) * | 1978-08-18 | 1980-02-28 |
-
1981
- 1981-04-17 JP JP56058179A patent/JPS57172453A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57172453A (en) | 1982-10-23 |
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