JPS647387B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Technical Field> The present invention relates to a display device such as a CRT, and in particular is configured so that the entire display screen can be displayed in a blinking manner when an abnormal condition is detected.

<Prior art> In general, CRT display devices have abnormal conditions (errors) in the device itself, the central processing unit, or other terminal devices.
Various other notification functions such as message display are provided to notify the operator of the occurrence. Conventional CRT display devices mainly display messages by blinking or changing color.
When a variety of status displays were used, there was a problem in that the blinking or color change of some characters could not sufficiently notify abnormal conditions.

<Objective> The present invention has been made in view of the problems of the prior art, and provides a display device that makes abnormal state display particularly easy to see in a graphic display device by blinking the entire display screen when an abnormal state is detected. The purpose is to provide.

<Example> The present invention will be explained in detail below based on the drawings.

FIG. 1 is a block circuit diagram of a color display device according to the present invention.

In the figure, ten central control circuits (CPUs) are controlled based on a program in a program memory 11 that stores program data in advance.

12 is a data memory in which various buffers, flags, etc. controlled by the CPU 10 are formed;
1 and is connected to the data bus 20.

The data bus 20 also includes a graphic display control unit (GDC) 13.
and a logic/table circuit 15 for blinking the graphic pattern.

The GDC 13 stores graphic information supplied under the control of the CPU 10 in the display memory 14 as a graphic dot pattern, and is currently commercially available and well known. Display memory 14
has a memory configuration for four screens, DM ₀ to DM ₃ , and each dot pattern is stored independently under the control of the CPU 10.
These dot data are accessed simultaneously in synchronization with the raster scanning of the CRT 16, and the corresponding dot data is read out.

For example, CRT16 is a 14-inch 768 dot x 550
It consists of a dot display screen and is raster scanned by the horizontal synchronization signal (HSYNC) and vertical synchronization signal (VSYNC) from the GDC 13. Although not shown, a keyboard device and various terminal devices are connected to the data bus 10 via an interface unit.

The logic/table circuit 15 stores color information and graphic blink information in a table under the control of the CPU 10 via the data bus 20 according to each logic condition, and also stores the color information and graphic blink information in the table according to each logic condition.
Based on the logic of the dot data read out in synchronization with the raster scan of the screen, a corresponding table is selected to determine the color and the presence or absence of blinking.

FIG. 2 shows a specific circuit example of this logic/table circuit 15, and will be explained in more detail with reference to this figure.

34 is a table memory, and a latch circuit 33
accessed by address data from.
One location accessed by this address data stores color information based on three primary colors and blink information. In this example, 16 locations are provided by 4-bit addresses. Therefore, 16 colors can be expressed, and 16 colors can be expressed simultaneously.
The presence or absence of blinking can be specified depending on the state of the street graphic pattern. Data at each location is addressed by the latch circuit 33 and stored via the data bus 20 under control from the CPU 10.

This latch circuit 33 is supplied with 4-bit dot data read simultaneously from each screen memory DMi of the data memory 14 shown in FIG. address counter 3
Address data from 1 is supplied via selector 32.

Furthermore, the dot data of the three primary colors read out from the table memory 34 according to the dot data from the display memory 14 is stored in the latch circuit 35, and at the same time, the blink data read out from the memory 34 is supplied to one of the gates 37. The other end of this gate 37 is supplied with the output of the blink pulse generator 36, that is, a pulse signal of several hundred MS that determines the blink period, and when the conditions with the blink data are satisfied, it is stored in the latch circuit 35. Reset the dot data. That is, the dot data is reset or not reset by the pulses of the blink pulse generator 36, thereby performing data blinking.
Further, when there is a blink signal "0" from the table memory 34, the gate 37 is always closed and therefore no blinking occurs.

Next, based on Figure 3, logic/table circuit 1
5 and the data memory 14 will now be explained in a little more detail.

Now, a triangular figure _P1 is stored in the display memory DM ₀ , and a triangular figure _P1 (same position as the figure _P1 in the memory DM ₀ ) and a circular figure _P2 are stored in the same _DM1 . shall be. The same positions are sequentially read out from these display memories DM ₀ and DM ₁ in synchronization with the raster scanning of the CRT 16, but when the P ₃ position with no graphic data is read out, it becomes a "0" output. Both b ₁ and b ₂ of the latch 33 become "0" to indicate the t ₀ line of the table memory 34, and the data is read out to determine the dot color and blink (BB).

Also, when the P ₁ position is read, both b ₁ and b ₂ are “1”
Then, _t3 of the table memory 34 is designated. Similarly, when the P ₂ position is read, b ₁ =0, b ₂ =1, and table memory t ₂ is designated. Therefore,
When the blink bit B ₃ of t ₃ is set to "1", the figure P ₁ is displayed blinking, and the blink bits B ₁ , B ₂ ,
If you store "1" in all of _B3 , all the shapes will blink.

Now, when an error is detected in the CPU 10, an error command is generated, and this error command causes the blink bit BB of the table memory 34 to be changed.
If "1" is written to all bits other than _B0 , the display bits of the latch 35 are periodically erased by the pulses of the blink pulse generator 36 as described above. I will do it. Also, in particular, write “1” to all display memory and set _B3 of blink bit BB to “1”.
By doing so, the entire display screen is blinked without being displayed graphically, making it easy to determine the abnormal state.

Note that although the above example is for a color display device, it can also be applied to a monochrome display device.

<Effects> As described above, since the display device of the present invention is provided with means for blinking the entire display screen when an abnormal state is detected, the display of the abnormal state becomes very easy to see and there is no risk of missing it.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram of a display device according to the present invention, FIG. 2 is a specific circuit example of a logic/table circuit, and FIG. 3 is a diagram for explaining the relationship between the logic/table circuit and data memory. be. 10 is CPU, 11 is program memory, 12
1 is a data memory, 13 is a graphic display control unit, 14 is a display memory, 15 is a logic/table circuit, 34 is a table memory, 35 is a latch, and 36 is a blink pulse generator.

Claims (1)

[Scope of Claims] 1. In a display device that displays graphic patterns in color, each color information to be displayed in color on the display screen and blink data indicating whether or not to blink the corresponding color information corresponding to each color information. and a rewriting means for rewriting the blink data in the storage means in response to the detection signal when an abnormal state is detected so that all of the color information is blinked, A display device characterized in that sometimes the entire screen is blinked based on the blink data in the storage means rewritten by the rewriting means.