JPS647507B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor logic integrated device, and more particularly to a semiconductor logic integrated device employing a scan path method. Recent advances in manufacturing technology such as microfabrication technology and the development of CAD tools have eliminated limitations on design man-hours, resulting in the increase in logic scale and the ability to realize complex logic in recent semiconductor logic integrated devices. I'm getting used to it. Generally, as the logic scale increases, the number of sequential circuits incorporated into a semiconductor logic integrated device increases, and an extremely large number of combinations of input signals (input patterns) are required to set the state of the sequential circuits. Furthermore, this sequential circuit requires a large number of input patterns to confirm its internal state. An increase in the number of input patterns requires a large amount of man-hours to create them, and in order to perform functional tests on the logic integrated circuit, an expensive LSI tester that can generate a large number of test vectors is required. When designing and developing integrated circuits, how functional tests are performed has come to have a significant impact on the number of development steps.

For example, a semiconductor logic integrated device has a simple combinational circuit section 102 and a scan circuit section as shown in FIG.
It is constituted by a path configuration sequential circuit section 101. This scan path configuration sequential circuit section 101 is
It further comprises a changeover switch 103 and a sequential circuit 104, and a control signal from a shift control terminal 105 operates the changeover switch 103 to select whether to configure a scan path or a normal logic circuit.

During normal operation, this semiconductor logic integrated device transfers signals between the chip and the outside through terminals 109 and 110.
and 111, and when configuring a scan path, the clock signal from the clock terminal 107 inputs the signal bit by bit from the shift input terminal (SIN) 106 to the internal sequential circuit 104 to set the internal state. . Also, from the shift/output terminal (SOT) 108, the sequential circuit 10 is clocked bit by bit by the clock signal from the clock terminal 107.
The internal state of 4 is read out.

Since this conventional semiconductor logic integrated device shifts only one bit for each pulse of the clock signal from the clock terminal 107, assuming that the number of sequential circuits is N, it is difficult to set the state of any sequential circuit. In the worst case, N clock pulses are required for the scan path, and if this was done without using an expensive LSI tester, the operation would be extremely complicated, the scale of the equipment would increase, and the number of bits in the scan path would be N.
However, the more it increases, the more complicated it becomes.

In this way, a semiconductor logic integrated device separates its internal sequential circuits from the combinational circuits using a certain control signal, constructing a path (scan path) that causes all of the internal sequential circuits to operate as a series of shift registers. The state of the sequential circuit of a logic integrated circuit can be freely set by inputting an external serial signal, and the state set in the sequential circuit can also be changed.
Using this scan path, it was possible to output the serial signal to the outside, but if the internal state of the semiconductor logic integrated device could be set freely, it would be possible to test the remaining combinational circuits using a simple algorithm. Since it is only necessary to consider the combinations of input signals, it is possible to automatically create test patterns using a computer, which greatly reduces the number of man-hours required to develop logic integrated circuits.

However, even if this scan path is introduced into the circuit configuration of conventional semiconductor logic integrated devices, functional tests of logic integrated circuits require the use of expensive LSI testers or complicated operations to test serial input signals. Sending the information into the logic integrated circuit and reading out the internal state of the logic integrated circuit also requires complicated operations. As the number of circuits increases and the number of scan path bits increases, the complexity increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor logic integrated device which eliminates the drawbacks of conventional semiconductor logic integrated devices and which allows setting the internal state of a large-scale logic integrated circuit and facilitating functional testing.

Furthermore, an object of the present invention is to provide a logic integrated circuit that includes:
configure a scan path, and further configure the scan path.
An object of the present invention is to provide a semiconductor logic integrated device in which an oscillator that generates a pulse train corresponding to the number of path bits is formed in a chip to facilitate functional testing.

According to the present invention, in a semiconductor logic integrated device having a combinational circuit and a sequential circuit section, all of the sequential circuit sections are provided with a path (scan path) that operates as a series of shift registers, and
A semiconductor logic integrated device is obtained, which is characterized in that it includes an oscillation circuit section that generates pulse trains as many as the number of bits in the scan path.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows a semiconductor logic integrated device according to an embodiment of the present invention. In FIG. 2, this embodiment includes a combinational circuit section 201, a sequential circuit 202 connected to the combinational circuit section 201 and forming a series of shift registers, and an oscillation circuit connected to the sequential circuit 202 that generates a pulse train. A circuit section 203 is included.

The combinational circuit section 201 is the combinational circuit 10 in FIG.
2, and the sequential circuit section 202 corresponds to the sequential circuit section 101 in FIG. The sequential circuit section 202 has a scanner configuration, functions as a series of shift registers, and has a shift input terminal 204 and a shift output terminal 205.

The oscillator circuit section 203 is an oscillator that generates a pulse train as many as the number of bits of the scan path, and operates as a normal oscillator in response to an oscillation control signal 206, and also as a chip clock signal. Furthermore, this oscillation circuit section 203 has an oscillation start instruction terminal 2.
With one pulse signal from 07, the scan
By generating as many pulse trains as the number of bits in the path and inputting this pulse train as the scan path clock, the states of all bits in the sequential circuit can be set and read. In other words, the scan path configuration sequential circuit section 202 can be arbitrarily set and read out with a single pulse signal, eliminating the need for complicated operations.

FIG. 3 shows a specific example of the configuration of the oscillation circuit section used in this embodiment, and FIG. 4 shows a timing chart showing the operation of the oscillator shown in FIG. 3. In FIGS. 3 and 4, the oscillation circuit section 203 is composed of a gate circuit, an inverter circuit, etc., and includes an oscillator 301 connected to an oscillation control terminal, and a counter composed of a plurality of flip-flops and connected to the oscillator 301. 302, a flip-flop 306 which is connected to the oscillation control start terminal 207 and operates the counter 302, and an AND circuit 311 which sends out an oscillation output signal.

The output terminal of the oscillator 301 is connected to an AND circuit 311 and an inverter circuit 312, and the output terminal of the AND circuit 311 is connected to the oscillation output terminal 208. The inverter circuit 312 is the counter 3
It is connected to one end of a flip-flop and AND circuit 313 on the input side of 02.

In the counter 302, the output of each flip-flop is connected to a NAND circuit 321, and the output thereof is connected to an AND circuit 313 and an OR circuit 315 of the oscillator 301. The output of AND circuit 313 is connected to the R terminal of flip-flop 306.

The Q output terminal of the flip-flop 306 is connected to an AND circuit 311 via an inverter circuit 314.

Next, when a signal "1" is input to the oscillation control terminal 206, the oscillator 301 oscillates unconditionally and functions as a chip clock. This oscillator 30
1 when the signal at the vibration control terminal 206 is “0”;
By inputting one pulse a as shown in FIG. 4 to the oscillation start instruction terminal (CKST) 207,
Q output signal b of flip-flop 306 is “1”
Then, the counter 302 is initialized. When this counter 302 is initialized, the output signal c of the counter 302 becomes "1", and the oscillator 30
1 starts oscillating. When oscillation starts, the flip-flop 306 is reset, the initialization signal of the counter 302 is released, and according to the oscillation output of the oscillator, the counter 302 starts counting operation, and all the flip-flops constituting the counter 302 are reset. When the Q output signal of the NAND circuit 321 becomes "1", the output signal c of the NAND circuit 321 becomes "0", and the oscillator 301 stops. i.e. counter 30
2 is possible by appropriately combining and initializing the set and reset of each flip-flop.
pulse trains can be generated.

Therefore, the oscillator 301 can send out a desired number of pulses e from the AND circuit 311.

Next, the semiconductor logic integrated device of this embodiment will be explained with reference to FIG. In FIG. 5, the semiconductor device 200 of this embodiment is connected to an internal state setting shift register 520 and an internal state reading shift register 530. To perform a functional test of this semiconductor device, first set the data input terminal 521 of each bit of the internal state setting shift register 520 to "0" or "1" using a simple changeover switch, etc. A parallel load is performed on the state setting shift register 520.

Next, this semiconductor logic integrated device 200 inputs one pulse to the oscillation start instruction terminal (CKST) to register the internal state setting shift register 5.
20 states are written from the shift input terminal (SIN) to set the desired internal state. After setting the internal state, check the output signal of the output terminal with respect to the input signal of other input terminals, and then input the next pulse to the oscillation start instruction terminal (CKST) to read the internal state. shift register 5
At 30, the internal state is read from the shift output terminal (SOT).

The internal state of the internal state reading shift register 503 can be easily checked by attaching a simple display device such as an LED to the Q output of each flip-flop.

In this embodiment, by performing a series of operations as described above, a functional test of a complex logic circuit can be easily performed, and the shift register 520 for setting the internal state and the shift register 530 for reading the internal state can be shifted into one shift register. - Can be done at the register. In other words, in this semiconductor logic integrated device, when the output signal from the shift output terminal (SOT) is input as a serial input to the shift register 520, the read internal state is returned to the semiconductor logic integrated device as is by the next oscillation start signal. But it becomes possible.

As explained above, the present invention makes it possible to easily perform functional tests on complex logic integrated circuits without using an expensive LSI tester. This is very noticeable, and since the number of bits in the scan path is shifted by a pulse train that is automatically generated within the chip, errors in setting the scan path state due to an incorrect number of shifts are eliminated. Effects can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional logic integrated circuit having a scan path, FIG. 2 is a diagram showing a semiconductor logic integrated device which is an embodiment of the present invention, and FIG. 3 is a diagram showing an embodiment of the present invention. FIG. 4 is a timing chart showing the operation of the oscillator shown in FIG. 3. FIG. 1 is a diagram illustrating an example to which a semiconductor logic integrated device according to an embodiment of the present invention is applied. 101...Scan path configuration sequential circuit section, 1
02...Combination circuit section, 103...Selector switch, 104...Sequential circuit, 105...Shift control terminal, 106...Shift input terminal, 107...Clock input terminal, 108...Shift output terminal, 1
09, 110, 111...Input or output terminal, 200...Semiconductor logic integrated device, 201...
Combinational circuit section, 202... Scan path configuration sequential circuit section, 203... Oscillation circuit section, 204... Shift input terminal, 205... Shift output terminal, 20
6...Oscillation control terminal, 207...Oscillation start instruction terminal, 208...Oscillation output terminal, 301...Oscillator, 302...Counter, 306...Counter initialization control flip-flop, 401-40
5...Signal waveform, 520...Shift register for internal state setting, 521...Data input terminal, 5
30...Shift register for reading internal status,
531...Data output terminal.

Claims (1)

[Claims] 1. In a semiconductor logic integrated device having a combinational circuit section and a sequential circuit section, all of the sequential circuit sections are
1. A semiconductor logic integrated device, comprising a scan path that operates as a series of shift registers, and an oscillation circuit section that generates as many pulse trains as the number of bits in the scan path.