JPS647511B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a MNOS (metal-nitride-oxide-semiconductor) type nonvolatile memory device. Conventional MNOS type nonvolatile memory devices are mainly formed of Al gates. The reason for this is that Al
This is because by using the gate process, after forming the nitride film-oxide film portion corresponding to N--O in the MNOS structure, there is no need to perform high-temperature annealing that would degrade memory retention characteristics. However, the present inventor first replaced the Al gate with
By using a Si gate, we demonstrated an optimal cell structure different from conventional ones. (Japanese Patent Application No. 52-123479) The object of the present invention is to provide a manufacturing method for effectively forming this cell structure.

The memory cell of a conventional Al-gate MNOS device has a tri-gate structure, as shown in Figure 1, with the same Al electrode 1 in the center.
MNOS 2 and enhancement mode MOS 3 are configured on both sides in series with MNOS 2. Therefore, during readout, three gates are accessed simultaneously, and (1) the load capacitance is the sum of the gate capacitances of the three elements, and (2) the readout voltage is also applied to the gate of the MNOS element, so there is no accumulation. There were disadvantages such as the loss of information that had been recorded. In addition, in the same figure, 4
5 is a nitride film, 5 is an oxide film, 6 is a diffusion layer (source, drain), and 7 is a Si substrate. In order to improve these drawbacks, we examined the cell structure as described above, and found the optimal cell structure, which consists of a Si gate MNOS11 and a Si gate MOS11, as shown in Figure 2.
We proposed a structure in which 2 gates are formed in series with separate gates. By doing this, only the gate of the MOS mentioned above is accessed during reading, so (1) the load capacitance is only the gate capacitance of the MOS, and (2) the read voltage is not applied to the gate electrode of the MNOS. Therefore, no information is lost due to reading.

However, in order to construct such a two-element/bit cell structure, in consideration of the gate voltages of the MOS and MNOS elements, it is generally necessary to adopt a structure as shown in FIG. 3. In order to create such a structure, first a MOS structure is formed, and then a part of the gate film 20 is etched away using a photomask to form an oxide film 1 having a thickness that allows charge tunneling.
4, a nitride film 15, and a polycrystalline Si film 16. However, this method requires sufficient mask alignment margin to prevent the MNOS gate and MOS gate from shorting or to prevent the capacitance between the gates from increasing. The present invention significantly simplifies the manufacturing process by omitting the step of removing a part of the gate film by photoetching in the conventional manufacturing method and by reducing the mask alignment margin, and at the same time greatly improves the characteristics. This makes it possible to form an excellent element.

First, as shown in Figure 4a, the first layer is made of polycrystalline Si containing at least 10 ²⁰ cm ^-3 or more of phosphorus.
It constitutes the gate 19 of the MOS. Next, using this as a mask, the first gate oxide film 21 on the substrate Si 18 is selectively removed by etching to expose the substrate surface. Thereafter, a predetermined oxidation is performed in a wet atmosphere at a temperature ranging from 600 to 1000°C, and as shown in FIG. Oxide film 2 formed on doped first polycrystalline Si gate electrode 19
At least 80% or less, preferably 50% of the film thickness of 2.
An oxide film is formed as shown below. For example, such an oxide film can be heated at 850°C in a wet atmosphere.
Formed by oxidation for 20 minutes.

Next, oxide film etching is performed on the entire surface to completely remove the oxide film 21 on the Si substrate 18 and expose the surface of the substrate. Oxide film 22 on the polycrystalline Si 19
Since it is thicker than the oxide film 21 deposited on the surface of the Si substrate, it is not completely removed, and as shown in FIG.
cover.

As shown in FIG. 4d, after forming an oxide film 23 with a thickness that allows charge to tunnel on the exposed surface of the Si substrate, a nitride film 24 and a second polycrystalline Si gate 2 are formed.
5 were deposited in sequence. By adopting such a method, the photoetching step can be omitted and the mask alignment margin can be reduced, as described above. Furthermore, according to the present invention, the first polycrystalline Si19
It is possible to obtain an even smaller cell by stacking the second polycrystalline Si25 and the second polycrystalline Si25, and in that case, the breakdown voltage between the layers can be increased and the capacitance can be reduced, which is very convenient when configuring LSI (large scale integrated circuit). good. In addition, since only the first layer polycrystalline Si 19 can be covered with the thick oxide film 22', the thin oxide film 23'
This is very preferable in terms of characteristics since the polycrystalline Si layer 19 can be protected from pre-cleaning (such as Si etching may be performed) before formation.

Example 1 As shown in FIG. 5, approximately 75 nm of SiO ₂ is deposited on a P(100) Si substrate 18 after a process such as separation between elements.
A first polycrystalline Si 19 was formed thereon by a vapor phase growth method, and (P) was diffused over the entire surface of the polycrystalline Si by a diffusion method using POCl ₃ as a source gas. The concentration of P in this case was approximately 5×10 ²⁰ cm ⁻³ .
After this, the first layer of polycrystalline Si is etched by photo-etching.
The gate oxide film was selectively etched using this as a mask. After this, oxidation was performed at 850°C for 20 minutes in a wet atmosphere to form a layer of SiO ₂ of approximately 40 nm on the exposed Si substrate surface and approximately 200 nm on the polycrystalline Si.
A film was formed. After this, the SiO ₂ film on the surface of the Si substrate was removed by etching. At this time, an approximately 120 nm thick oxide film remained on the polycrystalline Si. After that, using the oxide film on the polycrystalline Si 19 as a mask, the exposed Si
After lightly etching the surface of the substrate with an etchant containing NH ₃ −H ₂ O ₂ and HCl−H ₂ O ₂ , a thin oxide film 23 of approximately 2 nm is oxidized at 850°C for 20 minutes in N ₂ diluted O ₂ . Formed and subsequently by vapor phase growth method,
A Si ₃ N ₄ film 24 was formed to a thickness of about 50 nm. Thereafter, polycrystalline Si was deposited to a thickness of about 40 nm and processed by photoetching to form a second layer (second) polycrystalline Si gate 25. Subsequently, using the second layer polycrystalline Si 25 as a mask, P ions were implanted at 1×10 ¹⁶ cm ⁻² and 90 keV to form source and drain diffusion layers 26 . At this time, since the first layer of polycrystalline Si 19 has already been doped with P and the crystal grains have increased, the P ion implantation causes the Si substrate surface 2 below the first layer gate 19 to
However, according to the present invention, about 120 nm of SiO ₂ 2 on the first layer polycrystalline Si 19 is implanted.
Because it is covered with a Si ₃ N ₄ film 24 of 2″ and 50 nm,
There is no above risk. After this, after performing almost the same process as the normal MOS process, the source
The Al wiring 28 was connected to the drain 26 or the first and second polycrystalline Si layers. By using the above method, the cell area can be reduced by approximately
30%, approximately 10% less than the device shown in Figure 3.

[Brief explanation of drawings]

1 to 3 are diagrams showing the structure of a conventional semiconductor device, FIG. 4 is a process diagram for explaining the present invention, and FIG. 5 is an example of a semiconductor device formed according to the present invention. It is a diagram. 7, 10, 18: Semiconductor substrate, 19, 25: Polycrystalline Si layer, 22'', 23: SiO ₂ layer, 24: Si ₃ N ₄
layer.

Claims (1)

[Claims] 1. A method for manufacturing a non-volatile memory device including the following steps. (1) A process of forming a SiO ₂ film on the surface of a semiconductor substrate. (2) A step of forming a first gate electrode made of polycrystalline Si containing high concentration of impurities and having a desired shape at a desired portion on the SiO ₂ film. (3) Using the first gate electrode as a mask,
The process of removing the exposed parts of the SiO ₂ film. (4) A step of performing heat treatment in an oxidizing atmosphere to form a thin SiO ₂ film on the exposed surface of the semiconductor substrate and a thick SiO ₂ film covering the first gate electrode. (5) A step of removing the thin SiO ₂ film while leaving the thick SiO ₂ film. (6) A step of forming an SiO ₂ film having a thickness that allows charge to tunnel on the exposed surface of the semiconductor substrate. (7) Process of coating the entire surface with Si ₃ N ₄ film. (8) A step of forming a second gate electrode having a desired shape at a desired portion on the Si ₃ N ₄ film.