JPS647544B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AGC circuit, and more particularly to an AGC circuit applied to television receivers, video signal magnetic recording and reproducing devices, and the like.

AGC applied to devices that handle video signals, such as television receivers and video signal magnetic recording and reproducing devices.
One such circuit is an AGC circuit that detects the amplitude of a synchronization signal that does not change depending on the brightness of the image and controls the amplitude of the video signal so that this remains constant.
This is called a sink AGC circuit, and to explain its outline, as shown in Figure 1, the video signal S ₁ is
applied to the AGC amplifier 3 via the input terminal 1,
The output of this AGC amplifier 3 is supplied to a color signal removal circuit 4, where the color signal is removed and a luminance signal Y
Only the ingredients. The signal is then input to a sync separator 6 and a sync chip clamper 5. As shown in Fig. 2, the luminance signal Y has a horizontal synchronizing signal portion P _H having a synchronizing signal tip level V _C and a signal width T _S during 1H from the beginning of one scanning line to the beginning of the next scanning line.
Immediately thereafter, the pedestal period T _P is set to the pedestal level V _P and the video signal portion is subsequently formed. The synchronization separator 6 separates the synchronization signal, and the sync chip clamper 5 uses the separated synchronization signal to divide the signal width T _S into
The luminance signal Y is clamped to a constant level. That is, the tip of the sync signal portion (sync tip) of the luminance signal Y is clamped to a constant level. The output of the sync chip clamp device 5 is supplied to the AGC detector 8. A detection pulse BG formed by a synchronization signal delayed to the pedestal position by the detection pulse generator 7 is further applied to the AGC detector 8, and the pedestal level V of the luminance signal Y is detected during the pedestal period T _{P. P} and the reference voltage V _ref are compared, and the difference voltage is detected. This detection output is applied to the control terminal of the AGC amplifier 3 via the sink AGC filter 9, and its gain is controlled.

A concrete example of the AGC detector 8 will be explained with reference to _FIG . During the period, the video signal and the transistor
The difference from the reference voltage V _ref forming the base bias voltage of Q ₂ is output to the collectors of transistors Q ₃ and Q ₄ . The collector current _I1 of the transistor _Q3 is connected to the current mirror circuit 1 via the terminal 10a.
0, and the collector current I ₂ of the transistor Q ₄ flows into the current mirror circuit 10 via the sink AGC filter 9 and the terminal 10b. At this time,
Approximately the same current as the current flowing through terminal 10a flows through terminal 10.
flows through b. Therefore, if the DC current amplification factor hfe of the transistor Q ₅ is large, the current (I ₁ - I ₂ ) which is the difference between the collector currents of the transistors Q ₃ and Q ₄ flows into the sink AGC filter 9 (I ₁ <When I ₂ ),
Alternatively, the current difference (I ₁ −I ₂ ) flows out from the capacitor C ₁ of the sink AGC filter 9 (when I ₁ >I ₂ ) and flows through the transistor Q ₅ . In a balanced state where the collector currents I ₁ and I ₂ of the transistors Q ₃ and Q ₄ are equal, the current flowing to the terminal _10b is equal to the collector current I ₂ of the transistor Q ₄ . Almost no current flows. Also, of course, the detection pulse BG
During the period when the transistor is not supplied,
Since Q ₁ to _{Q 5} are all turned off, there is no fluctuation in the charge charged in the capacitor C ₁ of the sink AGC filter 9.

When the AGC control voltage is large and the gain of the AGC amplifier circuit 3 is controlled to be small, when a video signal with small amplitude arrives, at that moment
The amplitude of the output of AGC amplifier 3 becomes very small.
In this state, the synchronization separator 6 may not work properly, and the synchronization signal may not be separated, so the detection pulse BG is not generated, and the AGC detector 8 does not work properly. For example, as the synchronous separator 6, the second
Clamp the tip of the sync signal part _P''H shown in the figure at the clamp level V _A , and then set the sync signal tip level to
When applying a method in which V _C is set to (V _C = V _A ) and then clipped at a constant clip level V _B to obtain a synchronization signal _P''H , the output amplitude of AGC amplifier 3 as described above is When the amplitude of the video signal becomes extremely small and the amplitude of the video signal exists between the clamp level V _A and the clip level V _B for the entire horizontal scanning period, all signals are regarded as synchronous signals and cannot be separated. , AGC detector 8
Since the capacitor C1 of the sink AGC filter 9 does not operate, the charge in the capacitor _C1 of the sink AGC filter 9 does not change, and the AGC control voltage is still maintained immediately controlling the AGC amplifier 3 to the minimum gain, resulting in a so-called lockout state.

In order to eliminate this drawback, it has been proposed to connect a resistor in parallel to the capacitor _C1 to release the lockout, but this will reduce the detection sensitivity of the AGC detector 8, resulting in insufficient AGC functionality. It has its drawbacks.

An object of the present invention is to provide an AGC circuit that allows sink AGC even when synchronous separation is not possible.

The present invention is designed to discharge the charge of a capacitor charged by the detection output signal of the AGC detector using the output of the synchronous separation circuit.

Hereinafter, one embodiment of the AGC circuit according to the present invention will be described in detail with reference to the drawings. In FIG. 3, 12 is a synchronous separation output bypass circuit. The synchronous separation output bypass circuit is formed of a resistor R ₁ , one end 12 a of this resistor R ₁ is connected to the emitter of the emitter follower transistor Q ₆ for the synchronous separator 6 buffer, and the other end 12 a is connected to the transistor of the current mirror circuit 10 .
It is connected to the base of _Q5 . In addition, in the figure, X′ and
Y' and Y indicate that they are respectively connected in this embodiment.

Here, the signal width T _S of the horizontal synchronization part P _H in Fig. 2 is
During the period, the current I _S released from the capacitor C ₁ is I _S = V _S − V _J1 / R ₁ + R ₂ (1) where, V _S is the synchronizing signal generated at the emitter of the transistor Q ₆ . Peak voltage value.

V _J1 ; is a diode due to the current I ₃ flowing through the resistor R ₂
Voltage drop of _D1 , hfe of transistor _Q5 ≒1 As shown in equation (1), the charge of capacitor _C1 is discharged.

Figure 2 Pedestal period of horizontal synchronization signal part P _H
The current I _B flowing into the capacitor C ₁ during the period T _B of the detection pulse BG generated at T _P is determined as follows. That is, R ₂ I′ ₃ +V _J2 = (R ₁ + R ₄ ) (I ₁ − I′ ₃ ) ………(2) However, I′ ₃ is the current flowing through the resistor R ₂ and the terminal 10a.
and 10b are equal.

V _J2 is a diode due to the current I′ ₃ flowing through the resistor R ₂
The voltage drop of D ₁ is expressed as equation (2). And since I _B = I' ₃ − I ₂ , I ₁
= I ₂ , I _B becomes I _B =−(R ₂ I ₁ + V _J2 /R ₁ + R ₂ + R ₄ )……(3) (3) formula. Therefore, the charges in the capacitor _C1 are released during the period of the synchronizing signal width _TS , and are accumulated during the pulse period _TB of the detection pulse BG, so that the charges mutually cancel each other out. In addition, the current I _S discharged from the capacitor C ₁ during the period of the synchronization signal width T _S and the current I B flowing into the capacitor C ₁ during the period T _B of the detection pulse BG are I _S T _{S +} I _B T _B = O ......(4) If formula (4) is satisfied, I ₁ = I ₂ is maintained under normal conditions. Also, it is desirable that the currents I _S and I _B of the capacitor C ₁ are sufficiently small compared to I ₁ and I ₂ , and for this purpose, the resistance value of the resistor R ₁ of the synchronous separation output bypass circuit 12 is made large, and Peak voltage value of synchronization signal V _S
Alternatively, the value of the resistor R ₄ is selected so as to satisfy the above equation (4).

As mentioned above, when the sync separator 6 receives a video signal having a sync signal part or a sync signal part that is distorted and unrecognizable, the sync separator 6 identifies all of them as sync signals and detects the presence of the sync signal. The transistor outputs a high level signal for a period
Set the emitter potential of _Q6 to V _S. This allows current to flow through the current mirror circuit 10 and extracts the charge from the capacitor _C1 , so that even if a lockout occurs, the normal state can be restored. Also, as mentioned above, if the circuit is set to satisfy equation (4), the detection output will not deviate because it will settle into the state of I ₁ = I ₂ (a resistor should be connected in parallel to capacitor C ₁ ). I ₁ > I ₂
(The detection output will deviate because it will settle in the state of ).

The AGC circuit according to the present invention is configured to include charge control means for controlling the charge of the capacitor that accumulates the AGC detection output according to the signal obtained by the synchronization separation means, so regardless of the waveform and interval of the synchronization signal. It has the feature of performing AGC operation. Therefore, it is possible to prevent the occurrence of a lockout state in which the AGC operation is interrupted.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional AGC circuit, Figure 2 is a block diagram of a conventional AGC circuit.
The figure is an explanatory diagram of the synchronization signal, and Figure 3 is the AGC of the present invention.
1 is a circuit diagram showing a partial block diagram of an embodiment of the circuit; FIG. In the figure, numeral 3 is the AGC amplifier, 6 is the synchronous separator,
9 is a sink AGC filter, 10 is a current mirror circuit, 12 is a synchronous separation output bypass circuit, Q ₁
~ _Q6 is a transistor and _D1 is a diode.

Claims (1)

[Claims] 1 Sync separation means for separating a sync signal from a video signal; sync chip clamping means for clamping the tip of a sync signal portion (sync chip) to a constant level based on the sync signal separated by the sync separation unit; A detection means for detecting the pedestal level of the video signal, an AGC amplification means for controlling the gain of the input video signal by the detection output obtained by the detection means, and an output end of the detection means and a control input end of the AGC amplification means. A capacitor is connected at one end in the path and stores the detected output of the detection means, and is connected between the output end of the synchronous separation means and this capacitor, and the output of the capacitor is connected based on the synchronous signal output separated by the synchronous separation means. An AGC circuit characterized by comprising a charge discharging means for discharging accumulated charges.