JPS648392B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a form set error detection device.

When reading characters with an optical character reader (hereinafter referred to as OCR), form size and other reading control data (hereinafter referred to as FC) must be given to the OCR in advance.

OCR recognizes characters according to this FC, so if you accidentally set a form with a size different from the size specified by FC, you may not be able to obtain a satisfactory recognition result. Can not.

Therefore, if a document with a size different from the document size specified by the FC is mistakenly set, it is desirable to detect this as a document setting error before the OCR starts the recognition operation.

However, while there has been an OCR that can detect when the size of the actually set form is significantly different from the size of the form specified by FC,
If the size of the form is slightly different from the size specified by , it can be detected as a form set error.
OCR did not exist.

The present invention has been made in view of the above points, and its purpose is to prevent errors in cases where a document with a size different from that specified by the FC is set by mistake, even if the difference is small. It is an object of the present invention to provide a form setting error detection device that can reliably detect this as a form setting error.

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

1 and 2 schematically show a form setting error detection device according to an embodiment of the present invention, in which FIG. 1 is a plan view showing the mechanical part, and FIG. 2 is a plan view showing the electrical part. FIG. 3 is a block diagram showing the parts.

In the figure, 1 is a transport path, 2 is a form, 3 is a reading head,
Reference numeral 4 indicates a running rail, 5 an edge detection circuit, 6 a timing counter, and 7 a control means.

The conveyance path 1 is for conveying the form 2 line by line, and the surface of the conveyance path 1 is black. Also, form 2
The surface of is white.

The reading head 3 is for capturing an optical image of the form 2 as a video signal. The reading head 3 is equipped with a light source 31 and a light receiving element 32 such as a CCD, and scans the character line in the character height direction while traveling from left to right (in the conveying direction) on the traveling rail 4. is being done.

Also, scanning in the character height direction by the reading head 3 is
10bit/mm is 12.8mm, that is, 12.8 bits.

It is assumed that the reading head 3 travels on the running rail 4 from left to right every time a timing pulse is supplied to a pulse motor (not shown).

The edge detection circuit 5 is a circuit that detects the left edge and right edge of the form 2 using the video signal a supplied from the reading head 3 and the scanning clock pulse b.

FIG. 3 shows the edge detection circuit 5 in more detail, 501 is an AND gate, 502 is a counter, 503 is a shift register, 504, 50
5,508,509 is an inverter, 506,51
0 indicates an AND gate, and 507 and 511 indicate flip-flops.

AND gate 501 is for calculating the AND of video signal a and scanning clock pulse b.
The scanning clock pulse b is supplied 128 times for each scan of the reading head 3 in the character height direction. Further, the AND gate output pulse C is supplied to the counter 502.

A counter 502 is for counting AND gate output pulses C. The contents of the counter 502 are cleared every time the reading head 3 scans in the character height direction, and the counter output d is supplied to the shift register each time.

Note that the counter output d is calculated at the time when one scan in the character height direction is completed by the reading head 3.
The content of the counter 502 is the threshold value (here, form 2
Set it to "100" considering the above noise, etc.)
If it exceeds this value, it will be "logic 1", and if it is less than that, it will be "logic 0".

The shift register 503 is used to shift the counter output d every time the reading head 3 scans in the character height direction.

Inverters 504 and 505 are shift registers 5
This is for inverting the lower two bits of 03.

AND gate 506 is inverter 504, 50
5 and the upper two bits of the shift register 503.

AND gate output E is flip-flop 507
is supplied to.

Flip-flop 507 has an AND gate output E
This is a circuit that is set when the signal becomes "logic 1". When set, the flip-flop 507 outputs the first edge detection signal F to the timing counter 6.
It is designed to supply

Inverters 508 and 509 are shift register 5
This is to invert the upper two bits of 03.

AND gate 510 is inverter 508, 50
This is for calculating the logical product of the lower two bits of the output of shift register 503 and the first edge detection signal F. AND gate output G is supplied to flip-flop 511.

Flip-flop 511 is an AND gate elution G
This is a circuit that is set when the signal becomes "logic 1". By being set, the flip-flop 511 outputs the second edge detection signal H to the control means 7.
It is designed to supply

The timing counter 6 is for counting timing pulses I (pulses supplied to the pulse motor for driving the reading head 3) synchronized with the running of the reading head 3. The contents of the timing counter 6 are cleared at the rising timing of the first edge detection signal F.

When the second edge detection signal H is supplied, the control means 10 reads out the contents of the timing counter 6.
It is compared with a predetermined value specified by FC, and if the difference exceeds an allowable value, a form set error detection signal J is output.

Next, referring to FIG. 4, FIG. 5, and FIG. 6, a document set error detection device according to the present invention is provided.
Explain how OCR works.

When the OCR is activated, an FC instructing the form size and other information is given to the control means 7.

A form 2 is taken out from a card hopper (not shown) and conveyed on a conveyance path 1.

At this time, the reading head 3 is also at the home position (transport path 1
left end).

Also, the clear signal K is sent to the flip-flop 50.
7,511.

The reading head 3 returned to the home position travels to the right on the traveling rail 4 in synchronization with the timing pulse I, and scans the conveyance path 1 or the form 2 in the character height direction while traveling. I will do it.

As the reading head 3 scans, a video signal a is supplied from the reading head 3 to one input of the AND gate 501.

The other input of the AND gate 501 is supplied with the scanning clock b, which is set per one scan by the reading head 3.
It has been supplied 128 times.

Therefore, every time the scanning clock b is supplied to the AND gate 501 when the video signal a is at a high level, the AND gate output pulse C is sent to the counter 502.
will be supplied.

The counter 502 outputs an AND gate output pulse C every time the reading head 3 scans in the character height direction.
is counted, and if the counted value exceeds the threshold (i.e. 101
If the count exceeds 100, the counter output d is set to "logic 1"; if the count is 100 or less, the counter output d is set to "logic 0".

Considering the video signal a here, when the reading head 3 is scanning the conveyance path 1, the video signal a is at a high level except for the noise part.
On the other hand, it can be seen that when the reading head 3 is scanning the form 2, the level is low except for the noise portion and the character portion.

Therefore, when the reading head 3 is scanning the conveyance path 1, the counter output d is "logic 1" and the form 2.
When scanning above, it becomes "logic 0".

The counter output d supplied to the shift register 503 is shifted every time the reading head 3 scans one scan, so when the reading head 3 traveling on the running rail 4 has not yet reached the left edge of the form 2, the counter output d is sent to the shift register 503. The contents of 503 are all "logic 1".

As a result, the AND gate output E remains at "logic 0".

The scanning line of the reading head 3 is as shown in FIG.
From this point on, the counter output d becomes "logic 0".

Therefore, when the scanning line of the reading head 3 reaches the left edge of the form 2, the contents of the shift register 503 become "logic 0" sequentially starting from the lower bit.

In this way, the lower two of the shift register 503
When the bit becomes a "logic 0", the AND gate output E becomes a "logic 1" and the flip-flop 507 is set.

When the flip-flop 507 is set, the timing counter 6 is output from the flip-flop 507.
A first edge detection signal F is supplied to the first edge detection signal F.

The timing counter 6 is reset at the timing when the first edge detection signal F rises.

Timing pulses I synchronized with the running of the reading head 3 are supplied to the timing counter 6, and the timing counter 6 counts the timing pulses I.

On the other hand, the reading head 3 moves further to the right as the reading operation progresses.

As the reading head 3 moves forward, the contents of the shift register 503 become "logic 0" starting from the lower bits, and eventually all bits become "logic 0".

When the reading head 3 reaches the right edge of the form 2 as shown in FIG. 6, the counter output d becomes "logic 1" from this point on.

Therefore, when the reading head 3 reaches the right edge of the form 2, the contents of the shift register 503 become "logic 1" sequentially starting from the lower bit.

In this way, when the lower two bits of shift register 503 become "logic 1", AND gate output G becomes "logic 1", and as a result, flip-flop 511 is set.

When the flip-flop 511 is set, the second edge detection signal H is supplied to the control means 7.

Upon receiving the second edge detection signal H, the control means 7 checks the contents of the timing counter 6.

The contents of the timing counter 6 are stored in the read head 3.
shows the number of timing pulses I supplied to the pulse motor and timing counter 6 for driving the reading head 2 after reaching the left edge of the form 2 until reaching the right edge of the form 2. There is.

Since the moving distance of the reading head per timing pulse I is determined, the control means 7 compares the contents of the timing counter 6 with a predetermined value specified by the FC to check whether the size of the form 2 is correct. You can know what's going on.

That is, if the absolute value of the difference between the content of the timing counter 6 and the predetermined value specified by FC exceeds the allowable range, the control means outputs the form set error signal J, and if it is within the allowable range, the control means outputs the form set error signal J. Performs a row read operation.

In the above description, the reading head 3 is moved from left to right, but it may be moved from right to left.

Moreover, the form set error detection device according to the present invention is used.
If the OCR is operated until it finishes reading each sheet, it is also possible to detect tears in the sheet.

As explained above, by using the form setting error detection device according to the present invention, it is possible to accurately measure the width of the form for each reading line, so that errors in setting the form, tears in the form, etc. can be detected accurately.

[Brief explanation of drawings]

FIG. 1 is a plan view of the mechanical part of the form setting error detection device. FIG. 2 is a block diagram of the electrical part of the form set error detection device. FIG. 3 is a block diagram of the edge detection circuit. Figure 4 is an OCR operation flowchart. 5 and 6 are front views of the mechanical parts of the form setting error detection device. 3...Reading head, 5...Edge detection circuit, 5
01,506,509...and gate, 502
... Counter, 503 ... Shift register, 50
4,505,508,509...Inverter, 5
07,511...Flip-flop, a...Video signal, F...First edge detection signal, H...Second
Edge detection signal, I...timing pulse, J...
...Error detection signal.

Claims (1)

[Scope of Claims] 1. A reading head that runs perpendicular to the conveying direction of the form every time a timing pulse is supplied and scans the form using a scanning clock pulse; outputting a first edge detection signal indicating detection of an edge on one side of the form based on the video signal from the reading head that changes as the reading head passes, and the scanning clock pulse; and when the reading head passes from the form side to the transport path side; an edge detection circuit for outputting a second edge detection signal indicative of another edge detection of a document based on the varying video signal from the read head and the scan clock pulse; and the first edge detection signal supplied from the edge detection circuit. a timing counter that is set by a signal and counts timing pulses that are synchronized with the running of the reading head; and when the second edge detection signal is supplied from the edge detection circuit, the output of the timing counter is received, and the contents of the timing counter are counted. and control means for outputting an error detection signal when the absolute value of the difference between the set value and the predetermined value exceeds a permissible range.